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Revert r191049/r191059 as it can produce wrong code (see PR17975).

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It has already been reverted on the 3.4 branch in r196521.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206311 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Robert Lougher 2014-04-15 18:34:24 +00:00
parent 2bbc5a7e2c
commit 4634a9ba1e
3 changed files with 4 additions and 97 deletions
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21
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -3555,27 +3555,6 @@ SDNode *DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos,
HasPos ? Pos : Neg).getNode();
}
// fold (or (shl (*ext x), (*ext y)),
// (srl (*ext x), (*ext (sub 32, y)))) ->
// (*ext (rotl x, y)) or (*ext (rotr x, (sub 32, y)))
//
// fold (or (shl (*ext x), (*ext (sub 32, y))),
// (srl (*ext x), (*ext y))) ->
// (*ext (rotr x, y)) or (*ext (rotl x, (sub 32, y)))
if (Shifted.getOpcode() == ISD::ZERO_EXTEND ||
Shifted.getOpcode() == ISD::ANY_EXTEND) {
SDValue InnerShifted = Shifted.getOperand(0);
EVT InnerVT = InnerShifted.getValueType();
bool HasPosInner = TLI.isOperationLegalOrCustom(PosOpcode, InnerVT);
if (HasPosInner || TLI.isOperationLegalOrCustom(NegOpcode, InnerVT)) {
if (matchRotateSub(InnerPos, InnerNeg, InnerVT.getSizeInBits())) {
SDValue V = DAG.getNode(HasPosInner ? PosOpcode : NegOpcode, DL,
InnerVT, InnerShifted, HasPosInner ? Pos : Neg);
return DAG.getNode(Shifted.getOpcode(), DL, VT, V).getNode();
}
}
}
return nullptr;
}

4
test/CodeGen/ARM64/regress-interphase-shift.ll
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@ -4,6 +4,10 @@
; on the phase of legalization, which led to the creation of an unexpected and
; unselectable "rotr" node: (i32 (rotr i32, i64)).
; FIXME: This test is xfailed because it relies on an optimization that has
; been reverted (see PR17975).
; XFAIL: *
define void @foo(i64* nocapture %d) {
; CHECK-LABEL: foo:
; CHECK: rorv

76
test/CodeGen/X86/rotate3.ll
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@ -1,76 +0,0 @@
; Check that (or (shl x, y), (srl x, (sub 32, y))) is folded into (rotl x, y)
; and (or (shl x, (sub 32, y)), (srl x, r)) into (rotr x, y) even if the
; argument is zero extended. Fix for PR16726.
; RUN: llc < %s -march=x86-64 -mcpu=corei7 | FileCheck %s
define zeroext i8 @rolbyte(i32 %nBits_arg, i8 %x_arg) nounwind readnone {
entry:
%tmp1 = zext i8 %x_arg to i32
%tmp3 = shl i32 %tmp1, %nBits_arg
%tmp8 = sub i32 8, %nBits_arg
%tmp10 = lshr i32 %tmp1, %tmp8
%tmp11 = or i32 %tmp3, %tmp10
%tmp12 = trunc i32 %tmp11 to i8
ret i8 %tmp12
}
; CHECK: rolb %cl, %{{[a-z0-9]+}}
define zeroext i8 @rorbyte(i32 %nBits_arg, i8 %x_arg) nounwind readnone {
entry:
%tmp1 = zext i8 %x_arg to i32
%tmp3 = lshr i32 %tmp1, %nBits_arg
%tmp8 = sub i32 8, %nBits_arg
%tmp10 = shl i32 %tmp1, %tmp8
%tmp11 = or i32 %tmp3, %tmp10
%tmp12 = trunc i32 %tmp11 to i8
ret i8 %tmp12
}
; CHECK: rorb %cl, %{{[a-z0-9]+}}
define zeroext i16 @rolword(i32 %nBits_arg, i16 %x_arg) nounwind readnone {
entry:
%tmp1 = zext i16 %x_arg to i32
%tmp3 = shl i32 %tmp1, %nBits_arg
%tmp8 = sub i32 16, %nBits_arg
%tmp10 = lshr i32 %tmp1, %tmp8
%tmp11 = or i32 %tmp3, %tmp10
%tmp12 = trunc i32 %tmp11 to i16
ret i16 %tmp12
}
; CHECK: rolw %cl, %{{[a-z0-9]+}}
define zeroext i16 @rorword(i32 %nBits_arg, i16 %x_arg) nounwind readnone {
entry:
%tmp1 = zext i16 %x_arg to i32
%tmp3 = lshr i32 %tmp1, %nBits_arg
%tmp8 = sub i32 16, %nBits_arg
%tmp10 = shl i32 %tmp1, %tmp8
%tmp11 = or i32 %tmp3, %tmp10
%tmp12 = trunc i32 %tmp11 to i16
ret i16 %tmp12
}
; CHECK: rorw %cl, %{{[a-z0-9]+}}
define i64 @roldword(i64 %nBits_arg, i32 %x_arg) nounwind readnone {
entry:
%tmp1 = zext i32 %x_arg to i64
%tmp3 = shl i64 %tmp1, %nBits_arg
%tmp8 = sub i64 32, %nBits_arg
%tmp10 = lshr i64 %tmp1, %tmp8
%tmp11 = or i64 %tmp3, %tmp10
ret i64 %tmp11
}
; CHECK: roll %cl, %{{[a-z0-9]+}}
define zeroext i64 @rordword(i64 %nBits_arg, i32 %x_arg) nounwind readnone {
entry:
%tmp1 = zext i32 %x_arg to i64
%tmp3 = lshr i64 %tmp1, %nBits_arg
%tmp8 = sub i64 32, %nBits_arg
%tmp10 = shl i64 %tmp1, %tmp8
%tmp11 = or i64 %tmp3, %tmp10
ret i64 %tmp11
}
; CHECK: rorl %cl, %{{[a-z0-9]+}}