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ARMEB: Fix trunc store for vector types
Reviewed at http://reviews.llvm.org/D4135 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211010 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -8464,7 +8464,8 @@ static SDValue PerformSTORECombine(SDNode *N,
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SDLoc DL(St);
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SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal);
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SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
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for (unsigned i = 0; i < NumElems; ++i) ShuffleVec[i] = i * SizeRatio;
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for (unsigned i = 0; i < NumElems; ++i)
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ShuffleVec[i] = TLI.isBigEndian() ? (i+1) * SizeRatio - 1 : i * SizeRatio;
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// Can't shuffle using an illegal type.
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if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
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26
test/CodeGen/ARM/big-endian-neon-trunc-store.ll
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26
test/CodeGen/ARM/big-endian-neon-trunc-store.ll
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@ -0,0 +1,26 @@
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; RUN: llc < %s -mtriple armeb-eabi -mattr v7,neon -o - | FileCheck %s
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define void @vector_trunc_store_2i64_to_2i16( <2 x i64>* %loadaddr, <2 x i16>* %storeaddr ) {
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; CHECK-LABEL: vector_trunc_store_2i64_to_2i16:
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; CHECK: vmovn.i64 [[REG:d[0-9]+]]
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; CHECK: vrev32.16 [[REG]], [[REG]]
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; CHECK: vuzp.16 [[REG]], [[REG2:d[0-9]+]]
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; CHECK: vrev32.16 [[REG]], [[REG2]]
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%1 = load <2 x i64>* %loadaddr
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%2 = trunc <2 x i64> %1 to <2 x i16>
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store <2 x i16> %2, <2 x i16>* %storeaddr
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ret void
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}
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define void @vector_trunc_store_4i32_to_4i8( <4 x i32>* %loadaddr, <4 x i8>* %storeaddr ) {
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; CHECK-LABEL: vector_trunc_store_4i32_to_4i8:
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; CHECK: vmovn.i32 [[REG:d[0-9]+]]
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; CHECK: vrev16.8 [[REG]], [[REG]]
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; CHECK: vuzp.8 [[REG]], [[REG2:d[0-9]+]]
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; CHECK: vrev32.8 [[REG]], [[REG2]]
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%1 = load <4 x i32>* %loadaddr
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%2 = trunc <4 x i32> %1 to <4 x i8>
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store <4 x i8> %2, <4 x i8>* %storeaddr
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ret void
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}
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