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change the addressing mode of the str instruction to reg+imm

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29571 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2006-08-08 20:35:03 +00:00
parent d9ea017494
commit 46adf8119d
4 changed files with 13 additions and 7 deletions
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4
lib/Target/ARM/ARMInstrInfo.cpp
View File

@ -22,6 +22,10 @@ ARMInstrInfo::ARMInstrInfo()
: TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])) {
}
const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
return &ARM::IntRegsRegClass;
}
/// Return true if the instruction is a register to register move and
/// leave the source and dest operands in the passed parameters.
///

4
lib/Target/ARM/ARMInstrInfo.h
View File

@ -31,6 +31,10 @@ public:
///
virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
/// getPointerRegClass - Return the register class to use to hold pointers.
/// This is used for addressing modes.
virtual const TargetRegisterClass *getPointerRegClass() const;
/// Return true if the instruction is a register to register move and
/// leave the source and dest operands in the passed parameters.
///

6
lib/Target/ARM/ARMInstrInfo.td
View File

@ -67,9 +67,9 @@ def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
"ldr $dst, $addr",
[(set IntRegs:$dst, (load iaddr:$addr))]>;
def str : InstARM<(ops IntRegs:$src, IntRegs:$addr),
"str $src, [$addr]",
[(store IntRegs:$src, IntRegs:$addr)]>;
def str : InstARM<(ops IntRegs:$src, memri:$addr),
"str $src, $addr",
[(store IntRegs:$src, iaddr:$addr)]>;
def movrr : InstARM<(ops IntRegs:$dst, IntRegs:$src),
"mov $dst, $src", []>;

6
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -135,10 +135,8 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
//sub sp, sp, #NumBytes
BuildMI(MBB, MBBI, ARM::subri, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes);
//add ip, sp, #NumBytes - 4
BuildMI(MBB, MBBI, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(NumBytes - 4);
//str lr, [ip]
BuildMI(MBB, MBBI, ARM::str, 1, ARM::R14).addReg(ARM::R12);
//str lr, [sp, #NumBytes - 4]
BuildMI(MBB, MBBI, ARM::str, 2, ARM::R14).addImm(NumBytes - 4).addReg(ARM::R13);
}
void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,