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Remove the rest of the *_sfp Neon instruction patterns.
Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions. This change made a big difference in the code generated for the CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing a fine job, but some instructions that were previously moved outside the loop are not moved now. It's using fewer VFP registers now, which is generally a good thing, so I think the estimates for register pressure changed and that affected the LICM behavior. Since that isn't obviously wrong, I've just changed the test file. This completes the work for Radar 8711675. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121730 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
parent
0e6d540d17
commit
4711d5cda3
@ -58,8 +58,6 @@ static const ARM_MLxEntry ARM_MLxTable[] = {
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{ ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
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{ ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
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{ ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
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{ ARM::VMLAfd_sfp, ARM::VMULfd_sfp, ARM::VADDfd_sfp, false, false },
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{ ARM::VMLSfd_sfp, ARM::VMULfd_sfp, ARM::VSUBfd_sfp, false, false },
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{ ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
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{ ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
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{ ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
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@ -1667,7 +1667,7 @@ def SubReg_i32_lane : SDNodeXForm<imm, [{
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// Instruction Classes
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//===----------------------------------------------------------------------===//
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// Basic 2-register operations: single-, double- and quad-register.
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// Basic 2-register operations: double- and quad-register.
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class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
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bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
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string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
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@ -1736,13 +1736,7 @@ class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
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(ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
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"$src1 = $Vd, $src2 = $Vm", []>;
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// Basic 3-register operations: single-, double- and quad-register.
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class N3VS<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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string OpcodeStr, string Dt>
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: N3V<op24, op23, op21_20, op11_8, 0, op4,
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(outs DPR_VFP2:$Vd), (ins DPR_VFP2:$Vn, DPR_VFP2:$Vm), N3RegFrm,
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IIC_VBIND, OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", []>;
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// Basic 3-register operations: double- and quad-register.
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class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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InstrItinClass itin, string OpcodeStr, string Dt,
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ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
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@ -1912,13 +1906,7 @@ class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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let isCommutable = 0;
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}
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// Multiply-Add/Sub operations: single-, double- and quad-register.
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class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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InstrItinClass itin, string OpcodeStr, string Dt>
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: N3V<op24, op23, op21_20, op11_8, 0, op4, (outs DPR_VFP2:$Vd),
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(ins DPR_VFP2:$src1, DPR_VFP2:$Vn, DPR_VFP2:$Vm), N3RegFrm, itin,
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OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", []>;
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// Multiply-Add/Sub operations: double- and quad-register.
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class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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InstrItinClass itin, string OpcodeStr, string Dt,
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ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
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@ -4678,83 +4666,47 @@ def VTBX4Pseudo
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class N2VSPat<SDNode OpNode, NeonI Inst>
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: NEONFPPat<(f32 (OpNode SPR:$a)),
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(EXTRACT_SUBREG
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(v2f32 (COPY_TO_REGCLASS
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(Inst (INSERT_SUBREG
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(v2f32 (COPY_TO_REGCLASS (Inst
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(INSERT_SUBREG
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(v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
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SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
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class N3VSPat<SDNode OpNode, NeonI Inst>
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: NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
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(EXTRACT_SUBREG (v2f32
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(Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
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SPR:$a, ssub_0),
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(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
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SPR:$b, ssub_0))),
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ssub_0)>;
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(EXTRACT_SUBREG
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(v2f32 (COPY_TO_REGCLASS (Inst
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(INSERT_SUBREG
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(v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
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SPR:$a, ssub_0),
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(INSERT_SUBREG
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(v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
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SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
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class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
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: NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
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(EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
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SPR:$acc, ssub_0),
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(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
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SPR:$a, ssub_0),
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(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
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SPR:$b, ssub_0)),
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ssub_0)>;
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(EXTRACT_SUBREG
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(v2f32 (COPY_TO_REGCLASS (Inst
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(INSERT_SUBREG
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(v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
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SPR:$acc, ssub_0),
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(INSERT_SUBREG
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(v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
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SPR:$a, ssub_0),
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(INSERT_SUBREG
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(v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
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SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
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// These need separate instructions because they must use DPR_VFP2 register
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// class which have SPR sub-registers.
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// Vector Add Operations used for single-precision FP
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let neverHasSideEffects = 1 in
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def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32">;
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def : N3VSPat<fadd, VADDfd_sfp>;
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// Vector Sub Operations used for single-precision FP
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let neverHasSideEffects = 1 in
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def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32">;
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def : N3VSPat<fsub, VSUBfd_sfp>;
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// Vector Multiply Operations used for single-precision FP
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let neverHasSideEffects = 1 in
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def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32">;
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def : N3VSPat<fmul, VMULfd_sfp>;
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// Vector Multiply-Accumulate/Subtract used for single-precision FP
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// vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
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// we want to avoid them for now. e.g., alternating vmla/vadd instructions.
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let neverHasSideEffects = 1 in
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def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32">;
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def : N3VSMulOpPat<fmul, fadd, VMLAfd_sfp>,
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def : N3VSPat<fadd, VADDfd>;
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def : N3VSPat<fsub, VSUBfd>;
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def : N3VSPat<fmul, VMULfd>;
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def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
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Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
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let neverHasSideEffects = 1 in
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def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32">;
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def : N3VSMulOpPat<fmul, fsub, VMLSfd_sfp>,
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def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
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Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
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// Vector Absolute used for single-precision FP
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def : N2VSPat<fabs, VABSfd>;
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// Vector Negate used for single-precision FP
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def : N2VSPat<fneg, VNEGfd>;
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// Vector Maximum used for single-precision FP
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let neverHasSideEffects = 1 in
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def VMAXfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$Vd),
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(ins DPR_VFP2:$Vn, DPR_VFP2:$Vm), N3RegFrm, IIC_VBIND,
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"vmax", "f32", "$Vd, $Vn, $Vm", "", []>;
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def : N3VSPat<NEONfmax, VMAXfd_sfp>;
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// Vector Minimum used for single-precision FP
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let neverHasSideEffects = 1 in
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def VMINfd_sfp : N3V<0, 0, 0b10, 0b1111, 0, 0, (outs DPR_VFP2:$Vd),
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(ins DPR_VFP2:$Vn, DPR_VFP2:$Vm), N3RegFrm, IIC_VBIND,
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"vmin", "f32", "$Vd, $Vn, $Vm", "", []>;
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def : N3VSPat<NEONfmin, VMINfd_sfp>;
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// Vector Convert between single-precision FP and integer
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def : N3VSPat<NEONfmax, VMAXfd>;
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def : N3VSPat<NEONfmin, VMINfd>;
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def : N2VSPat<arm_ftosi, VCVTf2sd>;
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def : N2VSPat<arm_ftoui, VCVTf2ud>;
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def : N2VSPat<arm_sitof, VCVTs2fd>;
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@ -15,9 +15,6 @@ bb.nph: ; preds = %bb5
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; Loop preheader
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; CHECK: vmov.f32
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; CHECK: vsub.f32
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; CHECK: vadd.f32
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; CHECK: vmul.f32
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bb7: ; preds = %bb9, %bb.nph
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%s1.02 = phi float [ undef, %bb.nph ], [ %35, %bb9 ] ; <float> [#uses=3]
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%tmp79 = add i32 undef, undef ; <i32> [#uses=1]
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@ -73,8 +70,6 @@ bb8: ; preds = %bb8, %bb7
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br i1 %34, label %bb8, label %bb9
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bb9: ; preds = %bb8
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; CHECK: %bb9
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; CHECK: vmov.f32
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%35 = fadd float 0.000000e+00, undef ; <float> [#uses=1]
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br label %bb7
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}
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@ -1613,11 +1613,6 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
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Name == "VNEGScc")
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return false;
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// Ignore the *_sfp instructions when decoding. They are used by the
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// compiler to implement scalar floating point operations using vector
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// operations in order to work around some performance issues.
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if (Name.find("_sfp") != std::string::npos) return false;
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// LDMIA_RET is a special case of LDM (Load Multiple) where the registers
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// loaded include the PC, causing a branch to a loaded address. Ignore
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// the LDMIA_RET instruction when decoding.
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