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Rename SDOperand to SDValue.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-07-27 21:46:04 +00:00
parent 8968450305
commit 475871a144
57 changed files with 5556 additions and 5561 deletions
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2
docs/CodeGenerator.html
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@ -787,7 +787,7 @@ define multiple values. For example, a combined div/rem operation will define
both the dividend and the remainder. Many other situations require multiple
values as well. Each node also has some number of operands, which are edges
to the node defining the used value. Because nodes may define multiple values,
edges are represented by instances of the <tt>SDOperand</tt> class, which is
edges are represented by instances of the <tt>SDValue</tt> class, which is
a <tt>&lt;SDNode, unsigned&gt;</tt> pair, indicating the node and result
value being used, respectively. Each value produced by an <tt>SDNode</tt> has
an associated <tt>MVT</tt> (Machine Value Type) indicating what the type of the

14
include/llvm/CodeGen/DAGISelHeader.h
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@ -35,7 +35,7 @@ static bool IsChainCompatible(SDNode *Chain, SDNode *Op) {
else if (Chain->getOpcode() == ISD::TokenFactor)
return false;
else if (Chain->getNumOperands() > 0) {
SDOperand C0 = Chain->getOperand(0);
SDValue C0 = Chain->getOperand(0);
if (C0.getValueType() == MVT::Other)
return C0.Val != Op && IsChainCompatible(C0.Val, Op);
}
@ -75,7 +75,7 @@ inline bool isSelected(int Id) {
/// AddToISelQueue - adds a node to the instruction
/// selection queue.
void AddToISelQueue(SDOperand N) DISABLE_INLINE {
void AddToISelQueue(SDValue N) DISABLE_INLINE {
int Id = N.Val->getNodeId();
if (Id != -1 && !isQueued(Id)) {
ISelQueue.push_back(N.Val);
@ -117,7 +117,7 @@ inline void UpdateQueue(const ISelQueueUpdater &ISQU) {
/// ReplaceUses - replace all uses of the old node F with the use
/// of the new node T.
void ReplaceUses(SDOperand F, SDOperand T) DISABLE_INLINE {
void ReplaceUses(SDValue F, SDValue T) DISABLE_INLINE {
ISelQueueUpdater ISQU(ISelQueue);
CurDAG->ReplaceAllUsesOfValueWith(F, T, &ISQU);
setSelected(F.Val->getNodeId());
@ -126,7 +126,7 @@ void ReplaceUses(SDOperand F, SDOperand T) DISABLE_INLINE {
/// ReplaceUses - replace all uses of the old nodes F with the use
/// of the new nodes T.
void ReplaceUses(const SDOperand *F, const SDOperand *T,
void ReplaceUses(const SDValue *F, const SDValue *T,
unsigned Num) DISABLE_INLINE {
ISelQueueUpdater ISQU(ISelQueue);
CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num, &ISQU);
@ -143,7 +143,7 @@ void ReplaceUses(SDNode *F, SDNode *T) DISABLE_INLINE {
ISelQueueUpdater ISQU(ISelQueue);
if (FNumVals != TNumVals) {
for (unsigned i = 0, e = std::min(FNumVals, TNumVals); i < e; ++i)
CurDAG->ReplaceAllUsesOfValueWith(SDOperand(F, i), SDOperand(T, i), &ISQU);
CurDAG->ReplaceAllUsesOfValueWith(SDValue(F, i), SDValue(T, i), &ISQU);
} else {
CurDAG->ReplaceAllUsesWith(F, T, &ISQU);
}
@ -153,7 +153,7 @@ void ReplaceUses(SDNode *F, SDNode *T) DISABLE_INLINE {
/// SelectRoot - Top level entry to DAG instruction selector.
/// Selects instructions starting at the root of the current DAG.
SDOperand SelectRoot(SDOperand Root) {
SDValue SelectRoot(SDValue Root) {
SelectRootInit();
unsigned NumBytes = (DAGSize + 7) / 8;
ISelQueued = new unsigned char[NumBytes];
@ -176,7 +176,7 @@ SDOperand SelectRoot(SDOperand Root) {
// Skip already selected nodes.
if (isSelected(Node->getNodeId()))
continue;
SDNode *ResNode = Select(SDOperand(Node, 0));
SDNode *ResNode = Select(SDValue(Node, 0));
// If node should not be replaced,
// continue with the next one.
if (ResNode == Node)

14
include/llvm/CodeGen/ScheduleDAG.h
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@ -330,7 +330,7 @@ namespace llvm {
/// register number for the results of the node.
///
void EmitNode(SDNode *Node, bool IsClone,
DenseMap<SDOperand, unsigned> &VRBaseMap);
DenseMap<SDValue, unsigned> &VRBaseMap);
/// EmitNoop - Emit a noop instruction.
///
@ -349,19 +349,19 @@ namespace llvm {
/// EmitSubregNode - Generate machine code for subreg nodes.
///
void EmitSubregNode(SDNode *Node,
DenseMap<SDOperand, unsigned> &VRBaseMap);
DenseMap<SDValue, unsigned> &VRBaseMap);
/// getVR - Return the virtual register corresponding to the specified result
/// of the specified node.
unsigned getVR(SDOperand Op, DenseMap<SDOperand, unsigned> &VRBaseMap);
unsigned getVR(SDValue Op, DenseMap<SDValue, unsigned> &VRBaseMap);
/// getDstOfCopyToRegUse - If the only use of the specified result number of
/// node is a CopyToReg, return its destination register. Return 0 otherwise.
unsigned getDstOfOnlyCopyToRegUse(SDNode *Node, unsigned ResNo) const;
void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum,
void AddOperand(MachineInstr *MI, SDValue Op, unsigned IIOpNum,
const TargetInstrDesc *II,
DenseMap<SDOperand, unsigned> &VRBaseMap);
DenseMap<SDValue, unsigned> &VRBaseMap);
void AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO);
@ -371,11 +371,11 @@ namespace llvm {
/// implicit physical register output.
void EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
unsigned SrcReg,
DenseMap<SDOperand, unsigned> &VRBaseMap);
DenseMap<SDValue, unsigned> &VRBaseMap);
void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
const TargetInstrDesc &II,
DenseMap<SDOperand, unsigned> &VRBaseMap);
DenseMap<SDValue, unsigned> &VRBaseMap);
/// EmitLiveInCopy - Emit a copy for a live in physical register. If the
/// physical register has only a single copy use, then coalesced the copy

352
include/llvm/CodeGen/SelectionDAG.h
View File

@ -52,7 +52,7 @@ class SelectionDAG {
MachineModuleInfo *MMI;
/// Root - The root of the entire DAG. EntryNode - The starting token.
SDOperand Root, EntryNode;
SDValue Root, EntryNode;
/// AllNodes - A linked list of nodes in the current DAG.
alist<SDNode, LargestSDNode> &AllNodes;
@ -120,15 +120,15 @@ public:
/// getRoot - Return the root tag of the SelectionDAG.
///
const SDOperand &getRoot() const { return Root; }
const SDValue &getRoot() const { return Root; }
/// getEntryNode - Return the token chain corresponding to the entry of the
/// function.
const SDOperand &getEntryNode() const { return EntryNode; }
const SDValue &getEntryNode() const { return EntryNode; }
/// setRoot - Set the current root tag of the SelectionDAG.
///
const SDOperand &setRoot(SDOperand N) {
const SDValue &setRoot(SDValue N) {
assert((!N.Val || N.getValueType() == MVT::Other) &&
"DAG root value is not a chain!");
return Root = N;
@ -188,61 +188,61 @@ public:
//===--------------------------------------------------------------------===//
// Node creation methods.
//
SDOperand getConstant(uint64_t Val, MVT VT, bool isTarget = false);
SDOperand getConstant(const APInt &Val, MVT VT, bool isTarget = false);
SDOperand getIntPtrConstant(uint64_t Val, bool isTarget = false);
SDOperand getTargetConstant(uint64_t Val, MVT VT) {
SDValue getConstant(uint64_t Val, MVT VT, bool isTarget = false);
SDValue getConstant(const APInt &Val, MVT VT, bool isTarget = false);
SDValue getIntPtrConstant(uint64_t Val, bool isTarget = false);
SDValue getTargetConstant(uint64_t Val, MVT VT) {
return getConstant(Val, VT, true);
}
SDOperand getTargetConstant(const APInt &Val, MVT VT) {
SDValue getTargetConstant(const APInt &Val, MVT VT) {
return getConstant(Val, VT, true);
}
SDOperand getConstantFP(double Val, MVT VT, bool isTarget = false);
SDOperand getConstantFP(const APFloat& Val, MVT VT, bool isTarget = false);
SDOperand getTargetConstantFP(double Val, MVT VT) {
SDValue getConstantFP(double Val, MVT VT, bool isTarget = false);
SDValue getConstantFP(const APFloat& Val, MVT VT, bool isTarget = false);
SDValue getTargetConstantFP(double Val, MVT VT) {
return getConstantFP(Val, VT, true);
}
SDOperand getTargetConstantFP(const APFloat& Val, MVT VT) {
SDValue getTargetConstantFP(const APFloat& Val, MVT VT) {
return getConstantFP(Val, VT, true);
}
SDOperand getGlobalAddress(const GlobalValue *GV, MVT VT,
SDValue getGlobalAddress(const GlobalValue *GV, MVT VT,
int offset = 0, bool isTargetGA = false);
SDOperand getTargetGlobalAddress(const GlobalValue *GV, MVT VT,
SDValue getTargetGlobalAddress(const GlobalValue *GV, MVT VT,
int offset = 0) {
return getGlobalAddress(GV, VT, offset, true);
}
SDOperand getFrameIndex(int FI, MVT VT, bool isTarget = false);
SDOperand getTargetFrameIndex(int FI, MVT VT) {
SDValue getFrameIndex(int FI, MVT VT, bool isTarget = false);
SDValue getTargetFrameIndex(int FI, MVT VT) {
return getFrameIndex(FI, VT, true);
}
SDOperand getJumpTable(int JTI, MVT VT, bool isTarget = false);
SDOperand getTargetJumpTable(int JTI, MVT VT) {
SDValue getJumpTable(int JTI, MVT VT, bool isTarget = false);
SDValue getTargetJumpTable(int JTI, MVT VT) {
return getJumpTable(JTI, VT, true);
}
SDOperand getConstantPool(Constant *C, MVT VT,
SDValue getConstantPool(Constant *C, MVT VT,
unsigned Align = 0, int Offs = 0, bool isT=false);
SDOperand getTargetConstantPool(Constant *C, MVT VT,
SDValue getTargetConstantPool(Constant *C, MVT VT,
unsigned Align = 0, int Offset = 0) {
return getConstantPool(C, VT, Align, Offset, true);
}
SDOperand getConstantPool(MachineConstantPoolValue *C, MVT VT,
SDValue getConstantPool(MachineConstantPoolValue *C, MVT VT,
unsigned Align = 0, int Offs = 0, bool isT=false);
SDOperand getTargetConstantPool(MachineConstantPoolValue *C,
SDValue getTargetConstantPool(MachineConstantPoolValue *C,
MVT VT, unsigned Align = 0,
int Offset = 0) {
return getConstantPool(C, VT, Align, Offset, true);
}
SDOperand getBasicBlock(MachineBasicBlock *MBB);
SDOperand getExternalSymbol(const char *Sym, MVT VT);
SDOperand getTargetExternalSymbol(const char *Sym, MVT VT);
SDOperand getArgFlags(ISD::ArgFlagsTy Flags);
SDOperand getValueType(MVT);
SDOperand getRegister(unsigned Reg, MVT VT);
SDOperand getDbgStopPoint(SDOperand Root, unsigned Line, unsigned Col,
SDValue getBasicBlock(MachineBasicBlock *MBB);
SDValue getExternalSymbol(const char *Sym, MVT VT);
SDValue getTargetExternalSymbol(const char *Sym, MVT VT);
SDValue getArgFlags(ISD::ArgFlagsTy Flags);
SDValue getValueType(MVT);
SDValue getRegister(unsigned Reg, MVT VT);
SDValue getDbgStopPoint(SDValue Root, unsigned Line, unsigned Col,
const CompileUnitDesc *CU);
SDOperand getLabel(unsigned Opcode, SDOperand Root, unsigned LabelID);
SDValue getLabel(unsigned Opcode, SDValue Root, unsigned LabelID);
SDOperand getCopyToReg(SDOperand Chain, unsigned Reg, SDOperand N) {
SDValue getCopyToReg(SDValue Chain, unsigned Reg, SDValue N) {
return getNode(ISD::CopyToReg, MVT::Other, Chain,
getRegister(Reg, N.getValueType()), N);
}
@ -250,57 +250,57 @@ public:
// This version of the getCopyToReg method takes an extra operand, which
// indicates that there is potentially an incoming flag value (if Flag is not
// null) and that there should be a flag result.
SDOperand getCopyToReg(SDOperand Chain, unsigned Reg, SDOperand N,
SDOperand Flag) {
SDValue getCopyToReg(SDValue Chain, unsigned Reg, SDValue N,
SDValue Flag) {
const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
SDOperand Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Flag };
SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Flag };
return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.Val ? 4 : 3);
}
// Similar to last getCopyToReg() except parameter Reg is a SDOperand
SDOperand getCopyToReg(SDOperand Chain, SDOperand Reg, SDOperand N,
SDOperand Flag) {
// Similar to last getCopyToReg() except parameter Reg is a SDValue
SDValue getCopyToReg(SDValue Chain, SDValue Reg, SDValue N,
SDValue Flag) {
const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
SDOperand Ops[] = { Chain, Reg, N, Flag };
SDValue Ops[] = { Chain, Reg, N, Flag };
return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.Val ? 4 : 3);
}
SDOperand getCopyFromReg(SDOperand Chain, unsigned Reg, MVT VT) {
SDValue getCopyFromReg(SDValue Chain, unsigned Reg, MVT VT) {
const MVT *VTs = getNodeValueTypes(VT, MVT::Other);
SDOperand Ops[] = { Chain, getRegister(Reg, VT) };
SDValue Ops[] = { Chain, getRegister(Reg, VT) };
return getNode(ISD::CopyFromReg, VTs, 2, Ops, 2);
}
// This version of the getCopyFromReg method takes an extra operand, which
// indicates that there is potentially an incoming flag value (if Flag is not
// null) and that there should be a flag result.
SDOperand getCopyFromReg(SDOperand Chain, unsigned Reg, MVT VT,
SDOperand Flag) {
SDValue getCopyFromReg(SDValue Chain, unsigned Reg, MVT VT,
SDValue Flag) {
const MVT *VTs = getNodeValueTypes(VT, MVT::Other, MVT::Flag);
SDOperand Ops[] = { Chain, getRegister(Reg, VT), Flag };
SDValue Ops[] = { Chain, getRegister(Reg, VT), Flag };
return getNode(ISD::CopyFromReg, VTs, 3, Ops, Flag.Val ? 3 : 2);
}
SDOperand getCondCode(ISD::CondCode Cond);
SDValue getCondCode(ISD::CondCode Cond);
/// getZeroExtendInReg - Return the expression required to zero extend the Op
/// value assuming it was the smaller SrcTy value.
SDOperand getZeroExtendInReg(SDOperand Op, MVT SrcTy);
SDValue getZeroExtendInReg(SDValue Op, MVT SrcTy);
/// getCALLSEQ_START - Return a new CALLSEQ_START node, which always must have
/// a flag result (to ensure it's not CSE'd).
SDOperand getCALLSEQ_START(SDOperand Chain, SDOperand Op) {
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op) {
const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
SDOperand Ops[] = { Chain, Op };
SDValue Ops[] = { Chain, Op };
return getNode(ISD::CALLSEQ_START, VTs, 2, Ops, 2);
}
/// getCALLSEQ_END - Return a new CALLSEQ_END node, which always must have a
/// flag result (to ensure it's not CSE'd).
SDOperand getCALLSEQ_END(SDOperand Chain, SDOperand Op1, SDOperand Op2,
SDOperand InFlag) {
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
SDValue InFlag) {
SDVTList NodeTys = getVTList(MVT::Other, MVT::Flag);
SmallVector<SDOperand, 4> Ops;
SmallVector<SDValue, 4> Ops;
Ops.push_back(Chain);
Ops.push_back(Op1);
Ops.push_back(Op2);
@ -311,103 +311,103 @@ public:
/// getNode - Gets or creates the specified node.
///
SDOperand getNode(unsigned Opcode, MVT VT);
SDOperand getNode(unsigned Opcode, MVT VT, SDOperand N);
SDOperand getNode(unsigned Opcode, MVT VT, SDOperand N1, SDOperand N2);
SDOperand getNode(unsigned Opcode, MVT VT,
SDOperand N1, SDOperand N2, SDOperand N3);
SDOperand getNode(unsigned Opcode, MVT VT,
SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4);
SDOperand getNode(unsigned Opcode, MVT VT,
SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4,
SDOperand N5);
SDOperand getNode(unsigned Opcode, MVT VT,
const SDOperand *Ops, unsigned NumOps);
SDOperand getNode(unsigned Opcode, MVT VT,
SDValue getNode(unsigned Opcode, MVT VT);
SDValue getNode(unsigned Opcode, MVT VT, SDValue N);
SDValue getNode(unsigned Opcode, MVT VT, SDValue N1, SDValue N2);
SDValue getNode(unsigned Opcode, MVT VT,
SDValue N1, SDValue N2, SDValue N3);
SDValue getNode(unsigned Opcode, MVT VT,
SDValue N1, SDValue N2, SDValue N3, SDValue N4);
SDValue getNode(unsigned Opcode, MVT VT,
SDValue N1, SDValue N2, SDValue N3, SDValue N4,
SDValue N5);
SDValue getNode(unsigned Opcode, MVT VT,
const SDValue *Ops, unsigned NumOps);
SDValue getNode(unsigned Opcode, MVT VT,
const SDUse *Ops, unsigned NumOps);
SDOperand getNode(unsigned Opcode, const std::vector<MVT> &ResultTys,
const SDOperand *Ops, unsigned NumOps);
SDOperand getNode(unsigned Opcode, const MVT *VTs, unsigned NumVTs,
const SDOperand *Ops, unsigned NumOps);
SDOperand getNode(unsigned Opcode, SDVTList VTs);
SDOperand getNode(unsigned Opcode, SDVTList VTs, SDOperand N);
SDOperand getNode(unsigned Opcode, SDVTList VTs, SDOperand N1, SDOperand N2);
SDOperand getNode(unsigned Opcode, SDVTList VTs,
SDOperand N1, SDOperand N2, SDOperand N3);
SDOperand getNode(unsigned Opcode, SDVTList VTs,
SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4);
SDOperand getNode(unsigned Opcode, SDVTList VTs,
SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4,
SDOperand N5);
SDOperand getNode(unsigned Opcode, SDVTList VTs,
const SDOperand *Ops, unsigned NumOps);
SDValue getNode(unsigned Opcode, const std::vector<MVT> &ResultTys,
const SDValue *Ops, unsigned NumOps);
SDValue getNode(unsigned Opcode, const MVT *VTs, unsigned NumVTs,
const SDValue *Ops, unsigned NumOps);
SDValue getNode(unsigned Opcode, SDVTList VTs);
SDValue getNode(unsigned Opcode, SDVTList VTs, SDValue N);
SDValue getNode(unsigned Opcode, SDVTList VTs, SDValue N1, SDValue N2);
SDValue getNode(unsigned Opcode, SDVTList VTs,
SDValue N1, SDValue N2, SDValue N3);
SDValue getNode(unsigned Opcode, SDVTList VTs,
SDValue N1, SDValue N2, SDValue N3, SDValue N4);
SDValue getNode(unsigned Opcode, SDVTList VTs,
SDValue N1, SDValue N2, SDValue N3, SDValue N4,
SDValue N5);
SDValue getNode(unsigned Opcode, SDVTList VTs,
const SDValue *Ops, unsigned NumOps);
SDOperand getMemcpy(SDOperand Chain, SDOperand Dst, SDOperand Src,
SDOperand Size, unsigned Align,
SDValue getMemcpy(SDValue Chain, SDValue Dst, SDValue Src,
SDValue Size, unsigned Align,
bool AlwaysInline,
const Value *DstSV, uint64_t DstSVOff,
const Value *SrcSV, uint64_t SrcSVOff);
SDOperand getMemmove(SDOperand Chain, SDOperand Dst, SDOperand Src,
SDOperand Size, unsigned Align,
SDValue getMemmove(SDValue Chain, SDValue Dst, SDValue Src,
SDValue Size, unsigned Align,
const Value *DstSV, uint64_t DstOSVff,
const Value *SrcSV, uint64_t SrcSVOff);
SDOperand getMemset(SDOperand Chain, SDOperand Dst, SDOperand Src,
SDOperand Size, unsigned Align,
SDValue getMemset(SDValue Chain, SDValue Dst, SDValue Src,
SDValue Size, unsigned Align,
const Value *DstSV, uint64_t DstSVOff);
/// getSetCC - Helper function to make it easier to build SetCC's if you just
/// have an ISD::CondCode instead of an SDOperand.
/// have an ISD::CondCode instead of an SDValue.
///
SDOperand getSetCC(MVT VT, SDOperand LHS, SDOperand RHS,
SDValue getSetCC(MVT VT, SDValue LHS, SDValue RHS,
ISD::CondCode Cond) {
return getNode(ISD::SETCC, VT, LHS, RHS, getCondCode(Cond));
}
/// getVSetCC - Helper function to make it easier to build VSetCC's nodes
/// if you just have an ISD::CondCode instead of an SDOperand.
/// if you just have an ISD::CondCode instead of an SDValue.
///
SDOperand getVSetCC(MVT VT, SDOperand LHS, SDOperand RHS,
SDValue getVSetCC(MVT VT, SDValue LHS, SDValue RHS,
ISD::CondCode Cond) {
return getNode(ISD::VSETCC, VT, LHS, RHS, getCondCode(Cond));
}
/// getSelectCC - Helper function to make it easier to build SelectCC's if you
/// just have an ISD::CondCode instead of an SDOperand.
/// just have an ISD::CondCode instead of an SDValue.
///
SDOperand getSelectCC(SDOperand LHS, SDOperand RHS,
SDOperand True, SDOperand False, ISD::CondCode Cond) {
SDValue getSelectCC(SDValue LHS, SDValue RHS,
SDValue True, SDValue False, ISD::CondCode Cond) {
return getNode(ISD::SELECT_CC, True.getValueType(), LHS, RHS, True, False,
getCondCode(Cond));
}
/// getVAArg - VAArg produces a result and token chain, and takes a pointer
/// and a source value as input.
SDOperand getVAArg(MVT VT, SDOperand Chain, SDOperand Ptr,
SDOperand SV);
SDValue getVAArg(MVT VT, SDValue Chain, SDValue Ptr,
SDValue SV);
/// getAtomic - Gets a node for an atomic op, produces result and chain, takes
/// 3 operands
SDOperand getAtomic(unsigned Opcode, SDOperand Chain, SDOperand Ptr,
SDOperand Cmp, SDOperand Swp, const Value* PtrVal,
SDValue getAtomic(unsigned Opcode, SDValue Chain, SDValue Ptr,
SDValue Cmp, SDValue Swp, const Value* PtrVal,
unsigned Alignment=0);
/// getAtomic - Gets a node for an atomic op, produces result and chain, takes
/// 2 operands
SDOperand getAtomic(unsigned Opcode, SDOperand Chain, SDOperand Ptr,
SDOperand Val, const Value* PtrVal,
SDValue getAtomic(unsigned Opcode, SDValue Chain, SDValue Ptr,
SDValue Val, const Value* PtrVal,
unsigned Alignment = 0);
/// getMergeValues - Create a MERGE_VALUES node from the given operands.
/// Allowed to return something different (and simpler) if Simplify is true.
SDOperand getMergeValues(const SDOperand *Ops, unsigned NumOps,
SDValue getMergeValues(const SDValue *Ops, unsigned NumOps,
bool Simplify = true);
/// getMergeValues - Create a MERGE_VALUES node from the given types and ops.
/// Allowed to return something different (and simpler) if Simplify is true.
/// May be faster than the above version if VTs is known and NumOps is large.
SDOperand getMergeValues(SDVTList VTs, const SDOperand *Ops, unsigned NumOps,
SDValue getMergeValues(SDVTList VTs, const SDValue *Ops, unsigned NumOps,
bool Simplify = true) {
if (Simplify && NumOps == 1)
return Ops[0];
@ -417,38 +417,38 @@ public:
/// getLoad - Loads are not normal binary operators: their result type is not
/// determined by their operands, and they produce a value AND a token chain.
///
SDOperand getLoad(MVT VT, SDOperand Chain, SDOperand Ptr,
SDValue getLoad(MVT VT, SDValue Chain, SDValue Ptr,
const Value *SV, int SVOffset, bool isVolatile=false,
unsigned Alignment=0);
SDOperand getExtLoad(ISD::LoadExtType ExtType, MVT VT,
SDOperand Chain, SDOperand Ptr, const Value *SV,
SDValue getExtLoad(ISD::LoadExtType ExtType, MVT VT,
SDValue Chain, SDValue Ptr, const Value *SV,
int SVOffset, MVT EVT, bool isVolatile=false,
unsigned Alignment=0);
SDOperand getIndexedLoad(SDOperand OrigLoad, SDOperand Base,
SDOperand Offset, ISD::MemIndexedMode AM);
SDOperand getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
MVT VT, SDOperand Chain,
SDOperand Ptr, SDOperand Offset,
SDValue getIndexedLoad(SDValue OrigLoad, SDValue Base,
SDValue Offset, ISD::MemIndexedMode AM);
SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
MVT VT, SDValue Chain,
SDValue Ptr, SDValue Offset,
const Value *SV, int SVOffset, MVT EVT,
bool isVolatile=false, unsigned Alignment=0);
/// getStore - Helper function to build ISD::STORE nodes.
///
SDOperand getStore(SDOperand Chain, SDOperand Val, SDOperand Ptr,
SDValue getStore(SDValue Chain, SDValue Val, SDValue Ptr,
const Value *SV, int SVOffset, bool isVolatile=false,
unsigned Alignment=0);
SDOperand getTruncStore(SDOperand Chain, SDOperand Val, SDOperand Ptr,
SDValue getTruncStore(SDValue Chain, SDValue Val, SDValue Ptr,
const Value *SV, int SVOffset, MVT TVT,
bool isVolatile=false, unsigned Alignment=0);
SDOperand getIndexedStore(SDOperand OrigStoe, SDOperand Base,
SDOperand Offset, ISD::MemIndexedMode AM);
SDValue getIndexedStore(SDValue OrigStoe, SDValue Base,
SDValue Offset, ISD::MemIndexedMode AM);
// getSrcValue - Construct a node to track a Value* through the backend.
SDOperand getSrcValue(const Value *v);
SDValue getSrcValue(const Value *v);
// getMemOperand - Construct a node to track a memory reference
// through the backend.
SDOperand getMemOperand(const MachineMemOperand &MO);
SDValue getMemOperand(const MachineMemOperand &MO);
/// UpdateNodeOperands - *Mutate* the specified node in-place to have the
/// specified operands. If the resultant node already exists in the DAG,
@ -456,66 +456,66 @@ public:
/// already exists. If the resultant node does not exist in the DAG, the
/// input node is returned. As a degenerate case, if you specify the same
/// input operands as the node already has, the input node is returned.
SDOperand UpdateNodeOperands(SDOperand N, SDOperand Op);
SDOperand UpdateNodeOperands(SDOperand N, SDOperand Op1, SDOperand Op2);
SDOperand UpdateNodeOperands(SDOperand N, SDOperand Op1, SDOperand Op2,
SDOperand Op3);
SDOperand UpdateNodeOperands(SDOperand N, SDOperand Op1, SDOperand Op2,
SDOperand Op3, SDOperand Op4);
SDOperand UpdateNodeOperands(SDOperand N, SDOperand Op1, SDOperand Op2,
SDOperand Op3, SDOperand Op4, SDOperand Op5);
SDOperand UpdateNodeOperands(SDOperand N,
const SDOperand *Ops, unsigned NumOps);
SDValue UpdateNodeOperands(SDValue N, SDValue Op);
SDValue UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2);
SDValue UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2,
SDValue Op3);
SDValue UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2,
SDValue Op3, SDValue Op4);
SDValue UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2,
SDValue Op3, SDValue Op4, SDValue Op5);
SDValue UpdateNodeOperands(SDValue N,
const SDValue *Ops, unsigned NumOps);
/// SelectNodeTo - These are used for target selectors to *mutate* the
/// specified node to have the specified return type, Target opcode, and
/// operands. Note that target opcodes are stored as
/// ~TargetOpcode in the node opcode field. The resultant node is returned.
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT, SDOperand Op1);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT, SDValue Op1);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT,
SDOperand Op1, SDOperand Op2);
SDValue Op1, SDValue Op2);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT,
SDOperand Op1, SDOperand Op2, SDOperand Op3);
SDValue Op1, SDValue Op2, SDValue Op3);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT,
const SDOperand *Ops, unsigned NumOps);
const SDValue *Ops, unsigned NumOps);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1, MVT VT2);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
MVT VT2, const SDOperand *Ops, unsigned NumOps);
MVT VT2, const SDValue *Ops, unsigned NumOps);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
MVT VT2, MVT VT3, const SDOperand *Ops, unsigned NumOps);
MVT VT2, MVT VT3, const SDValue *Ops, unsigned NumOps);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
MVT VT2, SDOperand Op1);
MVT VT2, SDValue Op1);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
MVT VT2, SDOperand Op1, SDOperand Op2);
MVT VT2, SDValue Op1, SDValue Op2);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
MVT VT2, SDOperand Op1, SDOperand Op2, SDOperand Op3);
MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, SDVTList VTs,
const SDOperand *Ops, unsigned NumOps);
const SDValue *Ops, unsigned NumOps);
/// MorphNodeTo - These *mutate* the specified node to have the specified
/// return type, opcode, and operands.
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT);
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT, SDOperand Op1);
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT, SDValue Op1);
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT,
SDOperand Op1, SDOperand Op2);
SDValue Op1, SDValue Op2);
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT,
SDOperand Op1, SDOperand Op2, SDOperand Op3);
SDValue Op1, SDValue Op2, SDValue Op3);
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT,
const SDOperand *Ops, unsigned NumOps);
const SDValue *Ops, unsigned NumOps);
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1, MVT VT2);
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1,
MVT VT2, const SDOperand *Ops, unsigned NumOps);
MVT VT2, const SDValue *Ops, unsigned NumOps);
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1,
MVT VT2, MVT VT3, const SDOperand *Ops, unsigned NumOps);
MVT VT2, MVT VT3, const SDValue *Ops, unsigned NumOps);
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1,
MVT VT2, SDOperand Op1);
MVT VT2, SDValue Op1);
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1,
MVT VT2, SDOperand Op1, SDOperand Op2);
MVT VT2, SDValue Op1, SDValue Op2);
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1,
MVT VT2, SDOperand Op1, SDOperand Op2, SDOperand Op3);
MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs,
const SDOperand *Ops, unsigned NumOps);
const SDValue *Ops, unsigned NumOps);
/// getTargetNode - These are used for target selectors to create a new node
/// with specified return type(s), target opcode, and operands.
@ -524,35 +524,35 @@ public:
/// node of the specified opcode and operands, it returns that node instead of
/// the current one.
SDNode *getTargetNode(unsigned Opcode, MVT VT);
SDNode *getTargetNode(unsigned Opcode, MVT VT, SDOperand Op1);
SDNode *getTargetNode(unsigned Opcode, MVT VT, SDOperand Op1, SDOperand Op2);
SDNode *getTargetNode(unsigned Opcode, MVT VT, SDValue Op1);
SDNode *getTargetNode(unsigned Opcode, MVT VT, SDValue Op1, SDValue Op2);
SDNode *getTargetNode(unsigned Opcode, MVT VT,
SDOperand Op1, SDOperand Op2, SDOperand Op3);
SDValue Op1, SDValue Op2, SDValue Op3);
SDNode *getTargetNode(unsigned Opcode, MVT VT,
const SDOperand *Ops, unsigned NumOps);
const SDValue *Ops, unsigned NumOps);
SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2);
SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, SDOperand Op1);
SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, SDValue Op1);
SDNode *getTargetNode(unsigned Opcode, MVT VT1,
MVT VT2, SDOperand Op1, SDOperand Op2);
MVT VT2, SDValue Op1, SDValue Op2);
SDNode *getTargetNode(unsigned Opcode, MVT VT1,
MVT VT2, SDOperand Op1, SDOperand Op2, SDOperand Op3);
MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2,
const SDOperand *Ops, unsigned NumOps);
const SDValue *Ops, unsigned NumOps);
SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
SDOperand Op1, SDOperand Op2);
SDValue Op1, SDValue Op2);
SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
SDOperand Op1, SDOperand Op2, SDOperand Op3);
SDValue Op1, SDValue Op2, SDValue Op3);
SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
const SDOperand *Ops, unsigned NumOps);
const SDValue *Ops, unsigned NumOps);
SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, MVT VT4,
const SDOperand *Ops, unsigned NumOps);
const SDValue *Ops, unsigned NumOps);
SDNode *getTargetNode(unsigned Opcode, const std::vector<MVT> &ResultTys,
const SDOperand *Ops, unsigned NumOps);
const SDValue *Ops, unsigned NumOps);
/// getNodeIfExists - Get the specified node if it's already available, or
/// else return NULL.
SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTs,
const SDOperand *Ops, unsigned NumOps);
const SDValue *Ops, unsigned NumOps);
/// DAGUpdateListener - Clients of various APIs that cause global effects on
/// the DAG can optionally implement this interface. This allows the clients
@ -588,22 +588,22 @@ public:
/// informed about nodes that are deleted and modified due to recursive
/// changes in the dag.
///
void ReplaceAllUsesWith(SDOperand From, SDOperand Op,
void ReplaceAllUsesWith(SDValue From, SDValue Op,
DAGUpdateListener *UpdateListener = 0);
void ReplaceAllUsesWith(SDNode *From, SDNode *To,
DAGUpdateListener *UpdateListener = 0);
void ReplaceAllUsesWith(SDNode *From, const SDOperand *To,
void ReplaceAllUsesWith(SDNode *From, const SDValue *To,
DAGUpdateListener *UpdateListener = 0);
/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving
/// uses of other values produced by From.Val alone.
void ReplaceAllUsesOfValueWith(SDOperand From, SDOperand To,
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To,
DAGUpdateListener *UpdateListener = 0);
/// ReplaceAllUsesOfValuesWith - Like ReplaceAllUsesOfValueWith, but
/// for multiple values at once. This correctly handles the case where
/// there is an overlap between the From values and the To values.
void ReplaceAllUsesOfValuesWith(const SDOperand *From, const SDOperand *To,
void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To,
unsigned Num,
DAGUpdateListener *UpdateListener = 0);
@ -640,20 +640,20 @@ public:
/// CreateStackTemporary - Create a stack temporary, suitable for holding the
/// specified value type. If minAlign is specified, the slot size will have
/// at least that alignment.
SDOperand CreateStackTemporary(MVT VT, unsigned minAlign = 1);
SDValue CreateStackTemporary(MVT VT, unsigned minAlign = 1);
/// FoldSetCC - Constant fold a setcc to true or false.
SDOperand FoldSetCC(MVT VT, SDOperand N1,
SDOperand N2, ISD::CondCode Cond);
SDValue FoldSetCC(MVT VT, SDValue N1,
SDValue N2, ISD::CondCode Cond);
/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We
/// use this predicate to simplify operations downstream.
bool SignBitIsZero(SDOperand Op, unsigned Depth = 0) const;
bool SignBitIsZero(SDValue Op, unsigned Depth = 0) const;
/// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We
/// use this predicate to simplify operations downstream. Op and Mask are
/// known to be the same type.
bool MaskedValueIsZero(SDOperand Op, const APInt &Mask, unsigned Depth = 0)
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth = 0)
const;
/// ComputeMaskedBits - Determine which of the bits specified in Mask are
@ -661,7 +661,7 @@ public:
/// bitsets. This code only analyzes bits in Mask, in order to short-circuit
/// processing. Targets can implement the computeMaskedBitsForTargetNode
/// method in the TargetLowering class to allow target nodes to be understood.
void ComputeMaskedBits(SDOperand Op, const APInt &Mask, APInt &KnownZero,
void ComputeMaskedBits(SDValue Op, const APInt &Mask, APInt &KnownZero,
APInt &KnownOne, unsigned Depth = 0) const;
/// ComputeNumSignBits - Return the number of times the sign bit of the
@ -671,24 +671,24 @@ public:
/// the top 3 bits are all equal to each other, so we return 3. Targets can
/// implement the ComputeNumSignBitsForTarget method in the TargetLowering
/// class to allow target nodes to be understood.
unsigned ComputeNumSignBits(SDOperand Op, unsigned Depth = 0) const;
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth = 0) const;
/// isVerifiedDebugInfoDesc - Returns true if the specified SDOperand has
/// isVerifiedDebugInfoDesc - Returns true if the specified SDValue has
/// been verified as a debug information descriptor.
bool isVerifiedDebugInfoDesc(SDOperand Op) const;
bool isVerifiedDebugInfoDesc(SDValue Op) const;
/// getShuffleScalarElt - Returns the scalar element that will make up the ith
/// element of the result of the vector shuffle.
SDOperand getShuffleScalarElt(const SDNode *N, unsigned Idx);
SDValue getShuffleScalarElt(const SDNode *N, unsigned Idx);
private:
inline alist_traits<SDNode, LargestSDNode>::AllocatorType &getAllocator();
void RemoveNodeFromCSEMaps(SDNode *N);
SDNode *AddNonLeafNodeToCSEMaps(SDNode *N);
SDNode *FindModifiedNodeSlot(SDNode *N, SDOperand Op, void *&InsertPos);
SDNode *FindModifiedNodeSlot(SDNode *N, SDOperand Op1, SDOperand Op2,
SDNode *FindModifiedNodeSlot(SDNode *N, SDValue Op, void *&InsertPos);
SDNode *FindModifiedNodeSlot(SDNode *N, SDValue Op1, SDValue Op2,
void *&InsertPos);
SDNode *FindModifiedNodeSlot(SDNode *N, const SDOperand *Ops, unsigned NumOps,
SDNode *FindModifiedNodeSlot(SDNode *N, const SDValue *Ops, unsigned NumOps,
void *&InsertPos);
void DeleteNodeNotInCSEMaps(SDNode *N);

12
include/llvm/CodeGen/SelectionDAGISel.h
View File

@ -21,7 +21,7 @@
namespace llvm {
class SelectionDAGLowering;
class SDOperand;
class SDValue;
class MachineRegisterInfo;
class MachineBasicBlock;
class MachineFunction;
@ -70,9 +70,9 @@ public:
/// not match or is not implemented, return true. The resultant operands
/// (which will appear in the machine instruction) should be added to the
/// OutOps vector.
virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
std::vector<SDOperand> &OutOps,
std::vector<SDValue> &OutOps,
SelectionDAG &DAG) {
return true;
}
@ -168,13 +168,13 @@ protected:
/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
/// by tblgen. Others should not call it.
void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
SelectionDAG &DAG);
// Calls to these predicates are generated by tblgen.
bool CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
int64_t DesiredMaskS) const;
bool CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
int64_t DesiredMaskS) const;
private:

179
include/llvm/CodeGen/SelectionDAGNodes.h
View File

@ -795,7 +795,7 @@ namespace ISD {
//===----------------------------------------------------------------------===//
/// SDOperand - Unlike LLVM values, Selection DAG nodes may return multiple
/// SDValue - Unlike LLVM values, Selection DAG nodes may return multiple
/// values as the result of a computation. Many nodes return multiple values,
/// from loads (which define a token and a return value) to ADDC (which returns
/// a result and a carry value), to calls (which may return an arbitrary number
@ -803,28 +803,28 @@ namespace ISD {
///
/// As such, each use of a SelectionDAG computation must indicate the node that
/// computes it as well as which return value to use from that node. This pair
/// of information is represented with the SDOperand value type.
/// of information is represented with the SDValue value type.
///
class SDOperand {
class SDValue {
public:
SDNode *Val; // The node defining the value we are using.
unsigned ResNo; // Which return value of the node we are using.
SDOperand() : Val(0), ResNo(0) {}
SDOperand(SDNode *val, unsigned resno) : Val(val), ResNo(resno) {}
SDValue() : Val(0), ResNo(0) {}
SDValue(SDNode *val, unsigned resno) : Val(val), ResNo(resno) {}
bool operator==(const SDOperand &O) const {
bool operator==(const SDValue &O) const {
return Val == O.Val && ResNo == O.ResNo;
}
bool operator!=(const SDOperand &O) const {
bool operator!=(const SDValue &O) const {
return !operator==(O);
}
bool operator<(const SDOperand &O) const {
bool operator<(const SDValue &O) const {
return Val < O.Val || (Val == O.Val && ResNo < O.ResNo);
}
SDOperand getValue(unsigned R) const {
return SDOperand(Val, R);
SDValue getValue(unsigned R) const {
return SDValue(Val, R);
}
// isOperandOf - Return true if this node is an operand of N.
@ -843,7 +843,7 @@ public:
// Forwarding methods - These forward to the corresponding methods in SDNode.
inline unsigned getOpcode() const;
inline unsigned getNumOperands() const;
inline const SDOperand &getOperand(unsigned i) const;
inline const SDValue &getOperand(unsigned i) const;
inline uint64_t getConstantOperandVal(unsigned i) const;
inline bool isTargetOpcode() const;
inline bool isMachineOpcode() const;
@ -855,7 +855,7 @@ public:
/// side-effecting instructions. In practice, this looks through token
/// factors and non-volatile loads. In order to remain efficient, this only
/// looks a couple of nodes in, it does not do an exhaustive search.
bool reachesChainWithoutSideEffects(SDOperand Dest,
bool reachesChainWithoutSideEffects(SDValue Dest,
unsigned Depth = 2) const;
/// use_empty - Return true if there are no nodes using value ResNo
@ -870,42 +870,42 @@ public:
};
template<> struct DenseMapInfo<SDOperand> {
static inline SDOperand getEmptyKey() {
return SDOperand((SDNode*)-1, -1U);
template<> struct DenseMapInfo<SDValue> {
static inline SDValue getEmptyKey() {
return SDValue((SDNode*)-1, -1U);
}
static inline SDOperand getTombstoneKey() {
return SDOperand((SDNode*)-1, 0);
static inline SDValue getTombstoneKey() {
return SDValue((SDNode*)-1, 0);
}
static unsigned getHashValue(const SDOperand &Val) {
static unsigned getHashValue(const SDValue &Val) {
return ((unsigned)((uintptr_t)Val.Val >> 4) ^
(unsigned)((uintptr_t)Val.Val >> 9)) + Val.ResNo;
}
static bool isEqual(const SDOperand &LHS, const SDOperand &RHS) {
static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
return LHS == RHS;
}
static bool isPod() { return true; }
};
/// simplify_type specializations - Allow casting operators to work directly on
/// SDOperands as if they were SDNode*'s.
template<> struct simplify_type<SDOperand> {
/// SDValues as if they were SDNode*'s.
template<> struct simplify_type<SDValue> {
typedef SDNode* SimpleType;
static SimpleType getSimplifiedValue(const SDOperand &Val) {
static SimpleType getSimplifiedValue(const SDValue &Val) {
return static_cast<SimpleType>(Val.Val);
}
};
template<> struct simplify_type<const SDOperand> {
template<> struct simplify_type<const SDValue> {
typedef SDNode* SimpleType;
static SimpleType getSimplifiedValue(const SDOperand &Val) {
static SimpleType getSimplifiedValue(const SDValue &Val) {
return static_cast<SimpleType>(Val.Val);
}
};
/// SDUse - Represents a use of the SDNode referred by
/// the SDOperand.
/// the SDValue.
class SDUse {
SDOperand Operand;
SDValue Operand;
/// User - Parent node of this operand.
SDNode *User;
/// Prev, next - Pointers to the uses list of the SDNode referred by
@ -918,7 +918,7 @@ public:
SDUse(SDNode *val, unsigned resno) :
Operand(val,resno), User(NULL), Prev(NULL), Next(NULL) {}
SDUse& operator= (const SDOperand& Op) {
SDUse& operator= (const SDValue& Op) {
Operand = Op;
Next = NULL;
Prev = NULL;
@ -938,21 +938,22 @@ public:
void setUser(SDNode *p) { User = p; }
operator SDOperand() const { return Operand; }
operator SDValue() const { return Operand; }
const SDOperand& getSDOperand() const { return Operand; }
const SDValue& getSDValue() const { return Operand; }
SDNode *&getVal() { return Operand.Val; }
SDNode *const &getVal() const { return Operand.Val; }
bool operator==(const SDOperand &O) const {
bool operator==(const SDValue &O) const {
return Operand == O;
}
bool operator!=(const SDOperand &O) const {
bool operator!=(const SDValue &O) const {
return !(Operand == O);
}
bool operator<(const SDOperand &O) const {
bool operator<(const SDValue &O) const {
return Operand < O;
}
@ -972,56 +973,56 @@ protected:
/// simplify_type specializations - Allow casting operators to work directly on
/// SDOperands as if they were SDNode*'s.
/// SDValues as if they were SDNode*'s.
template<> struct simplify_type<SDUse> {
typedef SDNode* SimpleType;
static SimpleType getSimplifiedValue(const SDUse &Val) {
return static_cast<SimpleType>(Val.getSDOperand().Val);
return static_cast<SimpleType>(Val.getVal());
}
};
template<> struct simplify_type<const SDUse> {
typedef SDNode* SimpleType;
static SimpleType getSimplifiedValue(const SDUse &Val) {
return static_cast<SimpleType>(Val.getSDOperand().Val);
return static_cast<SimpleType>(Val.getVal());
}
};
/// SDOperandPtr - A helper SDOperand pointer class, that can handle
/// arrays of SDUse and arrays of SDOperand objects. This is required
/// SDOperandPtr - A helper SDValue pointer class, that can handle
/// arrays of SDUse and arrays of SDValue objects. This is required
/// in many places inside the SelectionDAG.
///
class SDOperandPtr {
const SDOperand *ptr; // The pointer to the SDOperand object
int object_size; // The size of the object containg the SDOperand
const SDValue *ptr; // The pointer to the SDValue object
int object_size; // The size of the object containg the SDValue
public:
SDOperandPtr() : ptr(0), object_size(0) {}
SDOperandPtr(SDUse * use_ptr) {
ptr = &use_ptr->getSDOperand();
ptr = &use_ptr->getSDValue();
object_size = (int)sizeof(SDUse);
}
SDOperandPtr(const SDOperand * op_ptr) {
SDOperandPtr(const SDValue * op_ptr) {
ptr = op_ptr;
object_size = (int)sizeof(SDOperand);
object_size = (int)sizeof(SDValue);
}
const SDOperand operator *() { return *ptr; }
const SDOperand *operator ->() { return ptr; }
const SDValue operator *() { return *ptr; }
const SDValue *operator ->() { return ptr; }
SDOperandPtr operator ++ () {
ptr = (SDOperand*)((char *)ptr + object_size);
ptr = (SDValue*)((char *)ptr + object_size);
return *this;
}
SDOperandPtr operator ++ (int) {
SDOperandPtr tmp = *this;
ptr = (SDOperand*)((char *)ptr + object_size);
ptr = (SDValue*)((char *)ptr + object_size);
return tmp;
}
SDOperand operator[] (int idx) const {
return *(SDOperand*)((char*) ptr + object_size * idx);
SDValue operator[] (int idx) const {
return *(SDValue*)((char*) ptr + object_size * idx);
}
};
@ -1215,9 +1216,9 @@ public:
/// ConstantSDNode operand.
uint64_t getConstantOperandVal(unsigned Num) const;
const SDOperand &getOperand(unsigned Num) const {
const SDValue &getOperand(unsigned Num) const {
assert(Num < NumOperands && "Invalid child # of SDNode!");
return OperandList[Num].getSDOperand();
return OperandList[Num].getSDValue();
}
typedef SDUse* op_iterator;
@ -1276,7 +1277,7 @@ protected:
return Ret;
}
SDNode(unsigned Opc, SDVTList VTs, const SDOperand *Ops, unsigned NumOps)
SDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops, unsigned NumOps)
: NodeType(Opc), OperandsNeedDelete(true), SubclassData(0),
NodeId(-1), Uses(NULL) {
NumOperands = NumOps;
@ -1302,7 +1303,7 @@ protected:
for (unsigned i = 0; i != NumOps; ++i) {
OperandList[i] = Ops[i];
OperandList[i].setUser(this);
Ops[i].getSDOperand().Val->addUse(OperandList[i]);
Ops[i].getVal()->addUse(OperandList[i]);
}
ValueList = VTs.VTs;
@ -1352,36 +1353,36 @@ protected:
};
// Define inline functions from the SDOperand class.
// Define inline functions from the SDValue class.
inline unsigned SDOperand::getOpcode() const {
inline unsigned SDValue::getOpcode() const {
return Val->getOpcode();
}
inline MVT SDOperand::getValueType() const {
inline MVT SDValue::getValueType() const {
return Val->getValueType(ResNo);
}
inline unsigned SDOperand::getNumOperands() const {
inline unsigned SDValue::getNumOperands() const {
return Val->getNumOperands();
}
inline const SDOperand &SDOperand::getOperand(unsigned i) const {
inline const SDValue &SDValue::getOperand(unsigned i) const {
return Val->getOperand(i);
}
inline uint64_t SDOperand::getConstantOperandVal(unsigned i) const {
inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
return Val->getConstantOperandVal(i);
}
inline bool SDOperand::isTargetOpcode() const {
inline bool SDValue::isTargetOpcode() const {
return Val->isTargetOpcode();
}
inline bool SDOperand::isMachineOpcode() const {
inline bool SDValue::isMachineOpcode() const {
return Val->isMachineOpcode();
}
inline unsigned SDOperand::getMachineOpcode() const {
inline unsigned SDValue::getMachineOpcode() const {
return Val->getMachineOpcode();
}
inline bool SDOperand::use_empty() const {
inline bool SDValue::use_empty() const {
return !Val->hasAnyUseOfValue(ResNo);
}
inline bool SDOperand::hasOneUse() const {
inline bool SDValue::hasOneUse() const {
return Val->hasNUsesOfValue(1, ResNo);
}
@ -1391,7 +1392,7 @@ class UnarySDNode : public SDNode {
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
SDUse Op;
public:
UnarySDNode(unsigned Opc, SDVTList VTs, SDOperand X)
UnarySDNode(unsigned Opc, SDVTList VTs, SDValue X)
: SDNode(Opc, VTs) {
Op = X;
InitOperands(&Op, 1);
@ -1404,7 +1405,7 @@ class BinarySDNode : public SDNode {
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
SDUse Ops[2];
public:
BinarySDNode(unsigned Opc, SDVTList VTs, SDOperand X, SDOperand Y)
BinarySDNode(unsigned Opc, SDVTList VTs, SDValue X, SDValue Y)
: SDNode(Opc, VTs) {
Ops[0] = X;
Ops[1] = Y;
@ -1418,8 +1419,8 @@ class TernarySDNode : public SDNode {
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
SDUse Ops[3];
public:
TernarySDNode(unsigned Opc, SDVTList VTs, SDOperand X, SDOperand Y,
SDOperand Z)
TernarySDNode(unsigned Opc, SDVTList VTs, SDValue X, SDValue Y,
SDValue Z)
: SDNode(Opc, VTs) {
Ops[0] = X;
Ops[1] = Y;
@ -1440,9 +1441,9 @@ public:
// FIXME: Remove the "noinline" attribute once <rdar://problem/5852746> is
// fixed.
#ifdef __GNUC__
explicit __attribute__((__noinline__)) HandleSDNode(SDOperand X)
explicit __attribute__((__noinline__)) HandleSDNode(SDValue X)
#else
explicit HandleSDNode(SDOperand X)
explicit HandleSDNode(SDValue X)
#endif
: SDNode(ISD::HANDLENODE, getSDVTList(MVT::Other)) {
Op = X;
@ -1490,8 +1491,8 @@ public:
/// reference performed by operation.
MachineMemOperand getMemOperand() const;
const SDOperand &getChain() const { return getOperand(0); }
const SDOperand &getBasePtr() const {
const SDValue &getChain() const { return getOperand(0); }
const SDValue &getBasePtr() const {
return getOperand(getOpcode() == ISD::STORE ? 2 : 1);
}
@ -1524,13 +1525,13 @@ class AtomicSDNode : public MemSDNode {
// Opc: opcode for atomic
// VTL: value type list
// Chain: memory chain for operaand
// Ptr: address to update as a SDOperand
// Ptr: address to update as a SDValue
// Cmp: compare value
// Swp: swap value
// SrcVal: address to update as a Value (used for MemOperand)
// Align: alignment of memory
AtomicSDNode(unsigned Opc, SDVTList VTL, SDOperand Chain, SDOperand Ptr,
SDOperand Cmp, SDOperand Swp, const Value* SrcVal,
AtomicSDNode(unsigned Opc, SDVTList VTL, SDValue Chain, SDValue Ptr,
SDValue Cmp, SDValue Swp, const Value* SrcVal,
unsigned Align=0)
: MemSDNode(Opc, VTL, Cmp.getValueType(), SrcVal, /*SVOffset=*/0,
Align, /*isVolatile=*/true) {
@ -1540,8 +1541,8 @@ class AtomicSDNode : public MemSDNode {
Ops[3] = Cmp;
InitOperands(Ops, 4);
}
AtomicSDNode(unsigned Opc, SDVTList VTL, SDOperand Chain, SDOperand Ptr,
SDOperand Val, const Value* SrcVal, unsigned Align=0)
AtomicSDNode(unsigned Opc, SDVTList VTL, SDValue Chain, SDValue Ptr,
SDValue Val, const Value* SrcVal, unsigned Align=0)
: MemSDNode(Opc, VTL, Val.getValueType(), SrcVal, /*SVOffset=*/0,
Align, /*isVolatile=*/true) {
Ops[0] = Chain;
@ -1550,8 +1551,8 @@ class AtomicSDNode : public MemSDNode {
InitOperands(Ops, 3);
}
const SDOperand &getBasePtr() const { return getOperand(1); }
const SDOperand &getVal() const { return getOperand(2); }
const SDValue &getBasePtr() const { return getOperand(1); }
const SDValue &getVal() const { return getOperand(2); }
bool isCompareAndSwap() const { return getOpcode() == ISD::ATOMIC_CMP_SWAP; }
@ -1871,7 +1872,7 @@ class DbgStopPointSDNode : public SDNode {
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
protected:
friend class SelectionDAG;
DbgStopPointSDNode(SDOperand ch, unsigned l, unsigned c,
DbgStopPointSDNode(SDValue ch, unsigned l, unsigned c,
const CompileUnitDesc *cu)
: SDNode(ISD::DBG_STOPPOINT, getSDVTList(MVT::Other)),
Line(l), Column(c), CU(cu) {
@ -1895,7 +1896,7 @@ class LabelSDNode : public SDNode {
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
protected:
friend class SelectionDAG;
LabelSDNode(unsigned NodeTy, SDOperand ch, unsigned id)
LabelSDNode(unsigned NodeTy, SDValue ch, unsigned id)
: SDNode(NodeTy, getSDVTList(MVT::Other)), LabelID(id) {
Chain = ch;
InitOperands(&Chain, 1);
@ -2083,7 +2084,7 @@ protected:
*/
SDUse Ops[4];
public:
LSBaseSDNode(ISD::NodeType NodeTy, SDOperand *Operands, unsigned numOperands,
LSBaseSDNode(ISD::NodeType NodeTy, SDValue *Operands, unsigned numOperands,
SDVTList VTs, ISD::MemIndexedMode AM, MVT VT,
const Value *SV, int SVO, unsigned Align, bool Vol)
: MemSDNode(NodeTy, VTs, VT, SV, SVO, Align, Vol) {
@ -2096,7 +2097,7 @@ public:
"Only indexed loads and stores have a non-undef offset operand");
}
const SDOperand &getOffset() const {
const SDValue &getOffset() const {
return getOperand(getOpcode() == ISD::LOAD ? 2 : 3);
}
@ -2125,7 +2126,7 @@ class LoadSDNode : public LSBaseSDNode {
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
protected:
friend class SelectionDAG;
LoadSDNode(SDOperand *ChainPtrOff, SDVTList VTs,
LoadSDNode(SDValue *ChainPtrOff, SDVTList VTs,
ISD::MemIndexedMode AM, ISD::LoadExtType ETy, MVT LVT,
const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
: LSBaseSDNode(ISD::LOAD, ChainPtrOff, 3,
@ -2140,8 +2141,8 @@ public:
return ISD::LoadExtType((SubclassData >> 3) & 3);
}
const SDOperand &getBasePtr() const { return getOperand(1); }
const SDOperand &getOffset() const { return getOperand(2); }
const SDValue &getBasePtr() const { return getOperand(1); }
const SDValue &getOffset() const { return getOperand(2); }
static bool classof(const LoadSDNode *) { return true; }
static bool classof(const SDNode *N) {
@ -2155,7 +2156,7 @@ class StoreSDNode : public LSBaseSDNode {
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
protected:
friend class SelectionDAG;
StoreSDNode(SDOperand *ChainValuePtrOff, SDVTList VTs,
StoreSDNode(SDValue *ChainValuePtrOff, SDVTList VTs,
ISD::MemIndexedMode AM, bool isTrunc, MVT SVT,
const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
: LSBaseSDNode(ISD::STORE, ChainValuePtrOff, 4,
@ -2169,9 +2170,9 @@ public:
/// For floats, it is the same as doing an FP_ROUND and storing the result.
bool isTruncatingStore() const { return (SubclassData >> 3) & 1; }
const SDOperand &getValue() const { return getOperand(1); }
const SDOperand &getBasePtr() const { return getOperand(2); }
const SDOperand &getOffset() const { return getOperand(3); }
const SDValue &getValue() const { return getOperand(1); }
const SDValue &getBasePtr() const { return getOperand(2); }
const SDValue &getOffset() const { return getOperand(3); }
static bool classof(const StoreSDNode *) { return true; }
static bool classof(const SDNode *N) {

124
include/llvm/Target/TargetLowering.h
View File

@ -37,7 +37,7 @@ namespace llvm {
class MachineFrameInfo;
class MachineInstr;
class SDNode;
class SDOperand;
class SDValue;
class SelectionDAG;
class TargetData;
class TargetMachine;
@ -112,7 +112,7 @@ public:
/// getSetCCResultType - Return the ValueType of the result of setcc
/// operations.
virtual MVT getSetCCResultType(const SDOperand &) const;
virtual MVT getSetCCResultType(const SDValue &) const;
/// getSetCCResultContents - For targets without boolean registers, this flag
/// returns information about the contents of the high-bits in the setcc
@ -266,7 +266,7 @@ public:
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
/// are assumed to be legal.
virtual bool isShuffleMaskLegal(SDOperand Mask, MVT VT) const {
virtual bool isShuffleMaskLegal(SDValue Mask, MVT VT) const {
return true;
}
@ -274,7 +274,7 @@ public:
/// used by Targets can use this to indicate if there is a suitable
/// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
/// pool entry.
virtual bool isVectorClearMaskLegal(const std::vector<SDOperand> &BVOps,
virtual bool isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
MVT EVT,
SelectionDAG &DAG) const {
return false;
@ -603,8 +603,8 @@ public:
/// getPreIndexedAddressParts - returns true by value, base pointer and
/// offset pointer and addressing mode by reference if the node's address
/// can be legally represented as pre-indexed load / store address.
virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
SDOperand &Offset,
virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
SDValue &Offset,
ISD::MemIndexedMode &AM,
SelectionDAG &DAG) {
return false;
@ -614,7 +614,7 @@ public:
/// offset pointer and addressing mode by reference if this node can be
/// combined with a load / store to form a post-indexed load / store.
virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
SDOperand &Base, SDOperand &Offset,
SDValue &Base, SDValue &Offset,
ISD::MemIndexedMode &AM,
SelectionDAG &DAG) {
return false;
@ -622,7 +622,7 @@ public:
/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
/// jumptable.
virtual SDOperand getPICJumpTableRelocBase(SDOperand Table,
virtual SDValue getPICJumpTableRelocBase(SDValue Table,
SelectionDAG &DAG) const;
//===--------------------------------------------------------------------===//
@ -630,18 +630,18 @@ public:
//
/// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
/// SDOperands for returning information from TargetLowering to its clients
/// SDValues for returning information from TargetLowering to its clients
/// that want to combine
struct TargetLoweringOpt {
SelectionDAG &DAG;
bool AfterLegalize;
SDOperand Old;
SDOperand New;
SDValue Old;
SDValue New;
explicit TargetLoweringOpt(SelectionDAG &InDAG, bool afterLegalize)
: DAG(InDAG), AfterLegalize(afterLegalize) {}
bool CombineTo(SDOperand O, SDOperand N) {
bool CombineTo(SDValue O, SDValue N) {
Old = O;
New = N;
return true;
@ -651,7 +651,7 @@ public:
/// specified instruction is a constant integer. If so, check to see if
/// there are any bits set in the constant that are not demanded. If so,
/// shrink the constant and return true.
bool ShrinkDemandedConstant(SDOperand Op, const APInt &Demanded);
bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
};
/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
@ -662,14 +662,14 @@ public:
/// KnownZero bits for the expression (used to simplify the caller).
/// The KnownZero/One bits may only be accurate for those bits in the
/// DemandedMask.
bool SimplifyDemandedBits(SDOperand Op, const APInt &DemandedMask,
bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
APInt &KnownZero, APInt &KnownOne,
TargetLoweringOpt &TLO, unsigned Depth = 0) const;
/// computeMaskedBitsForTargetNode - Determine which of the bits specified in
/// Mask are known to be either zero or one and return them in the
/// KnownZero/KnownOne bitsets.
virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
virtual void computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
APInt &KnownZero,
APInt &KnownOne,
@ -679,7 +679,7 @@ public:
/// ComputeNumSignBitsForTargetNode - This method can be implemented by
/// targets that want to expose additional information about sign bits to the
/// DAG Combiner.
virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op,
virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
unsigned Depth = 0) const;
struct DAGCombinerInfo {
@ -696,14 +696,14 @@ public:
bool isCalledByLegalizer() const { return CalledByLegalizer; }
void AddToWorklist(SDNode *N);
SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To);
SDOperand CombineTo(SDNode *N, SDOperand Res);
SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1);
SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To);
SDValue CombineTo(SDNode *N, SDValue Res);
SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1);
};
/// SimplifySetCC - Try to simplify a setcc built with the specified operands
/// and cc. If it is unable to simplify it, return a null SDOperand.
SDOperand SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1,
/// and cc. If it is unable to simplify it, return a null SDValue.
SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
ISD::CondCode Cond, bool foldBooleans,
DAGCombinerInfo &DCI) const;
@ -724,14 +724,14 @@ public:
///
/// The semantics are as follows:
/// Return Value:
/// SDOperand.Val == 0 - No change was made
/// SDOperand.Val == N - N was replaced, is dead, and is already handled.
/// SDValue.Val == 0 - No change was made
/// SDValue.Val == N - N was replaced, is dead, and is already handled.
/// otherwise - N should be replaced by the returned Operand.
///
/// In addition, methods provided by DAGCombinerInfo may be used to perform
/// more complex transformations.
///
virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
//===--------------------------------------------------------------------===//
// TargetLowering Configuration Methods - These methods should be invoked by
@ -966,14 +966,14 @@ public:
/// lower the arguments for the specified function, into the specified DAG.
virtual void
LowerArguments(Function &F, SelectionDAG &DAG,
SmallVectorImpl<SDOperand>& ArgValues);
SmallVectorImpl<SDValue>& ArgValues);
/// LowerCallTo - This hook lowers an abstract call to a function into an
/// actual call. This returns a pair of operands. The first element is the
/// return value for the function (if RetTy is not VoidTy). The second
/// element is the outgoing token chain.
struct ArgListEntry {
SDOperand Node;
SDValue Node;
const Type* Ty;
bool isSExt : 1;
bool isZExt : 1;
@ -987,17 +987,17 @@ public:
isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
};
typedef std::vector<ArgListEntry> ArgListTy;
virtual std::pair<SDOperand, SDOperand>
LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
virtual std::pair<SDValue, SDValue>
LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
bool isVarArg, unsigned CallingConv, bool isTailCall,
SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
SDValue Callee, ArgListTy &Args, SelectionDAG &DAG);
/// EmitTargetCodeForMemcpy - Emit target-specific code that performs a
/// memcpy. This can be used by targets to provide code sequences for cases
/// that don't fit the target's parameters for simple loads/stores and can be
/// more efficient than using a library call. This function can return a null
/// SDOperand if the target declines to use custom code and a different
/// SDValue if the target declines to use custom code and a different
/// lowering strategy should be used.
///
/// If AlwaysInline is true, the size is constant and the target should not
@ -1006,46 +1006,46 @@ public:
/// expanded in a place where calls are not feasible (e.g. within the prologue
/// for another call). If the target chooses to decline an AlwaysInline
/// request here, legalize will resort to using simple loads and stores.
virtual SDOperand
virtual SDValue
EmitTargetCodeForMemcpy(SelectionDAG &DAG,
SDOperand Chain,
SDOperand Op1, SDOperand Op2,
SDOperand Op3, unsigned Align,
SDValue Chain,
SDValue Op1, SDValue Op2,
SDValue Op3, unsigned Align,
bool AlwaysInline,
const Value *DstSV, uint64_t DstOff,
const Value *SrcSV, uint64_t SrcOff) {
return SDOperand();
return SDValue();
}
/// EmitTargetCodeForMemmove - Emit target-specific code that performs a
/// memmove. This can be used by targets to provide code sequences for cases
/// that don't fit the target's parameters for simple loads/stores and can be
/// more efficient than using a library call. This function can return a null
/// SDOperand if the target declines to use custom code and a different
/// SDValue if the target declines to use custom code and a different
/// lowering strategy should be used.
virtual SDOperand
virtual SDValue
EmitTargetCodeForMemmove(SelectionDAG &DAG,
SDOperand Chain,
SDOperand Op1, SDOperand Op2,
SDOperand Op3, unsigned Align,
SDValue Chain,
SDValue Op1, SDValue Op2,
SDValue Op3, unsigned Align,
const Value *DstSV, uint64_t DstOff,
const Value *SrcSV, uint64_t SrcOff) {
return SDOperand();
return SDValue();
}
/// EmitTargetCodeForMemset - Emit target-specific code that performs a
/// memset. This can be used by targets to provide code sequences for cases
/// that don't fit the target's parameters for simple stores and can be more
/// efficient than using a library call. This function can return a null
/// SDOperand if the target declines to use custom code and a different
/// SDValue if the target declines to use custom code and a different
/// lowering strategy should be used.
virtual SDOperand
virtual SDValue
EmitTargetCodeForMemset(SelectionDAG &DAG,
SDOperand Chain,
SDOperand Op1, SDOperand Op2,
SDOperand Op3, unsigned Align,
SDValue Chain,
SDValue Op1, SDValue Op2,
SDValue Op3, unsigned Align,
const Value *DstSV, uint64_t DstOff) {
return SDOperand();
return SDValue();
}
/// LowerOperation - This callback is invoked for operations that are
@ -1053,7 +1053,7 @@ public:
/// and whose defined values are all legal.
/// If the target has no operations that require custom lowering, it need not
/// implement this. The default implementation of this aborts.
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
/// ReplaceNodeResults - This callback is invoked for operations that are
/// unsupported by the target, which are registered to use 'custom' lowering,
@ -1071,8 +1071,8 @@ public:
/// IsEligibleForTailCallOptimization - Check whether the call is eligible for
/// tail call optimization. Targets which want to do tail call optimization
/// should override this function.
virtual bool IsEligibleForTailCallOptimization(SDOperand Call,
SDOperand Ret,
virtual bool IsEligibleForTailCallOptimization(SDValue Call,
SDValue Ret,
SelectionDAG &DAG) const {
return false;
}
@ -1081,21 +1081,21 @@ public:
/// preceeds the RET node and whether the return uses the result of the node
/// or is a void return. This function can be used by the target to determine
/// eligiblity of tail call optimization.
static bool CheckTailCallReturnConstraints(SDOperand Call, SDOperand Ret) {
static bool CheckTailCallReturnConstraints(SDValue Call, SDValue Ret) {
unsigned NumOps = Ret.getNumOperands();
if ((NumOps == 1 &&
(Ret.getOperand(0) == SDOperand(Call.Val,1) ||
Ret.getOperand(0) == SDOperand(Call.Val,0))) ||
(Ret.getOperand(0) == SDValue(Call.Val,1) ||
Ret.getOperand(0) == SDValue(Call.Val,0))) ||
(NumOps > 1 &&
Ret.getOperand(0) == SDOperand(Call.Val,Call.Val->getNumValues()-1) &&
Ret.getOperand(1) == SDOperand(Call.Val,0)))
Ret.getOperand(0) == SDValue(Call.Val,Call.Val->getNumValues()-1) &&
Ret.getOperand(1) == SDValue(Call.Val,0)))
return true;
return false;
}
/// GetPossiblePreceedingTailCall - Get preceeding TailCallNodeOpCode node if
/// it exists skip possible ISD:TokenFactor.
static SDOperand GetPossiblePreceedingTailCall(SDOperand Chain,
static SDValue GetPossiblePreceedingTailCall(SDValue Chain,
unsigned TailCallNodeOpCode) {
if (Chain.getOpcode() == TailCallNodeOpCode) {
return Chain;
@ -1152,9 +1152,9 @@ public:
/// type to use for the specific AsmOperandInfo, setting
/// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
/// being passed in is available, it can be passed in as Op, otherwise an
/// empty SDOperand can be passed.
/// empty SDValue can be passed.
virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
SDOperand Op,
SDValue Op,
SelectionDAG *DAG = 0) const;
/// getConstraintType - Given a constraint, return the type of constraint it
@ -1190,8 +1190,8 @@ public:
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops.
virtual void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter,
std::vector<SDOperand> &Ops,
virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const;
//===--------------------------------------------------------------------===//
@ -1245,9 +1245,9 @@ public:
//===--------------------------------------------------------------------===//
// Div utility functions
//
SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG,
SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
std::vector<SDNode*>* Created) const;
SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG,
SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
std::vector<SDNode*>* Created) const;

1400
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

File diff suppressed because it is too large Load Diff

860
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

File diff suppressed because it is too large Load Diff

246
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
View File

@ -43,7 +43,7 @@ static RTLIB::Libcall GetFPLibCall(MVT VT,
void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
DEBUG(cerr << "Soften float result " << ResNo << ": "; N->dump(&DAG);
cerr << "\n");
SDOperand R = SDOperand();
SDValue R = SDValue();
switch (N->getOpcode()) {
default:
@ -76,14 +76,14 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
// If R is null, the sub-method took care of registering the result.
if (R.Val)
SetSoftenedFloat(SDOperand(N, ResNo), R);
SetSoftenedFloat(SDValue(N, ResNo), R);
}
SDOperand DAGTypeLegalizer::SoftenFloatRes_BIT_CONVERT(SDNode *N) {
SDValue DAGTypeLegalizer::SoftenFloatRes_BIT_CONVERT(SDNode *N) {
return BitConvertToInteger(N->getOperand(0));
}
SDOperand DAGTypeLegalizer::SoftenFloatRes_BUILD_PAIR(SDNode *N) {
SDValue DAGTypeLegalizer::SoftenFloatRes_BUILD_PAIR(SDNode *N) {
// Convert the inputs to integers, and build a new pair out of them.
return DAG.getNode(ISD::BUILD_PAIR,
TLI.getTypeToTransformTo(N->getValueType(0)),
@ -91,14 +91,14 @@ SDOperand DAGTypeLegalizer::SoftenFloatRes_BUILD_PAIR(SDNode *N) {
BitConvertToInteger(N->getOperand(1)));
}
SDOperand DAGTypeLegalizer::SoftenFloatRes_ConstantFP(ConstantFPSDNode *N) {
SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(ConstantFPSDNode *N) {
return DAG.getConstant(N->getValueAPF().convertToAPInt(),
TLI.getTypeToTransformTo(N->getValueType(0)));
}
SDOperand DAGTypeLegalizer::SoftenFloatRes_FADD(SDNode *N) {
SDValue DAGTypeLegalizer::SoftenFloatRes_FADD(SDNode *N) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDOperand Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
GetSoftenedFloat(N->getOperand(1)) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::ADD_F32,
@ -108,9 +108,9 @@ SDOperand DAGTypeLegalizer::SoftenFloatRes_FADD(SDNode *N) {
NVT, Ops, 2, false);
}
SDOperand DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(SDNode *N) {
SDOperand LHS = GetSoftenedFloat(N->getOperand(0));
SDOperand RHS = BitConvertToInteger(N->getOperand(1));
SDValue DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(SDNode *N) {
SDValue LHS = GetSoftenedFloat(N->getOperand(0));
SDValue RHS = BitConvertToInteger(N->getOperand(1));
MVT LVT = LHS.getValueType();
MVT RVT = RHS.getValueType();
@ -119,7 +119,7 @@ SDOperand DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(SDNode *N) {
unsigned RSize = RVT.getSizeInBits();
// First get the sign bit of second operand.
SDOperand SignBit = DAG.getNode(ISD::SHL, RVT, DAG.getConstant(1, RVT),
SDValue SignBit = DAG.getNode(ISD::SHL, RVT, DAG.getConstant(1, RVT),
DAG.getConstant(RSize - 1,
TLI.getShiftAmountTy()));
SignBit = DAG.getNode(ISD::AND, RVT, RHS, SignBit);
@ -137,7 +137,7 @@ SDOperand DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(SDNode *N) {
}
// Clear the sign bit of the first operand.
SDOperand Mask = DAG.getNode(ISD::SHL, LVT, DAG.getConstant(1, LVT),
SDValue Mask = DAG.getNode(ISD::SHL, LVT, DAG.getConstant(1, LVT),
DAG.getConstant(LSize - 1,
TLI.getShiftAmountTy()));
Mask = DAG.getNode(ISD::SUB, LVT, Mask, DAG.getConstant(1, LVT));
@ -147,9 +147,9 @@ SDOperand DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(SDNode *N) {
return DAG.getNode(ISD::OR, LVT, LHS, SignBit);
}
SDOperand DAGTypeLegalizer::SoftenFloatRes_FDIV(SDNode *N) {
SDValue DAGTypeLegalizer::SoftenFloatRes_FDIV(SDNode *N) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDOperand Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
GetSoftenedFloat(N->getOperand(1)) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::DIV_F32,
@ -159,9 +159,9 @@ SDOperand DAGTypeLegalizer::SoftenFloatRes_FDIV(SDNode *N) {
NVT, Ops, 2, false);
}
SDOperand DAGTypeLegalizer::SoftenFloatRes_FMUL(SDNode *N) {
SDValue DAGTypeLegalizer::SoftenFloatRes_FMUL(SDNode *N) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDOperand Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
GetSoftenedFloat(N->getOperand(1)) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::MUL_F32,
@ -171,25 +171,25 @@ SDOperand DAGTypeLegalizer::SoftenFloatRes_FMUL(SDNode *N) {
NVT, Ops, 2, false);
}
SDOperand DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(SDNode *N) {
SDValue DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(SDNode *N) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDOperand Op = N->getOperand(0);
SDValue Op = N->getOperand(0);
RTLIB::Libcall LC = RTLIB::getFPEXT(Op.getValueType(), N->getValueType(0));
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
return MakeLibCall(LC, NVT, &Op, 1, false);
}
SDOperand DAGTypeLegalizer::SoftenFloatRes_FP_ROUND(SDNode *N) {
SDValue DAGTypeLegalizer::SoftenFloatRes_FP_ROUND(SDNode *N) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDOperand Op = N->getOperand(0);
SDValue Op = N->getOperand(0);
RTLIB::Libcall LC = RTLIB::getFPROUND(Op.getValueType(), N->getValueType(0));
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
return MakeLibCall(LC, NVT, &Op, 1, false);
}
SDOperand DAGTypeLegalizer::SoftenFloatRes_FPOWI(SDNode *N) {
SDValue DAGTypeLegalizer::SoftenFloatRes_FPOWI(SDNode *N) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDOperand Ops[2] = { GetSoftenedFloat(N->getOperand(0)), N->getOperand(1) };
SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), N->getOperand(1) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::POWI_F32,
RTLIB::POWI_F64,
@ -198,9 +198,9 @@ SDOperand DAGTypeLegalizer::SoftenFloatRes_FPOWI(SDNode *N) {
NVT, Ops, 2, false);
}
SDOperand DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) {
SDValue DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDOperand Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
GetSoftenedFloat(N->getOperand(1)) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::SUB_F32,
@ -210,12 +210,12 @@ SDOperand DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) {
NVT, Ops, 2, false);
}
SDOperand DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N) {
SDValue DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N) {
LoadSDNode *L = cast<LoadSDNode>(N);
MVT VT = N->getValueType(0);
MVT NVT = TLI.getTypeToTransformTo(VT);
SDOperand NewL;
SDValue NewL;
if (L->getExtensionType() == ISD::NON_EXTLOAD) {
NewL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(),
NVT, L->getChain(), L->getBasePtr(), L->getOffset(),
@ -223,7 +223,7 @@ SDOperand DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N) {
L->isVolatile(), L->getAlignment());
// Legalized the chain result - switch anything that used the old chain to
// use the new one.
ReplaceValueWith(SDOperand(N, 1), NewL.getValue(1));
ReplaceValueWith(SDValue(N, 1), NewL.getValue(1));
return NewL;
}
@ -236,33 +236,33 @@ SDOperand DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N) {
L->isVolatile(), L->getAlignment());
// Legalized the chain result - switch anything that used the old chain to
// use the new one.
ReplaceValueWith(SDOperand(N, 1), NewL.getValue(1));
ReplaceValueWith(SDValue(N, 1), NewL.getValue(1));
return BitConvertToInteger(DAG.getNode(ISD::FP_EXTEND, VT, NewL));
}
SDOperand DAGTypeLegalizer::SoftenFloatRes_SELECT(SDNode *N) {
SDOperand LHS = GetSoftenedFloat(N->getOperand(1));
SDOperand RHS = GetSoftenedFloat(N->getOperand(2));
SDValue DAGTypeLegalizer::SoftenFloatRes_SELECT(SDNode *N) {
SDValue LHS = GetSoftenedFloat(N->getOperand(1));
SDValue RHS = GetSoftenedFloat(N->getOperand(2));
return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
}
SDOperand DAGTypeLegalizer::SoftenFloatRes_SELECT_CC(SDNode *N) {
SDOperand LHS = GetSoftenedFloat(N->getOperand(2));
SDOperand RHS = GetSoftenedFloat(N->getOperand(3));
SDValue DAGTypeLegalizer::SoftenFloatRes_SELECT_CC(SDNode *N) {
SDValue LHS = GetSoftenedFloat(N->getOperand(2));
SDValue RHS = GetSoftenedFloat(N->getOperand(3));
return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
N->getOperand(1), LHS, RHS, N->getOperand(4));
}
SDOperand DAGTypeLegalizer::SoftenFloatRes_SINT_TO_FP(SDNode *N) {
SDOperand Op = N->getOperand(0);
SDValue DAGTypeLegalizer::SoftenFloatRes_SINT_TO_FP(SDNode *N) {
SDValue Op = N->getOperand(0);
MVT RVT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), RVT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SINT_TO_FP!");
return MakeLibCall(LC, TLI.getTypeToTransformTo(RVT), &Op, 1, false);
}
SDOperand DAGTypeLegalizer::SoftenFloatRes_UINT_TO_FP(SDNode *N) {
SDOperand Op = N->getOperand(0);
SDValue DAGTypeLegalizer::SoftenFloatRes_UINT_TO_FP(SDNode *N) {
SDValue Op = N->getOperand(0);
MVT RVT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::getUINTTOFP(Op.getValueType(), RVT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UINT_TO_FP!");
@ -277,7 +277,7 @@ SDOperand DAGTypeLegalizer::SoftenFloatRes_UINT_TO_FP(SDNode *N) {
bool DAGTypeLegalizer::SoftenFloatOperand(SDNode *N, unsigned OpNo) {
DEBUG(cerr << "Soften float operand " << OpNo << ": "; N->dump(&DAG);
cerr << "\n");
SDOperand Res = SDOperand();
SDValue Res = SDValue();
switch (N->getOpcode()) {
default:
@ -313,16 +313,16 @@ bool DAGTypeLegalizer::SoftenFloatOperand(SDNode *N, unsigned OpNo) {
assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
"Invalid operand expansion");
ReplaceValueWith(SDOperand(N, 0), Res);
ReplaceValueWith(SDValue(N, 0), Res);
return false;
}
/// SoftenSetCCOperands - Soften the operands of a comparison. This code is
/// shared among BR_CC, SELECT_CC, and SETCC handlers.
void DAGTypeLegalizer::SoftenSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
void DAGTypeLegalizer::SoftenSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
ISD::CondCode &CCCode) {
SDOperand LHSInt = GetSoftenedFloat(NewLHS);
SDOperand RHSInt = GetSoftenedFloat(NewRHS);
SDValue LHSInt = GetSoftenedFloat(NewLHS);
SDValue RHSInt = GetSoftenedFloat(NewRHS);
MVT VT = NewLHS.getValueType();
assert((VT == MVT::f32 || VT == MVT::f64) && "Unsupported setcc type!");
@ -387,28 +387,28 @@ void DAGTypeLegalizer::SoftenSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
}
MVT RetVT = MVT::i32; // FIXME: is this the correct return type?
SDOperand Ops[2] = { LHSInt, RHSInt };
SDValue Ops[2] = { LHSInt, RHSInt };
NewLHS = MakeLibCall(LC1, RetVT, Ops, 2, false/*sign irrelevant*/);
NewRHS = DAG.getConstant(0, RetVT);
CCCode = TLI.getCmpLibcallCC(LC1);
if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
SDOperand Tmp = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(NewLHS),
SDValue Tmp = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(NewLHS),
NewLHS, NewRHS, DAG.getCondCode(CCCode));
NewLHS = MakeLibCall(LC2, RetVT, Ops, 2, false/*sign irrelevant*/);
NewLHS = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(NewLHS), NewLHS,
NewRHS, DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
NewLHS = DAG.getNode(ISD::OR, Tmp.getValueType(), Tmp, NewLHS);
NewRHS = SDOperand();
NewRHS = SDValue();
}
}
SDOperand DAGTypeLegalizer::SoftenFloatOp_BIT_CONVERT(SDNode *N) {
SDValue DAGTypeLegalizer::SoftenFloatOp_BIT_CONVERT(SDNode *N) {
return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0),
GetSoftenedFloat(N->getOperand(0)));
}
SDOperand DAGTypeLegalizer::SoftenFloatOp_BR_CC(SDNode *N) {
SDOperand NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
SDValue DAGTypeLegalizer::SoftenFloatOp_BR_CC(SDNode *N) {
SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
SoftenSetCCOperands(NewLHS, NewRHS, CCCode);
@ -420,29 +420,29 @@ SDOperand DAGTypeLegalizer::SoftenFloatOp_BR_CC(SDNode *N) {
}
// Update N to have the operands specified.
return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
DAG.getCondCode(CCCode), NewLHS, NewRHS,
N->getOperand(4));
}
SDOperand DAGTypeLegalizer::SoftenFloatOp_FP_TO_SINT(SDNode *N) {
SDValue DAGTypeLegalizer::SoftenFloatOp_FP_TO_SINT(SDNode *N) {
MVT RVT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::getFPTOSINT(N->getOperand(0).getValueType(), RVT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_SINT!");
SDOperand Op = GetSoftenedFloat(N->getOperand(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(LC, RVT, &Op, 1, false);
}
SDOperand DAGTypeLegalizer::SoftenFloatOp_FP_TO_UINT(SDNode *N) {
SDValue DAGTypeLegalizer::SoftenFloatOp_FP_TO_UINT(SDNode *N) {
MVT RVT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::getFPTOUINT(N->getOperand(0).getValueType(), RVT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_UINT!");
SDOperand Op = GetSoftenedFloat(N->getOperand(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(LC, RVT, &Op, 1, false);
}
SDOperand DAGTypeLegalizer::SoftenFloatOp_SELECT_CC(SDNode *N) {
SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
SDValue DAGTypeLegalizer::SoftenFloatOp_SELECT_CC(SDNode *N) {
SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
SoftenSetCCOperands(NewLHS, NewRHS, CCCode);
@ -454,13 +454,13 @@ SDOperand DAGTypeLegalizer::SoftenFloatOp_SELECT_CC(SDNode *N) {
}
// Update N to have the operands specified.
return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
N->getOperand(2), N->getOperand(3),
DAG.getCondCode(CCCode));
}
SDOperand DAGTypeLegalizer::SoftenFloatOp_SETCC(SDNode *N) {
SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
SDValue DAGTypeLegalizer::SoftenFloatOp_SETCC(SDNode *N) {
SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
SoftenSetCCOperands(NewLHS, NewRHS, CCCode);
@ -472,15 +472,15 @@ SDOperand DAGTypeLegalizer::SoftenFloatOp_SETCC(SDNode *N) {
}
// Otherwise, update N to have the operands specified.
return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
DAG.getCondCode(CCCode));
}
SDOperand DAGTypeLegalizer::SoftenFloatOp_STORE(SDNode *N, unsigned OpNo) {
SDValue DAGTypeLegalizer::SoftenFloatOp_STORE(SDNode *N, unsigned OpNo) {
assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
assert(OpNo == 1 && "Can only soften the stored value!");
StoreSDNode *ST = cast<StoreSDNode>(N);
SDOperand Val = ST->getValue();
SDValue Val = ST->getValue();
if (ST->isTruncatingStore())
// Do an FP_ROUND followed by a non-truncating store.
@ -505,8 +505,8 @@ SDOperand DAGTypeLegalizer::SoftenFloatOp_STORE(SDNode *N, unsigned OpNo) {
/// know that (at least) one result needs expansion.
void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
DEBUG(cerr << "Expand float result: "; N->dump(&DAG); cerr << "\n");
SDOperand Lo, Hi;
Lo = Hi = SDOperand();
SDValue Lo, Hi;
Lo = Hi = SDValue();
// See if the target wants to custom expand this node.
if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) ==
@ -554,11 +554,11 @@ void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
// If Lo/Hi is null, the sub-method took care of registering results etc.
if (Lo.Val)
SetExpandedFloat(SDOperand(N, ResNo), Lo, Hi);
SetExpandedFloat(SDValue(N, ResNo), Lo, Hi);
}
void DAGTypeLegalizer::ExpandFloatRes_ConstantFP(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
void DAGTypeLegalizer::ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo,
SDValue &Hi) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
assert(NVT.getSizeInBits() == integerPartWidth &&
"Do not know how to expand this float constant!");
@ -569,10 +569,10 @@ void DAGTypeLegalizer::ExpandFloatRes_ConstantFP(SDNode *N, SDOperand &Lo,
&C.getRawData()[0])), NVT);
}
void DAGTypeLegalizer::ExpandFloatRes_FADD(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
SDOperand Call = MakeLibCall(GetFPLibCall(N->getValueType(0),
void DAGTypeLegalizer::ExpandFloatRes_FADD(SDNode *N, SDValue &Lo,
SDValue &Hi) {
SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
SDValue Call = MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::ADD_F32,
RTLIB::ADD_F64,
RTLIB::ADD_F80,
@ -583,11 +583,11 @@ void DAGTypeLegalizer::ExpandFloatRes_FADD(SDNode *N, SDOperand &Lo,
Lo = Call.getOperand(0); Hi = Call.getOperand(1);
}
void DAGTypeLegalizer::ExpandFloatRes_FABS(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
void DAGTypeLegalizer::ExpandFloatRes_FABS(SDNode *N, SDValue &Lo,
SDValue &Hi) {
assert(N->getValueType(0) == MVT::ppcf128 &&
"Logic only correct for ppcf128!");
SDOperand Tmp;
SDValue Tmp;
GetExpandedFloat(N->getOperand(0), Lo, Tmp);
Hi = DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp);
// Lo = Hi==fabs(Hi) ? Lo : -Lo;
@ -596,10 +596,10 @@ void DAGTypeLegalizer::ExpandFloatRes_FABS(SDNode *N, SDOperand &Lo,
DAG.getCondCode(ISD::SETEQ));
}
void DAGTypeLegalizer::ExpandFloatRes_FDIV(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
SDOperand Call = MakeLibCall(GetFPLibCall(N->getValueType(0),
void DAGTypeLegalizer::ExpandFloatRes_FDIV(SDNode *N, SDValue &Lo,
SDValue &Hi) {
SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
SDValue Call = MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::DIV_F32,
RTLIB::DIV_F64,
RTLIB::DIV_F80,
@ -610,10 +610,10 @@ void DAGTypeLegalizer::ExpandFloatRes_FDIV(SDNode *N, SDOperand &Lo,
Lo = Call.getOperand(0); Hi = Call.getOperand(1);
}
void DAGTypeLegalizer::ExpandFloatRes_FMUL(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
SDOperand Call = MakeLibCall(GetFPLibCall(N->getValueType(0),
void DAGTypeLegalizer::ExpandFloatRes_FMUL(SDNode *N, SDValue &Lo,
SDValue &Hi) {
SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
SDValue Call = MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::MUL_F32,
RTLIB::MUL_F64,
RTLIB::MUL_F80,
@ -624,24 +624,24 @@ void DAGTypeLegalizer::ExpandFloatRes_FMUL(SDNode *N, SDOperand &Lo,
Lo = Call.getOperand(0); Hi = Call.getOperand(1);
}
void DAGTypeLegalizer::ExpandFloatRes_FNEG(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
void DAGTypeLegalizer::ExpandFloatRes_FNEG(SDNode *N, SDValue &Lo,
SDValue &Hi) {
GetExpandedFloat(N->getOperand(0), Lo, Hi);
Lo = DAG.getNode(ISD::FNEG, Lo.getValueType(), Lo);
Hi = DAG.getNode(ISD::FNEG, Hi.getValueType(), Hi);
}
void DAGTypeLegalizer::ExpandFloatRes_FP_EXTEND(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
void DAGTypeLegalizer::ExpandFloatRes_FP_EXTEND(SDNode *N, SDValue &Lo,
SDValue &Hi) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
Hi = DAG.getNode(ISD::FP_EXTEND, NVT, N->getOperand(0));
Lo = DAG.getConstantFP(APFloat(APInt(NVT.getSizeInBits(), 0)), NVT);
}
void DAGTypeLegalizer::ExpandFloatRes_FSUB(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
SDOperand Call = MakeLibCall(GetFPLibCall(N->getValueType(0),
void DAGTypeLegalizer::ExpandFloatRes_FSUB(SDNode *N, SDValue &Lo,
SDValue &Hi) {
SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
SDValue Call = MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::SUB_F32,
RTLIB::SUB_F64,
RTLIB::SUB_F80,
@ -652,8 +652,8 @@ void DAGTypeLegalizer::ExpandFloatRes_FSUB(SDNode *N, SDOperand &Lo,
Lo = Call.getOperand(0); Hi = Call.getOperand(1);
}
void DAGTypeLegalizer::ExpandFloatRes_LOAD(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
void DAGTypeLegalizer::ExpandFloatRes_LOAD(SDNode *N, SDValue &Lo,
SDValue &Hi) {
if (ISD::isNormalLoad(N)) {
ExpandRes_NormalLoad(N, Lo, Hi);
return;
@ -661,8 +661,8 @@ void DAGTypeLegalizer::ExpandFloatRes_LOAD(SDNode *N, SDOperand &Lo,
assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
LoadSDNode *LD = cast<LoadSDNode>(N);
SDOperand Chain = LD->getChain();
SDOperand Ptr = LD->getBasePtr();
SDValue Chain = LD->getChain();
SDValue Ptr = LD->getBasePtr();
MVT NVT = TLI.getTypeToTransformTo(LD->getValueType(0));
assert(NVT.isByteSized() && "Expanded type not byte sized!");
@ -681,15 +681,15 @@ void DAGTypeLegalizer::ExpandFloatRes_LOAD(SDNode *N, SDOperand &Lo,
// Modified the chain - switch anything that used the old chain to use the
// new one.
ReplaceValueWith(SDOperand(LD, 1), Chain);
ReplaceValueWith(SDValue(LD, 1), Chain);
}
void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
SDValue &Hi) {
assert(N->getValueType(0) == MVT::ppcf128 && "Unsupported XINT_TO_FP!");
MVT VT = N->getValueType(0);
MVT NVT = TLI.getTypeToTransformTo(VT);
SDOperand Src = N->getOperand(0);
SDValue Src = N->getOperand(0);
MVT SrcVT = Src.getValueType();
// First do an SINT_TO_FP, whether the original was signed or unsigned.
@ -760,11 +760,11 @@ void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDOperand &Lo,
/// need promotion or expansion as well as the specified one.
bool DAGTypeLegalizer::ExpandFloatOperand(SDNode *N, unsigned OpNo) {
DEBUG(cerr << "Expand float operand: "; N->dump(&DAG); cerr << "\n");
SDOperand Res = SDOperand();
SDValue Res = SDValue();
if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
== TargetLowering::Custom)
Res = TLI.LowerOperation(SDOperand(N, OpNo), DAG);
Res = TLI.LowerOperation(SDValue(N, OpNo), DAG);
if (Res.Val == 0) {
switch (N->getOpcode()) {
@ -806,16 +806,16 @@ bool DAGTypeLegalizer::ExpandFloatOperand(SDNode *N, unsigned OpNo) {
assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
"Invalid operand expansion");
ReplaceValueWith(SDOperand(N, 0), Res);
ReplaceValueWith(SDValue(N, 0), Res);
return false;
}
/// FloatExpandSetCCOperands - Expand the operands of a comparison. This code
/// is shared among BR_CC, SELECT_CC, and SETCC handlers.
void DAGTypeLegalizer::FloatExpandSetCCOperands(SDOperand &NewLHS,
SDOperand &NewRHS,
void DAGTypeLegalizer::FloatExpandSetCCOperands(SDValue &NewLHS,
SDValue &NewRHS,
ISD::CondCode &CCCode) {
SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
SDValue LHSLo, LHSHi, RHSLo, RHSHi;
GetExpandedFloat(NewLHS, LHSLo, LHSHi);
GetExpandedFloat(NewRHS, RHSLo, RHSHi);
@ -827,7 +827,7 @@ void DAGTypeLegalizer::FloatExpandSetCCOperands(SDOperand &NewLHS,
// BNE crN, L:
// FCMP crN, lo1, lo2
// The following can be improved, but not that much.
SDOperand Tmp1, Tmp2, Tmp3;
SDValue Tmp1, Tmp2, Tmp3;
Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ);
Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
@ -835,11 +835,11 @@ void DAGTypeLegalizer::FloatExpandSetCCOperands(SDOperand &NewLHS,
Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
NewLHS = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
NewRHS = SDOperand(); // LHS is the result, not a compare.
NewRHS = SDValue(); // LHS is the result, not a compare.
}
SDOperand DAGTypeLegalizer::ExpandFloatOp_BR_CC(SDNode *N) {
SDOperand NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
SDValue DAGTypeLegalizer::ExpandFloatOp_BR_CC(SDNode *N) {
SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode);
@ -851,36 +851,36 @@ SDOperand DAGTypeLegalizer::ExpandFloatOp_BR_CC(SDNode *N) {
}
// Update N to have the operands specified.
return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
DAG.getCondCode(CCCode), NewLHS, NewRHS,
N->getOperand(4));
}
SDOperand DAGTypeLegalizer::ExpandFloatOp_FP_ROUND(SDNode *N) {
SDValue DAGTypeLegalizer::ExpandFloatOp_FP_ROUND(SDNode *N) {
assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
"Logic only correct for ppcf128!");
SDOperand Lo, Hi;
SDValue Lo, Hi;
GetExpandedFloat(N->getOperand(0), Lo, Hi);
// Round it the rest of the way (e.g. to f32) if needed.
return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Hi, N->getOperand(1));
}
SDOperand DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(SDNode *N) {
SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(SDNode *N) {
MVT RVT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::getFPTOSINT(N->getOperand(0).getValueType(), RVT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_SINT!");
return MakeLibCall(LC, RVT, &N->getOperand(0), 1, false);
}
SDOperand DAGTypeLegalizer::ExpandFloatOp_FP_TO_UINT(SDNode *N) {
SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_UINT(SDNode *N) {
MVT RVT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::getFPTOUINT(N->getOperand(0).getValueType(), RVT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_UINT!");
return MakeLibCall(LC, N->getValueType(0), &N->getOperand(0), 1, false);
}
SDOperand DAGTypeLegalizer::ExpandFloatOp_SELECT_CC(SDNode *N) {
SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
SDValue DAGTypeLegalizer::ExpandFloatOp_SELECT_CC(SDNode *N) {
SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode);
@ -892,13 +892,13 @@ SDOperand DAGTypeLegalizer::ExpandFloatOp_SELECT_CC(SDNode *N) {
}
// Update N to have the operands specified.
return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
N->getOperand(2), N->getOperand(3),
DAG.getCondCode(CCCode));
}
SDOperand DAGTypeLegalizer::ExpandFloatOp_SETCC(SDNode *N) {
SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
SDValue DAGTypeLegalizer::ExpandFloatOp_SETCC(SDNode *N) {
SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode);
@ -910,11 +910,11 @@ SDOperand DAGTypeLegalizer::ExpandFloatOp_SETCC(SDNode *N) {
}
// Otherwise, update N to have the operands specified.
return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
DAG.getCondCode(CCCode));
}
SDOperand DAGTypeLegalizer::ExpandFloatOp_STORE(SDNode *N, unsigned OpNo) {
SDValue DAGTypeLegalizer::ExpandFloatOp_STORE(SDNode *N, unsigned OpNo) {
if (ISD::isNormalStore(N))
return ExpandOp_NormalStore(N, OpNo);
@ -922,14 +922,14 @@ SDOperand DAGTypeLegalizer::ExpandFloatOp_STORE(SDNode *N, unsigned OpNo) {
assert(OpNo == 1 && "Can only expand the stored value so far");
StoreSDNode *ST = cast<StoreSDNode>(N);
SDOperand Chain = ST->getChain();
SDOperand Ptr = ST->getBasePtr();
SDValue Chain = ST->getChain();
SDValue Ptr = ST->getBasePtr();
MVT NVT = TLI.getTypeToTransformTo(ST->getValue().getValueType());
assert(NVT.isByteSized() && "Expanded type not byte sized!");
assert(ST->getMemoryVT().bitsLE(NVT) && "Float type not round?");
SDOperand Lo, Hi;
SDValue Lo, Hi;
GetExpandedOp(ST->getValue(), Lo, Hi);
return DAG.getTruncStore(Chain, Lo, Ptr,

482
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

File diff suppressed because it is too large Load Diff

118
lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
View File

@ -29,7 +29,7 @@ void DAGTypeLegalizer::run() {
// The root of the dag may dangle to deleted nodes until the type legalizer is
// done. Set it to null to avoid confusion.
DAG.setRoot(SDOperand());
DAG.setRoot(SDValue());
// Walk all nodes in the graph, assigning them a NodeID of 'ReadyToProcess'
// (and remembering them) if they are leaves and assigning 'NewNode' if
@ -239,11 +239,11 @@ void DAGTypeLegalizer::AnalyzeNewNode(SDNode *&N) {
// replaced them, which can result in our node changing. Since remapping
// is rare, the code tries to minimize overhead in the non-remapping case.
SmallVector<SDOperand, 8> NewOps;
SmallVector<SDValue, 8> NewOps;
unsigned NumProcessed = 0;
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
SDOperand OrigOp = N->getOperand(i);
SDOperand Op = OrigOp;
SDValue OrigOp = N->getOperand(i);
SDValue Op = OrigOp;
if (Op.Val->getNodeId() == Processed)
RemapNode(Op);
@ -266,7 +266,7 @@ void DAGTypeLegalizer::AnalyzeNewNode(SDNode *&N) {
// Some operands changed - update the node.
if (!NewOps.empty())
N = DAG.UpdateNodeOperands(SDOperand(N, 0), &NewOps[0], NewOps.size()).Val;
N = DAG.UpdateNodeOperands(SDValue(N, 0), &NewOps[0], NewOps.size()).Val;
N->setNodeId(N->getNumOperands()-NumProcessed);
if (N->getNodeId() == ReadyToProcess)
@ -308,7 +308,7 @@ namespace {
/// ReplaceValueWith - The specified value was legalized to the specified other
/// value. If they are different, update the DAG and NodeIDs replacing any uses
/// of From to use To instead.
void DAGTypeLegalizer::ReplaceValueWith(SDOperand From, SDOperand To) {
void DAGTypeLegalizer::ReplaceValueWith(SDValue From, SDValue To) {
if (From == To) return;
// If expansion produced new nodes, make sure they are properly marked.
@ -347,14 +347,14 @@ void DAGTypeLegalizer::ReplaceNodeWith(SDNode *From, SDNode *To) {
for (unsigned i = 0, e = From->getNumValues(); i != e; ++i) {
assert(From->getValueType(i) == To->getValueType(i) &&
"Node results don't match");
ReplacedNodes[SDOperand(From, i)] = SDOperand(To, i);
ReplacedNodes[SDValue(From, i)] = SDValue(To, i);
}
}
/// RemapNode - If the specified value was already legalized to another value,
/// replace it by that value.
void DAGTypeLegalizer::RemapNode(SDOperand &N) {
DenseMap<SDOperand, SDOperand>::iterator I = ReplacedNodes.find(N);
void DAGTypeLegalizer::RemapNode(SDValue &N) {
DenseMap<SDValue, SDValue>::iterator I = ReplacedNodes.find(N);
if (I != ReplacedNodes.end()) {
// Use path compression to speed up future lookups if values get multiply
// replaced with other values.
@ -383,7 +383,7 @@ void DAGTypeLegalizer::ExpungeNode(SDNode *N) {
// If N is not remapped by ReplacedNodes then there is nothing to do.
unsigned i, e;
for (i = 0, e = N->getNumValues(); i != e; ++i)
if (ReplacedNodes.find(SDOperand(N, i)) != ReplacedNodes.end())
if (ReplacedNodes.find(SDValue(N, i)) != ReplacedNodes.end())
break;
if (i == e)
@ -391,80 +391,80 @@ void DAGTypeLegalizer::ExpungeNode(SDNode *N) {
// Remove N from all maps - this is expensive but rare.
for (DenseMap<SDOperand, SDOperand>::iterator I = PromotedIntegers.begin(),
for (DenseMap<SDValue, SDValue>::iterator I = PromotedIntegers.begin(),
E = PromotedIntegers.end(); I != E; ++I) {
assert(I->first.Val != N);
RemapNode(I->second);
}
for (DenseMap<SDOperand, SDOperand>::iterator I = SoftenedFloats.begin(),
for (DenseMap<SDValue, SDValue>::iterator I = SoftenedFloats.begin(),
E = SoftenedFloats.end(); I != E; ++I) {
assert(I->first.Val != N);
RemapNode(I->second);
}
for (DenseMap<SDOperand, SDOperand>::iterator I = ScalarizedVectors.begin(),
for (DenseMap<SDValue, SDValue>::iterator I = ScalarizedVectors.begin(),
E = ScalarizedVectors.end(); I != E; ++I) {
assert(I->first.Val != N);
RemapNode(I->second);
}
for (DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator
for (DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator
I = ExpandedIntegers.begin(), E = ExpandedIntegers.end(); I != E; ++I){
assert(I->first.Val != N);
RemapNode(I->second.first);
RemapNode(I->second.second);
}
for (DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator
for (DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator
I = ExpandedFloats.begin(), E = ExpandedFloats.end(); I != E; ++I) {
assert(I->first.Val != N);
RemapNode(I->second.first);
RemapNode(I->second.second);
}
for (DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator
for (DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator
I = SplitVectors.begin(), E = SplitVectors.end(); I != E; ++I) {
assert(I->first.Val != N);
RemapNode(I->second.first);
RemapNode(I->second.second);
}
for (DenseMap<SDOperand, SDOperand>::iterator I = ReplacedNodes.begin(),
for (DenseMap<SDValue, SDValue>::iterator I = ReplacedNodes.begin(),
E = ReplacedNodes.end(); I != E; ++I)
RemapNode(I->second);
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i)
ReplacedNodes.erase(SDOperand(N, i));
ReplacedNodes.erase(SDValue(N, i));
}
void DAGTypeLegalizer::SetPromotedInteger(SDOperand Op, SDOperand Result) {
void DAGTypeLegalizer::SetPromotedInteger(SDValue Op, SDValue Result) {
AnalyzeNewNode(Result.Val);
SDOperand &OpEntry = PromotedIntegers[Op];
SDValue &OpEntry = PromotedIntegers[Op];
assert(OpEntry.Val == 0 && "Node is already promoted!");
OpEntry = Result;
}
void DAGTypeLegalizer::SetSoftenedFloat(SDOperand Op, SDOperand Result) {
void DAGTypeLegalizer::SetSoftenedFloat(SDValue Op, SDValue Result) {
AnalyzeNewNode(Result.Val);
SDOperand &OpEntry = SoftenedFloats[Op];
SDValue &OpEntry = SoftenedFloats[Op];
assert(OpEntry.Val == 0 && "Node is already converted to integer!");
OpEntry = Result;
}
void DAGTypeLegalizer::SetScalarizedVector(SDOperand Op, SDOperand Result) {
void DAGTypeLegalizer::SetScalarizedVector(SDValue Op, SDValue Result) {
AnalyzeNewNode(Result.Val);
SDOperand &OpEntry = ScalarizedVectors[Op];
SDValue &OpEntry = ScalarizedVectors[Op];
assert(OpEntry.Val == 0 && "Node is already scalarized!");
OpEntry = Result;
}
void DAGTypeLegalizer::GetExpandedInteger(SDOperand Op, SDOperand &Lo,
SDOperand &Hi) {
std::pair<SDOperand, SDOperand> &Entry = ExpandedIntegers[Op];
void DAGTypeLegalizer::GetExpandedInteger(SDValue Op, SDValue &Lo,
SDValue &Hi) {
std::pair<SDValue, SDValue> &Entry = ExpandedIntegers[Op];
RemapNode(Entry.first);
RemapNode(Entry.second);
assert(Entry.first.Val && "Operand isn't expanded");
@ -472,22 +472,22 @@ void DAGTypeLegalizer::GetExpandedInteger(SDOperand Op, SDOperand &Lo,
Hi = Entry.second;
}
void DAGTypeLegalizer::SetExpandedInteger(SDOperand Op, SDOperand Lo,
SDOperand Hi) {
void DAGTypeLegalizer::SetExpandedInteger(SDValue Op, SDValue Lo,
SDValue Hi) {
// Lo/Hi may have been newly allocated, if so, add nodeid's as relevant.
AnalyzeNewNode(Lo.Val);
AnalyzeNewNode(Hi.Val);
// Remember that this is the result of the node.
std::pair<SDOperand, SDOperand> &Entry = ExpandedIntegers[Op];
std::pair<SDValue, SDValue> &Entry = ExpandedIntegers[Op];
assert(Entry.first.Val == 0 && "Node already expanded");
Entry.first = Lo;
Entry.second = Hi;
}
void DAGTypeLegalizer::GetExpandedFloat(SDOperand Op, SDOperand &Lo,
SDOperand &Hi) {
std::pair<SDOperand, SDOperand> &Entry = ExpandedFloats[Op];
void DAGTypeLegalizer::GetExpandedFloat(SDValue Op, SDValue &Lo,
SDValue &Hi) {
std::pair<SDValue, SDValue> &Entry = ExpandedFloats[Op];
RemapNode(Entry.first);
RemapNode(Entry.second);
assert(Entry.first.Val && "Operand isn't expanded");
@ -495,22 +495,22 @@ void DAGTypeLegalizer::GetExpandedFloat(SDOperand Op, SDOperand &Lo,
Hi = Entry.second;
}
void DAGTypeLegalizer::SetExpandedFloat(SDOperand Op, SDOperand Lo,
SDOperand Hi) {
void DAGTypeLegalizer::SetExpandedFloat(SDValue Op, SDValue Lo,
SDValue Hi) {
// Lo/Hi may have been newly allocated, if so, add nodeid's as relevant.
AnalyzeNewNode(Lo.Val);
AnalyzeNewNode(Hi.Val);
// Remember that this is the result of the node.
std::pair<SDOperand, SDOperand> &Entry = ExpandedFloats[Op];
std::pair<SDValue, SDValue> &Entry = ExpandedFloats[Op];
assert(Entry.first.Val == 0 && "Node already expanded");
Entry.first = Lo;
Entry.second = Hi;
}
void DAGTypeLegalizer::GetSplitVector(SDOperand Op, SDOperand &Lo,
SDOperand &Hi) {
std::pair<SDOperand, SDOperand> &Entry = SplitVectors[Op];
void DAGTypeLegalizer::GetSplitVector(SDValue Op, SDValue &Lo,
SDValue &Hi) {
std::pair<SDValue, SDValue> &Entry = SplitVectors[Op];
RemapNode(Entry.first);
RemapNode(Entry.second);
assert(Entry.first.Val && "Operand isn't split");
@ -518,14 +518,14 @@ void DAGTypeLegalizer::GetSplitVector(SDOperand Op, SDOperand &Lo,
Hi = Entry.second;
}
void DAGTypeLegalizer::SetSplitVector(SDOperand Op, SDOperand Lo,
SDOperand Hi) {
void DAGTypeLegalizer::SetSplitVector(SDValue Op, SDValue Lo,
SDValue Hi) {
// Lo/Hi may have been newly allocated, if so, add nodeid's as relevant.
AnalyzeNewNode(Lo.Val);
AnalyzeNewNode(Hi.Val);
// Remember that this is the result of the node.
std::pair<SDOperand, SDOperand> &Entry = SplitVectors[Op];
std::pair<SDValue, SDValue> &Entry = SplitVectors[Op];
assert(Entry.first.Val == 0 && "Node already split");
Entry.first = Lo;
Entry.second = Hi;
@ -537,27 +537,27 @@ void DAGTypeLegalizer::SetSplitVector(SDOperand Op, SDOperand Lo,
//===----------------------------------------------------------------------===//
/// BitConvertToInteger - Convert to an integer of the same size.
SDOperand DAGTypeLegalizer::BitConvertToInteger(SDOperand Op) {
SDValue DAGTypeLegalizer::BitConvertToInteger(SDValue Op) {
unsigned BitWidth = Op.getValueType().getSizeInBits();
return DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerVT(BitWidth), Op);
}
SDOperand DAGTypeLegalizer::CreateStackStoreLoad(SDOperand Op,
MVT DestVT) {
SDValue DAGTypeLegalizer::CreateStackStoreLoad(SDValue Op,
MVT DestVT) {
// Create the stack frame object. Make sure it is aligned for both
// the source and destination types.
unsigned SrcAlign =
TLI.getTargetData()->getPrefTypeAlignment(Op.getValueType().getTypeForMVT());
SDOperand FIPtr = DAG.CreateStackTemporary(DestVT, SrcAlign);
SDValue FIPtr = DAG.CreateStackTemporary(DestVT, SrcAlign);
// Emit a store to the stack slot.
SDOperand Store = DAG.getStore(DAG.getEntryNode(), Op, FIPtr, NULL, 0);
SDValue Store = DAG.getStore(DAG.getEntryNode(), Op, FIPtr, NULL, 0);
// Result is a load from the stack slot.
return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
}
/// JoinIntegers - Build an integer with low bits Lo and high bits Hi.
SDOperand DAGTypeLegalizer::JoinIntegers(SDOperand Lo, SDOperand Hi) {
SDValue DAGTypeLegalizer::JoinIntegers(SDValue Lo, SDValue Hi) {
MVT LVT = Lo.getValueType();
MVT HVT = Hi.getValueType();
MVT NVT = MVT::getIntegerVT(LVT.getSizeInBits() + HVT.getSizeInBits());
@ -571,9 +571,9 @@ SDOperand DAGTypeLegalizer::JoinIntegers(SDOperand Lo, SDOperand Hi) {
/// SplitInteger - Return the lower LoVT bits of Op in Lo and the upper HiVT
/// bits in Hi.
void DAGTypeLegalizer::SplitInteger(SDOperand Op,
void DAGTypeLegalizer::SplitInteger(SDValue Op,
MVT LoVT, MVT HiVT,
SDOperand &Lo, SDOperand &Hi) {
SDValue &Lo, SDValue &Hi) {
assert(LoVT.getSizeInBits() + HiVT.getSizeInBits() ==
Op.getValueType().getSizeInBits() && "Invalid integer splitting!");
Lo = DAG.getNode(ISD::TRUNCATE, LoVT, Op);
@ -585,17 +585,17 @@ void DAGTypeLegalizer::SplitInteger(SDOperand Op,
/// SplitInteger - Return the lower and upper halves of Op's bits in a value type
/// half the size of Op's.
void DAGTypeLegalizer::SplitInteger(SDOperand Op,
SDOperand &Lo, SDOperand &Hi) {
void DAGTypeLegalizer::SplitInteger(SDValue Op,
SDValue &Lo, SDValue &Hi) {
MVT HalfVT = MVT::getIntegerVT(Op.getValueType().getSizeInBits()/2);
SplitInteger(Op, HalfVT, HalfVT, Lo, Hi);
}
/// MakeLibCall - Generate a libcall taking the given operands as arguments and
/// returning a result of type RetVT.
SDOperand DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT RetVT,
const SDOperand *Ops, unsigned NumOps,
bool isSigned) {
SDValue DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT RetVT,
const SDValue *Ops, unsigned NumOps,
bool isSigned) {
TargetLowering::ArgListTy Args;
Args.reserve(NumOps);
@ -607,18 +607,18 @@ SDOperand DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT RetVT,
Entry.isZExt = !isSigned;
Args.push_back(Entry);
}
SDOperand Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
TLI.getPointerTy());
const Type *RetTy = RetVT.getTypeForMVT();
std::pair<SDOperand,SDOperand> CallInfo =
std::pair<SDValue,SDValue> CallInfo =
TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
CallingConv::C, false, Callee, Args, DAG);
return CallInfo.first;
}
SDOperand DAGTypeLegalizer::GetVectorElementPointer(SDOperand VecPtr, MVT EltVT,
SDOperand Index) {
SDValue DAGTypeLegalizer::GetVectorElementPointer(SDValue VecPtr, MVT EltVT,
SDValue Index) {
// Make sure the index type is big enough to compute in.
if (Index.getValueType().bitsGT(TLI.getPointerTy()))
Index = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Index);

410
lib/CodeGen/SelectionDAG/LegalizeTypes.h
View File

@ -112,31 +112,31 @@ private:
/// PromotedIntegers - For integer nodes that are below legal width, this map
/// indicates what promoted value to use.
DenseMap<SDOperand, SDOperand> PromotedIntegers;
DenseMap<SDValue, SDValue> PromotedIntegers;
/// ExpandedIntegers - For integer nodes that need to be expanded this map
/// indicates which operands are the expanded version of the input.
DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedIntegers;
DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedIntegers;
/// SoftenedFloats - For floating point nodes converted to integers of
/// the same size, this map indicates the converted value to use.
DenseMap<SDOperand, SDOperand> SoftenedFloats;
DenseMap<SDValue, SDValue> SoftenedFloats;
/// ExpandedFloats - For float nodes that need to be expanded this map
/// indicates which operands are the expanded version of the input.
DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedFloats;
DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedFloats;
/// ScalarizedVectors - For nodes that are <1 x ty>, this map indicates the
/// scalar value of type 'ty' to use.
DenseMap<SDOperand, SDOperand> ScalarizedVectors;
DenseMap<SDValue, SDValue> ScalarizedVectors;
/// SplitVectors - For nodes that need to be split this map indicates
/// which operands are the expanded version of the input.
DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > SplitVectors;
DenseMap<SDValue, std::pair<SDValue, SDValue> > SplitVectors;
/// ReplacedNodes - For nodes that have been replaced with another,
/// indicates the replacement node to use.
DenseMap<SDOperand, SDOperand> ReplacedNodes;
DenseMap<SDValue, SDValue> ReplacedNodes;
/// Worklist - This defines a worklist of nodes to process. In order to be
/// pushed onto this worklist, all operands of a node must have already been
@ -164,47 +164,47 @@ public:
ExpungeNode(Old);
ExpungeNode(New);
for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i)
ReplacedNodes[SDOperand(Old, i)] = SDOperand(New, i);
ReplacedNodes[SDValue(Old, i)] = SDValue(New, i);
}
private:
void AnalyzeNewNode(SDNode *&N);
void ReplaceValueWith(SDOperand From, SDOperand To);
void ReplaceValueWith(SDValue From, SDValue To);
void ReplaceNodeWith(SDNode *From, SDNode *To);
void RemapNode(SDOperand &N);
void RemapNode(SDValue &N);
void ExpungeNode(SDNode *N);
// Common routines.
SDOperand CreateStackStoreLoad(SDOperand Op, MVT DestVT);
SDOperand MakeLibCall(RTLIB::Libcall LC, MVT RetVT,
const SDOperand *Ops, unsigned NumOps, bool isSigned);
SDValue CreateStackStoreLoad(SDValue Op, MVT DestVT);
SDValue MakeLibCall(RTLIB::Libcall LC, MVT RetVT,
const SDValue *Ops, unsigned NumOps, bool isSigned);
SDOperand BitConvertToInteger(SDOperand Op);
SDOperand JoinIntegers(SDOperand Lo, SDOperand Hi);
void SplitInteger(SDOperand Op, SDOperand &Lo, SDOperand &Hi);
void SplitInteger(SDOperand Op, MVT LoVT, MVT HiVT,
SDOperand &Lo, SDOperand &Hi);
SDValue BitConvertToInteger(SDValue Op);
SDValue JoinIntegers(SDValue Lo, SDValue Hi);
void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
void SplitInteger(SDValue Op, MVT LoVT, MVT HiVT,
SDValue &Lo, SDValue &Hi);
SDOperand GetVectorElementPointer(SDOperand VecPtr, MVT EltVT,
SDOperand Index);
SDValue GetVectorElementPointer(SDValue VecPtr, MVT EltVT,
SDValue Index);
//===--------------------------------------------------------------------===//
// Integer Promotion Support: LegalizeIntegerTypes.cpp
//===--------------------------------------------------------------------===//
SDOperand GetPromotedInteger(SDOperand Op) {
SDOperand &PromotedOp = PromotedIntegers[Op];
SDValue GetPromotedInteger(SDValue Op) {
SDValue &PromotedOp = PromotedIntegers[Op];
RemapNode(PromotedOp);
assert(PromotedOp.Val && "Operand wasn't promoted?");
return PromotedOp;
}
void SetPromotedInteger(SDOperand Op, SDOperand Result);
void SetPromotedInteger(SDValue Op, SDValue Result);
/// ZExtPromotedInteger - Get a promoted operand and zero extend it to the
/// final size.
SDOperand ZExtPromotedInteger(SDOperand Op) {
SDValue ZExtPromotedInteger(SDValue Op) {
MVT OldVT = Op.getValueType();
Op = GetPromotedInteger(Op);
return DAG.getZeroExtendInReg(Op, OldVT);
@ -212,251 +212,251 @@ private:
// Integer Result Promotion.
void PromoteIntegerResult(SDNode *N, unsigned ResNo);
SDOperand PromoteIntRes_AssertSext(SDNode *N);
SDOperand PromoteIntRes_AssertZext(SDNode *N);
SDOperand PromoteIntRes_BIT_CONVERT(SDNode *N);
SDOperand PromoteIntRes_BSWAP(SDNode *N);
SDOperand PromoteIntRes_BUILD_PAIR(SDNode *N);
SDOperand PromoteIntRes_Constant(SDNode *N);
SDOperand PromoteIntRes_CTLZ(SDNode *N);
SDOperand PromoteIntRes_CTPOP(SDNode *N);
SDOperand PromoteIntRes_CTTZ(SDNode *N);
SDOperand PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N);
SDOperand PromoteIntRes_FP_TO_XINT(SDNode *N);
SDOperand PromoteIntRes_INT_EXTEND(SDNode *N);
SDOperand PromoteIntRes_LOAD(LoadSDNode *N);
SDOperand PromoteIntRes_SDIV(SDNode *N);
SDOperand PromoteIntRes_SELECT (SDNode *N);
SDOperand PromoteIntRes_SELECT_CC(SDNode *N);
SDOperand PromoteIntRes_SETCC(SDNode *N);
SDOperand PromoteIntRes_SHL(SDNode *N);
SDOperand PromoteIntRes_SimpleIntBinOp(SDNode *N);
SDOperand PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N);
SDOperand PromoteIntRes_SRA(SDNode *N);
SDOperand PromoteIntRes_SRL(SDNode *N);
SDOperand PromoteIntRes_TRUNCATE(SDNode *N);
SDOperand PromoteIntRes_UDIV(SDNode *N);
SDOperand PromoteIntRes_UNDEF(SDNode *N);
SDOperand PromoteIntRes_VAARG(SDNode *N);
SDValue PromoteIntRes_AssertSext(SDNode *N);
SDValue PromoteIntRes_AssertZext(SDNode *N);
SDValue PromoteIntRes_BIT_CONVERT(SDNode *N);
SDValue PromoteIntRes_BSWAP(SDNode *N);
SDValue PromoteIntRes_BUILD_PAIR(SDNode *N);
SDValue PromoteIntRes_Constant(SDNode *N);
SDValue PromoteIntRes_CTLZ(SDNode *N);
SDValue PromoteIntRes_CTPOP(SDNode *N);
SDValue PromoteIntRes_CTTZ(SDNode *N);
SDValue PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N);
SDValue PromoteIntRes_FP_TO_XINT(SDNode *N);
SDValue PromoteIntRes_INT_EXTEND(SDNode *N);
SDValue PromoteIntRes_LOAD(LoadSDNode *N);
SDValue PromoteIntRes_SDIV(SDNode *N);
SDValue PromoteIntRes_SELECT (SDNode *N);
SDValue PromoteIntRes_SELECT_CC(SDNode *N);
SDValue PromoteIntRes_SETCC(SDNode *N);
SDValue PromoteIntRes_SHL(SDNode *N);
SDValue PromoteIntRes_SimpleIntBinOp(SDNode *N);
SDValue PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N);
SDValue PromoteIntRes_SRA(SDNode *N);
SDValue PromoteIntRes_SRL(SDNode *N);
SDValue PromoteIntRes_TRUNCATE(SDNode *N);
SDValue PromoteIntRes_UDIV(SDNode *N);
SDValue PromoteIntRes_UNDEF(SDNode *N);
SDValue PromoteIntRes_VAARG(SDNode *N);
// Integer Operand Promotion.
bool PromoteIntegerOperand(SDNode *N, unsigned OperandNo);
SDOperand PromoteIntOp_ANY_EXTEND(SDNode *N);
SDOperand PromoteIntOp_BUILD_PAIR(SDNode *N);
SDOperand PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo);
SDOperand PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo);
SDOperand PromoteIntOp_BUILD_VECTOR(SDNode *N);
SDOperand PromoteIntOp_FP_EXTEND(SDNode *N);
SDOperand PromoteIntOp_FP_ROUND(SDNode *N);
SDOperand PromoteIntOp_INT_TO_FP(SDNode *N);
SDOperand PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, unsigned OpNo);
SDOperand PromoteIntOp_MEMBARRIER(SDNode *N);
SDOperand PromoteIntOp_SELECT(SDNode *N, unsigned OpNo);
SDOperand PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo);
SDOperand PromoteIntOp_SETCC(SDNode *N, unsigned OpNo);
SDOperand PromoteIntOp_SIGN_EXTEND(SDNode *N);
SDOperand PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo);
SDOperand PromoteIntOp_TRUNCATE(SDNode *N);
SDOperand PromoteIntOp_ZERO_EXTEND(SDNode *N);
SDValue PromoteIntOp_ANY_EXTEND(SDNode *N);
SDValue PromoteIntOp_BUILD_PAIR(SDNode *N);
SDValue PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo);
SDValue PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo);
SDValue PromoteIntOp_BUILD_VECTOR(SDNode *N);
SDValue PromoteIntOp_FP_EXTEND(SDNode *N);
SDValue PromoteIntOp_FP_ROUND(SDNode *N);
SDValue PromoteIntOp_INT_TO_FP(SDNode *N);
SDValue PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, unsigned OpNo);
SDValue PromoteIntOp_MEMBARRIER(SDNode *N);
SDValue PromoteIntOp_SELECT(SDNode *N, unsigned OpNo);
SDValue PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo);
SDValue PromoteIntOp_SETCC(SDNode *N, unsigned OpNo);
SDValue PromoteIntOp_SIGN_EXTEND(SDNode *N);
SDValue PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo);
SDValue PromoteIntOp_TRUNCATE(SDNode *N);
SDValue PromoteIntOp_ZERO_EXTEND(SDNode *N);
void PromoteSetCCOperands(SDOperand &LHS,SDOperand &RHS, ISD::CondCode Code);
void PromoteSetCCOperands(SDValue &LHS,SDValue &RHS, ISD::CondCode Code);
//===--------------------------------------------------------------------===//
// Integer Expansion Support: LegalizeIntegerTypes.cpp
//===--------------------------------------------------------------------===//
void GetExpandedInteger(SDOperand Op, SDOperand &Lo, SDOperand &Hi);
void SetExpandedInteger(SDOperand Op, SDOperand Lo, SDOperand Hi);
void GetExpandedInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
void SetExpandedInteger(SDValue Op, SDValue Lo, SDValue Hi);
// Integer Result Expansion.
void ExpandIntegerResult(SDNode *N, unsigned ResNo);
void ExpandIntRes_ANY_EXTEND (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_AssertSext (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_AssertZext (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_Constant (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_CTLZ (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_CTPOP (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_CTTZ (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_LOAD (LoadSDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_SIGN_EXTEND (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_SIGN_EXTEND_INREG (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_TRUNCATE (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_ZERO_EXTEND (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_FP_TO_SINT (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_FP_TO_UINT (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_ANY_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_AssertSext (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_AssertZext (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_Constant (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_CTLZ (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_CTPOP (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_CTTZ (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_LOAD (LoadSDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_SIGN_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_SIGN_EXTEND_INREG (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_TRUNCATE (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_ZERO_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_FP_TO_SINT (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_FP_TO_UINT (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_Logical (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_ADDSUB (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_ADDSUBC (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_ADDSUBE (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_BSWAP (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_MUL (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_SDIV (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_SREM (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_UDIV (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_UREM (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_Shift (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandIntRes_Logical (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_ADDSUB (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_ADDSUBC (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_ADDSUBE (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_BSWAP (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_MUL (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_SDIV (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_SREM (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_UDIV (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_UREM (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_Shift (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandShiftByConstant(SDNode *N, unsigned Amt,
SDOperand &Lo, SDOperand &Hi);
bool ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi);
SDValue &Lo, SDValue &Hi);
bool ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi);
// Integer Operand Expansion.
bool ExpandIntegerOperand(SDNode *N, unsigned OperandNo);
SDOperand ExpandIntOp_BIT_CONVERT(SDNode *N);
SDOperand ExpandIntOp_BR_CC(SDNode *N);
SDOperand ExpandIntOp_BUILD_VECTOR(SDNode *N);
SDOperand ExpandIntOp_EXTRACT_ELEMENT(SDNode *N);
SDOperand ExpandIntOp_SELECT_CC(SDNode *N);
SDOperand ExpandIntOp_SETCC(SDNode *N);
SDOperand ExpandIntOp_SINT_TO_FP(SDNode *N);
SDOperand ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo);
SDOperand ExpandIntOp_TRUNCATE(SDNode *N);
SDOperand ExpandIntOp_UINT_TO_FP(SDNode *N);
SDValue ExpandIntOp_BIT_CONVERT(SDNode *N);
SDValue ExpandIntOp_BR_CC(SDNode *N);
SDValue ExpandIntOp_BUILD_VECTOR(SDNode *N);
SDValue ExpandIntOp_EXTRACT_ELEMENT(SDNode *N);
SDValue ExpandIntOp_SELECT_CC(SDNode *N);
SDValue ExpandIntOp_SETCC(SDNode *N);
SDValue ExpandIntOp_SINT_TO_FP(SDNode *N);
SDValue ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo);
SDValue ExpandIntOp_TRUNCATE(SDNode *N);
SDValue ExpandIntOp_UINT_TO_FP(SDNode *N);
void IntegerExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
void IntegerExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
ISD::CondCode &CCCode);
//===--------------------------------------------------------------------===//
// Float to Integer Conversion Support: LegalizeFloatTypes.cpp
//===--------------------------------------------------------------------===//
SDOperand GetSoftenedFloat(SDOperand Op) {
SDOperand &SoftenedOp = SoftenedFloats[Op];
SDValue GetSoftenedFloat(SDValue Op) {
SDValue &SoftenedOp = SoftenedFloats[Op];
RemapNode(SoftenedOp);
assert(SoftenedOp.Val && "Operand wasn't converted to integer?");
return SoftenedOp;
}
void SetSoftenedFloat(SDOperand Op, SDOperand Result);
void SetSoftenedFloat(SDValue Op, SDValue Result);
// Result Float to Integer Conversion.
void SoftenFloatResult(SDNode *N, unsigned OpNo);
SDOperand SoftenFloatRes_BIT_CONVERT(SDNode *N);
SDOperand SoftenFloatRes_BUILD_PAIR(SDNode *N);
SDOperand SoftenFloatRes_ConstantFP(ConstantFPSDNode *N);
SDOperand SoftenFloatRes_FADD(SDNode *N);
SDOperand SoftenFloatRes_FCOPYSIGN(SDNode *N);
SDOperand SoftenFloatRes_FDIV(SDNode *N);
SDOperand SoftenFloatRes_FMUL(SDNode *N);
SDOperand SoftenFloatRes_FP_EXTEND(SDNode *N);
SDOperand SoftenFloatRes_FP_ROUND(SDNode *N);
SDOperand SoftenFloatRes_FPOWI(SDNode *N);
SDOperand SoftenFloatRes_FSUB(SDNode *N);
SDOperand SoftenFloatRes_LOAD(SDNode *N);
SDOperand SoftenFloatRes_SELECT(SDNode *N);
SDOperand SoftenFloatRes_SELECT_CC(SDNode *N);
SDOperand SoftenFloatRes_SINT_TO_FP(SDNode *N);
SDOperand SoftenFloatRes_UINT_TO_FP(SDNode *N);
SDValue SoftenFloatRes_BIT_CONVERT(SDNode *N);
SDValue SoftenFloatRes_BUILD_PAIR(SDNode *N);
SDValue SoftenFloatRes_ConstantFP(ConstantFPSDNode *N);
SDValue SoftenFloatRes_FADD(SDNode *N);
SDValue SoftenFloatRes_FCOPYSIGN(SDNode *N);
SDValue SoftenFloatRes_FDIV(SDNode *N);
SDValue SoftenFloatRes_FMUL(SDNode *N);
SDValue SoftenFloatRes_FP_EXTEND(SDNode *N);
SDValue SoftenFloatRes_FP_ROUND(SDNode *N);
SDValue SoftenFloatRes_FPOWI(SDNode *N);
SDValue SoftenFloatRes_FSUB(SDNode *N);
SDValue SoftenFloatRes_LOAD(SDNode *N);
SDValue SoftenFloatRes_SELECT(SDNode *N);
SDValue SoftenFloatRes_SELECT_CC(SDNode *N);
SDValue SoftenFloatRes_SINT_TO_FP(SDNode *N);
SDValue SoftenFloatRes_UINT_TO_FP(SDNode *N);
// Operand Float to Integer Conversion.
bool SoftenFloatOperand(SDNode *N, unsigned OpNo);
SDOperand SoftenFloatOp_BIT_CONVERT(SDNode *N);
SDOperand SoftenFloatOp_BR_CC(SDNode *N);
SDOperand SoftenFloatOp_FP_TO_SINT(SDNode *N);
SDOperand SoftenFloatOp_FP_TO_UINT(SDNode *N);
SDOperand SoftenFloatOp_SELECT_CC(SDNode *N);
SDOperand SoftenFloatOp_SETCC(SDNode *N);
SDOperand SoftenFloatOp_STORE(SDNode *N, unsigned OpNo);
SDValue SoftenFloatOp_BIT_CONVERT(SDNode *N);
SDValue SoftenFloatOp_BR_CC(SDNode *N);
SDValue SoftenFloatOp_FP_TO_SINT(SDNode *N);
SDValue SoftenFloatOp_FP_TO_UINT(SDNode *N);
SDValue SoftenFloatOp_SELECT_CC(SDNode *N);
SDValue SoftenFloatOp_SETCC(SDNode *N);
SDValue SoftenFloatOp_STORE(SDNode *N, unsigned OpNo);
void SoftenSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
void SoftenSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
ISD::CondCode &CCCode);
//===--------------------------------------------------------------------===//
// Float Expansion Support: LegalizeFloatTypes.cpp
//===--------------------------------------------------------------------===//
void GetExpandedFloat(SDOperand Op, SDOperand &Lo, SDOperand &Hi);
void SetExpandedFloat(SDOperand Op, SDOperand Lo, SDOperand Hi);
void GetExpandedFloat(SDValue Op, SDValue &Lo, SDValue &Hi);
void SetExpandedFloat(SDValue Op, SDValue Lo, SDValue Hi);
// Float Result Expansion.
void ExpandFloatResult(SDNode *N, unsigned ResNo);
void ExpandFloatRes_ConstantFP(SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandFloatRes_FABS (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandFloatRes_FADD (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandFloatRes_FDIV (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandFloatRes_FMUL (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandFloatRes_FNEG (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandFloatRes_FP_EXTEND (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandFloatRes_FSUB (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandFloatRes_LOAD (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandFloatRes_XINT_TO_FP(SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FABS (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FADD (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FDIV (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FMUL (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FNEG (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FP_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FSUB (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_LOAD (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, SDValue &Hi);
// Float Operand Expansion.
bool ExpandFloatOperand(SDNode *N, unsigned OperandNo);
SDOperand ExpandFloatOp_BR_CC(SDNode *N);
SDOperand ExpandFloatOp_FP_ROUND(SDNode *N);
SDOperand ExpandFloatOp_FP_TO_SINT(SDNode *N);
SDOperand ExpandFloatOp_FP_TO_UINT(SDNode *N);
SDOperand ExpandFloatOp_SELECT_CC(SDNode *N);
SDOperand ExpandFloatOp_SETCC(SDNode *N);
SDOperand ExpandFloatOp_STORE(SDNode *N, unsigned OpNo);
SDValue ExpandFloatOp_BR_CC(SDNode *N);
SDValue ExpandFloatOp_FP_ROUND(SDNode *N);
SDValue ExpandFloatOp_FP_TO_SINT(SDNode *N);
SDValue ExpandFloatOp_FP_TO_UINT(SDNode *N);
SDValue ExpandFloatOp_SELECT_CC(SDNode *N);
SDValue ExpandFloatOp_SETCC(SDNode *N);
SDValue ExpandFloatOp_STORE(SDNode *N, unsigned OpNo);
void FloatExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
void FloatExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
ISD::CondCode &CCCode);
//===--------------------------------------------------------------------===//
// Scalarization Support: LegalizeVectorTypes.cpp
//===--------------------------------------------------------------------===//
SDOperand GetScalarizedVector(SDOperand Op) {
SDOperand &ScalarizedOp = ScalarizedVectors[Op];
SDValue GetScalarizedVector(SDValue Op) {
SDValue &ScalarizedOp = ScalarizedVectors[Op];
RemapNode(ScalarizedOp);
assert(ScalarizedOp.Val && "Operand wasn't scalarized?");
return ScalarizedOp;
}
void SetScalarizedVector(SDOperand Op, SDOperand Result);
void SetScalarizedVector(SDValue Op, SDValue Result);
// Vector Result Scalarization: <1 x ty> -> ty.
void ScalarizeVectorResult(SDNode *N, unsigned OpNo);
SDOperand ScalarizeVecRes_BinOp(SDNode *N);
SDOperand ScalarizeVecRes_UnaryOp(SDNode *N);
SDValue ScalarizeVecRes_BinOp(SDNode *N);
SDValue ScalarizeVecRes_UnaryOp(SDNode *N);
SDOperand ScalarizeVecRes_BIT_CONVERT(SDNode *N);
SDOperand ScalarizeVecRes_FPOWI(SDNode *N);
SDOperand ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N);
SDOperand ScalarizeVecRes_LOAD(LoadSDNode *N);
SDOperand ScalarizeVecRes_SELECT(SDNode *N);
SDOperand ScalarizeVecRes_UNDEF(SDNode *N);
SDOperand ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N);
SDOperand ScalarizeVecRes_VSETCC(SDNode *N);
SDValue ScalarizeVecRes_BIT_CONVERT(SDNode *N);
SDValue ScalarizeVecRes_FPOWI(SDNode *N);
SDValue ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N);
SDValue ScalarizeVecRes_LOAD(LoadSDNode *N);
SDValue ScalarizeVecRes_SELECT(SDNode *N);
SDValue ScalarizeVecRes_UNDEF(SDNode *N);
SDValue ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N);
SDValue ScalarizeVecRes_VSETCC(SDNode *N);
// Vector Operand Scalarization: <1 x ty> -> ty.
bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo);
SDOperand ScalarizeVecOp_BIT_CONVERT(SDNode *N);
SDOperand ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
SDOperand ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo);
SDValue ScalarizeVecOp_BIT_CONVERT(SDNode *N);
SDValue ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
SDValue ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo);
//===--------------------------------------------------------------------===//
// Vector Splitting Support: LegalizeVectorTypes.cpp
//===--------------------------------------------------------------------===//
void GetSplitVector(SDOperand Op, SDOperand &Lo, SDOperand &Hi);
void SetSplitVector(SDOperand Op, SDOperand Lo, SDOperand Hi);
void GetSplitVector(SDValue Op, SDValue &Lo, SDValue &Hi);
void SetSplitVector(SDValue Op, SDValue Lo, SDValue Hi);
// Vector Result Splitting: <128 x ty> -> 2 x <64 x ty>.
void SplitVectorResult(SDNode *N, unsigned OpNo);
void SplitVecRes_BinOp(SDNode *N, SDOperand &Lo, SDOperand &Hi);
void SplitVecRes_UnaryOp(SDNode *N, SDOperand &Lo, SDOperand &Hi);
void SplitVecRes_BinOp(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_BIT_CONVERT(SDNode *N, SDOperand &Lo, SDOperand &Hi);
void SplitVecRes_BUILD_PAIR(SDNode *N, SDOperand &Lo, SDOperand &Hi);
void SplitVecRes_BUILD_VECTOR(SDNode *N, SDOperand &Lo, SDOperand &Hi);
void SplitVecRes_CONCAT_VECTORS(SDNode *N, SDOperand &Lo, SDOperand &Hi);
void SplitVecRes_FPOWI(SDNode *N, SDOperand &Lo, SDOperand &Hi);
void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDOperand &Lo, SDOperand &Hi);
void SplitVecRes_LOAD(LoadSDNode *N, SDOperand &Lo, SDOperand &Hi);
void SplitVecRes_UNDEF(SDNode *N, SDOperand &Lo, SDOperand &Hi);
void SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDOperand &Lo, SDOperand &Hi);
void SplitVecRes_VSETCC(SDNode *N, SDOperand &Lo, SDOperand &Hi);
void SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_BUILD_PAIR(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_LOAD(LoadSDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_VSETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
// Vector Operand Splitting: <128 x ty> -> 2 x <64 x ty>.
bool SplitVectorOperand(SDNode *N, unsigned OpNo);
SDOperand SplitVecOp_BIT_CONVERT(SDNode *N);
SDOperand SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N);
SDOperand SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
SDOperand SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo);
SDOperand SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo);
SDValue SplitVecOp_BIT_CONVERT(SDNode *N);
SDValue SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N);
SDValue SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
SDValue SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo);
SDValue SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo);
//===--------------------------------------------------------------------===//
// Generic Splitting: LegalizeTypesGeneric.cpp
@ -466,7 +466,7 @@ private:
// not necessarily identical types. As such they can be used for splitting
// vectors and expanding integers and floats.
void GetSplitOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi) {
void GetSplitOp(SDValue Op, SDValue &Lo, SDValue &Hi) {
if (Op.getValueType().isVector())
GetSplitVector(Op, Lo, Hi);
else if (Op.getValueType().isInteger())
@ -480,10 +480,10 @@ private:
void GetSplitDestVTs(MVT InVT, MVT &LoVT, MVT &HiVT);
// Generic Result Splitting.
void SplitRes_MERGE_VALUES(SDNode *N, SDOperand &Lo, SDOperand &Hi);
void SplitRes_SELECT (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void SplitRes_SELECT_CC (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void SplitRes_UNDEF (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void SplitRes_MERGE_VALUES(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitRes_SELECT (SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitRes_SELECT_CC (SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitRes_UNDEF (SDNode *N, SDValue &Lo, SDValue &Hi);
//===--------------------------------------------------------------------===//
// Generic Expansion: LegalizeTypesGeneric.cpp
@ -494,7 +494,7 @@ private:
// in memory on little/big-endian machines, followed by the Hi/Lo part. As
// such they can be used for expanding integers and floats.
void GetExpandedOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi) {
void GetExpandedOp(SDValue Op, SDValue &Lo, SDValue &Hi) {
if (Op.getValueType().isInteger())
GetExpandedInteger(Op, Lo, Hi);
else
@ -502,17 +502,17 @@ private:
}
// Generic Result Expansion.
void ExpandRes_BIT_CONVERT (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandRes_BUILD_PAIR (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandRes_EXTRACT_ELEMENT (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandRes_NormalLoad (SDNode *N, SDOperand &Lo, SDOperand &Hi);
void ExpandRes_BIT_CONVERT (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandRes_BUILD_PAIR (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandRes_EXTRACT_ELEMENT (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandRes_NormalLoad (SDNode *N, SDValue &Lo, SDValue &Hi);
// Generic Operand Expansion.
SDOperand ExpandOp_BIT_CONVERT (SDNode *N);
SDOperand ExpandOp_BUILD_VECTOR (SDNode *N);
SDOperand ExpandOp_EXTRACT_ELEMENT(SDNode *N);
SDOperand ExpandOp_NormalStore (SDNode *N, unsigned OpNo);
SDValue ExpandOp_BIT_CONVERT (SDNode *N);
SDValue ExpandOp_BUILD_VECTOR (SDNode *N);
SDValue ExpandOp_EXTRACT_ELEMENT(SDNode *N);
SDValue ExpandOp_NormalStore (SDNode *N, unsigned OpNo);
};

86
lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
View File

@ -28,10 +28,10 @@ using namespace llvm;
// little/big-endian machines, followed by the Hi/Lo part. This means that
// they cannot be used as is on vectors, for which Lo is always stored first.
void DAGTypeLegalizer::ExpandRes_BIT_CONVERT(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
void DAGTypeLegalizer::ExpandRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
SDValue &Hi) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDOperand InOp = N->getOperand(0);
SDValue InOp = N->getOperand(0);
MVT InVT = InOp.getValueType();
// Handle some special cases efficiently.
@ -74,21 +74,21 @@ void DAGTypeLegalizer::ExpandRes_BIT_CONVERT(SDNode *N, SDOperand &Lo,
}
// Lower the bit-convert to a store/load from the stack, then expand the load.
SDOperand Op = CreateStackStoreLoad(InOp, N->getValueType(0));
SDValue Op = CreateStackStoreLoad(InOp, N->getValueType(0));
ExpandRes_NormalLoad(Op.Val, Lo, Hi);
}
void DAGTypeLegalizer::ExpandRes_BUILD_PAIR(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
void DAGTypeLegalizer::ExpandRes_BUILD_PAIR(SDNode *N, SDValue &Lo,
SDValue &Hi) {
// Return the operands.
Lo = N->getOperand(0);
Hi = N->getOperand(1);
}
void DAGTypeLegalizer::ExpandRes_EXTRACT_ELEMENT(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
void DAGTypeLegalizer::ExpandRes_EXTRACT_ELEMENT(SDNode *N, SDValue &Lo,
SDValue &Hi) {
GetExpandedOp(N->getOperand(0), Lo, Hi);
SDOperand Part = cast<ConstantSDNode>(N->getOperand(1))->getValue() ? Hi : Lo;
SDValue Part = cast<ConstantSDNode>(N->getOperand(1))->getValue() ? Hi : Lo;
assert(Part.getValueType() == N->getValueType(0) &&
"Type twice as big as expanded type not itself expanded!");
@ -100,9 +100,9 @@ void DAGTypeLegalizer::ExpandRes_EXTRACT_ELEMENT(SDNode *N, SDOperand &Lo,
DAG.getConstant(1, TLI.getPointerTy()));
}
void DAGTypeLegalizer::ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
SDOperand OldVec = N->getOperand(0);
void DAGTypeLegalizer::ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo,
SDValue &Hi) {
SDValue OldVec = N->getOperand(0);
unsigned OldElts = OldVec.getValueType().getVectorNumElements();
// Convert to a vector of the expanded element type, for example
@ -110,12 +110,12 @@ void DAGTypeLegalizer::ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDOperand &Lo,
MVT OldVT = N->getValueType(0);
MVT NewVT = TLI.getTypeToTransformTo(OldVT);
SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT,
SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT,
MVT::getVectorVT(NewVT, 2*OldElts),
OldVec);
// Extract the elements at 2 * Idx and 2 * Idx + 1 from the new vector.
SDOperand Idx = N->getOperand(1);
SDValue Idx = N->getOperand(1);
// Make sure the type of Idx is big enough to hold the new values.
if (Idx.getValueType().bitsLT(TLI.getPointerTy()))
@ -132,14 +132,14 @@ void DAGTypeLegalizer::ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDOperand &Lo,
std::swap(Lo, Hi);
}
void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDValue &Lo,
SDValue &Hi) {
assert(ISD::isNormalLoad(N) && "This routine only for normal loads!");
LoadSDNode *LD = cast<LoadSDNode>(N);
MVT NVT = TLI.getTypeToTransformTo(LD->getValueType(0));
SDOperand Chain = LD->getChain();
SDOperand Ptr = LD->getBasePtr();
SDValue Chain = LD->getChain();
SDValue Ptr = LD->getBasePtr();
int SVOffset = LD->getSrcValueOffset();
unsigned Alignment = LD->getAlignment();
bool isVolatile = LD->isVolatile();
@ -167,7 +167,7 @@ void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDOperand &Lo,
// Modified the chain - switch anything that used the old chain to use
// the new one.
ReplaceValueWith(SDOperand(N, 1), Chain);
ReplaceValueWith(SDValue(N, 1), Chain);
}
@ -175,7 +175,7 @@ void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDOperand &Lo,
// Generic Operand Expansion.
//===--------------------------------------------------------------------===//
SDOperand DAGTypeLegalizer::ExpandOp_BIT_CONVERT(SDNode *N) {
SDValue DAGTypeLegalizer::ExpandOp_BIT_CONVERT(SDNode *N) {
if (N->getValueType(0).isVector()) {
// An illegal expanding type is being converted to a legal vector type.
// Make a two element vector out of the expanded parts and convert that
@ -186,13 +186,13 @@ SDOperand DAGTypeLegalizer::ExpandOp_BIT_CONVERT(SDNode *N) {
MVT NVT = MVT::getVectorVT(TLI.getTypeToTransformTo(OVT), 2);
if (isTypeLegal(NVT)) {
SDOperand Parts[2];
SDValue Parts[2];
GetExpandedOp(N->getOperand(0), Parts[0], Parts[1]);
if (TLI.isBigEndian())
std::swap(Parts[0], Parts[1]);
SDOperand Vec = DAG.getNode(ISD::BUILD_VECTOR, NVT, Parts, 2);
SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, NVT, Parts, 2);
return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Vec);
}
}
@ -201,7 +201,7 @@ SDOperand DAGTypeLegalizer::ExpandOp_BIT_CONVERT(SDNode *N) {
return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
}
SDOperand DAGTypeLegalizer::ExpandOp_BUILD_VECTOR(SDNode *N) {
SDValue DAGTypeLegalizer::ExpandOp_BUILD_VECTOR(SDNode *N) {
// The vector type is legal but the element type needs expansion.
MVT VecVT = N->getValueType(0);
unsigned NumElts = VecVT.getVectorNumElements();
@ -210,11 +210,11 @@ SDOperand DAGTypeLegalizer::ExpandOp_BUILD_VECTOR(SDNode *N) {
// Build a vector of twice the length out of the expanded elements.
// For example <3 x i64> -> <6 x i32>.
std::vector<SDOperand> NewElts;
std::vector<SDValue> NewElts;
NewElts.reserve(NumElts*2);
for (unsigned i = 0; i < NumElts; ++i) {
SDOperand Lo, Hi;
SDValue Lo, Hi;
GetExpandedOp(N->getOperand(i), Lo, Hi);
if (TLI.isBigEndian())
std::swap(Lo, Hi);
@ -222,7 +222,7 @@ SDOperand DAGTypeLegalizer::ExpandOp_BUILD_VECTOR(SDNode *N) {
NewElts.push_back(Hi);
}
SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR,
SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR,
MVT::getVectorVT(NewVT, NewElts.size()),
&NewElts[0], NewElts.size());
@ -230,20 +230,20 @@ SDOperand DAGTypeLegalizer::ExpandOp_BUILD_VECTOR(SDNode *N) {
return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
}
SDOperand DAGTypeLegalizer::ExpandOp_EXTRACT_ELEMENT(SDNode *N) {
SDOperand Lo, Hi;
SDValue DAGTypeLegalizer::ExpandOp_EXTRACT_ELEMENT(SDNode *N) {
SDValue Lo, Hi;
GetExpandedOp(N->getOperand(0), Lo, Hi);
return cast<ConstantSDNode>(N->getOperand(1))->getValue() ? Hi : Lo;
}
SDOperand DAGTypeLegalizer::ExpandOp_NormalStore(SDNode *N, unsigned OpNo) {
SDValue DAGTypeLegalizer::ExpandOp_NormalStore(SDNode *N, unsigned OpNo) {
assert(ISD::isNormalStore(N) && "This routine only for normal stores!");
assert(OpNo == 1 && "Can only expand the stored value so far");
StoreSDNode *St = cast<StoreSDNode>(N);
MVT NVT = TLI.getTypeToTransformTo(St->getValue().getValueType());
SDOperand Chain = St->getChain();
SDOperand Ptr = St->getBasePtr();
SDValue Chain = St->getChain();
SDValue Ptr = St->getBasePtr();
int SVOffset = St->getSrcValueOffset();
unsigned Alignment = St->getAlignment();
bool isVolatile = St->isVolatile();
@ -251,7 +251,7 @@ SDOperand DAGTypeLegalizer::ExpandOp_NormalStore(SDNode *N, unsigned OpNo) {
assert(NVT.isByteSized() && "Expanded type not byte sized!");
unsigned IncrementSize = NVT.getSizeInBits() / 8;
SDOperand Lo, Hi;
SDValue Lo, Hi;
GetExpandedOp(St->getValue(), Lo, Hi);
if (TLI.isBigEndian())
@ -280,7 +280,7 @@ SDOperand DAGTypeLegalizer::ExpandOp_NormalStore(SDNode *N, unsigned OpNo) {
// little-endian).
void DAGTypeLegalizer::SplitRes_MERGE_VALUES(SDNode *N,
SDOperand &Lo, SDOperand &Hi) {
SDValue &Lo, SDValue &Hi) {
// A MERGE_VALUES node can produce any number of values. We know that the
// first illegal one needs to be expanded into Lo/Hi.
unsigned i;
@ -288,7 +288,7 @@ void DAGTypeLegalizer::SplitRes_MERGE_VALUES(SDNode *N,
// The string of legal results gets turns into the input operands, which have
// the same type.
for (i = 0; isTypeLegal(N->getValueType(i)); ++i)
ReplaceValueWith(SDOperand(N, i), SDOperand(N->getOperand(i)));
ReplaceValueWith(SDValue(N, i), SDValue(N->getOperand(i)));
// The first illegal result must be the one that needs to be expanded.
GetSplitOp(N->getOperand(i), Lo, Hi);
@ -297,23 +297,23 @@ void DAGTypeLegalizer::SplitRes_MERGE_VALUES(SDNode *N,
// legal or not.
unsigned e = N->getNumValues();
for (++i; i != e; ++i)
ReplaceValueWith(SDOperand(N, i), SDOperand(N->getOperand(i)));
ReplaceValueWith(SDValue(N, i), SDValue(N->getOperand(i)));
}
void DAGTypeLegalizer::SplitRes_SELECT(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
SDOperand LL, LH, RL, RH;
void DAGTypeLegalizer::SplitRes_SELECT(SDNode *N, SDValue &Lo,
SDValue &Hi) {
SDValue LL, LH, RL, RH;
GetSplitOp(N->getOperand(1), LL, LH);
GetSplitOp(N->getOperand(2), RL, RH);
SDOperand Cond = N->getOperand(0);
SDValue Cond = N->getOperand(0);
Lo = DAG.getNode(ISD::SELECT, LL.getValueType(), Cond, LL, RL);
Hi = DAG.getNode(ISD::SELECT, LH.getValueType(), Cond, LH, RH);
}
void DAGTypeLegalizer::SplitRes_SELECT_CC(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
SDOperand LL, LH, RL, RH;
void DAGTypeLegalizer::SplitRes_SELECT_CC(SDNode *N, SDValue &Lo,
SDValue &Hi) {
SDValue LL, LH, RL, RH;
GetSplitOp(N->getOperand(2), LL, LH);
GetSplitOp(N->getOperand(3), RL, RH);
@ -323,7 +323,7 @@ void DAGTypeLegalizer::SplitRes_SELECT_CC(SDNode *N, SDOperand &Lo,
N->getOperand(1), LH, RH, N->getOperand(4));
}
void DAGTypeLegalizer::SplitRes_UNDEF(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
void DAGTypeLegalizer::SplitRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi) {
MVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
Lo = DAG.getNode(ISD::UNDEF, LoVT);

194
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -30,7 +30,7 @@ using namespace llvm;
void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
DEBUG(cerr << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);
cerr << "\n");
SDOperand R = SDOperand();
SDValue R = SDValue();
switch (N->getOpcode()) {
default:
@ -84,29 +84,29 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
// If R is null, the sub-method took care of registering the result.
if (R.Val)
SetScalarizedVector(SDOperand(N, ResNo), R);
SetScalarizedVector(SDValue(N, ResNo), R);
}
SDOperand DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
SDOperand LHS = GetScalarizedVector(N->getOperand(0));
SDOperand RHS = GetScalarizedVector(N->getOperand(1));
SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
SDValue LHS = GetScalarizedVector(N->getOperand(0));
SDValue RHS = GetScalarizedVector(N->getOperand(1));
return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
}
SDOperand DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
MVT NewVT = N->getValueType(0).getVectorElementType();
return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0));
}
SDOperand DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
SDOperand Op = GetScalarizedVector(N->getOperand(0));
SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
SDValue Op = GetScalarizedVector(N->getOperand(0));
return DAG.getNode(ISD::FPOWI, Op.getValueType(), Op, N->getOperand(1));
}
SDOperand DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
// The value to insert may have a wider type than the vector element type,
// so be sure to truncate it to the element type if necessary.
SDOperand Op = N->getOperand(1);
SDValue Op = N->getOperand(1);
MVT EltVT = N->getValueType(0).getVectorElementType();
if (Op.getValueType() != EltVT)
// FIXME: Can this happen for floating point types?
@ -114,47 +114,47 @@ SDOperand DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
return Op;
}
SDOperand DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
assert(ISD::isNormalLoad(N) && "Extending load of one-element vector?");
SDOperand Result = DAG.getLoad(N->getValueType(0).getVectorElementType(),
SDValue Result = DAG.getLoad(N->getValueType(0).getVectorElementType(),
N->getChain(), N->getBasePtr(),
N->getSrcValue(), N->getSrcValueOffset(),
N->isVolatile(), N->getAlignment());
// Legalized the chain result - switch anything that used the old chain to
// use the new one.
ReplaceValueWith(SDOperand(N, 1), Result.getValue(1));
ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
return Result;
}
SDOperand DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
// Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
MVT DestVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDOperand Op = GetScalarizedVector(N->getOperand(0));
SDValue Op = GetScalarizedVector(N->getOperand(0));
return DAG.getNode(N->getOpcode(), DestVT, Op);
}
SDOperand DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
}
SDOperand DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
SDOperand LHS = GetScalarizedVector(N->getOperand(1));
SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
SDValue LHS = GetScalarizedVector(N->getOperand(1));
return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0), LHS,
GetScalarizedVector(N->getOperand(2)));
}
SDOperand DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
// Figure out if the scalar is the LHS or RHS and return it.
SDOperand EltNum = N->getOperand(2).getOperand(0);
SDValue EltNum = N->getOperand(2).getOperand(0);
unsigned Op = cast<ConstantSDNode>(EltNum)->getValue() != 0;
return GetScalarizedVector(N->getOperand(Op));
}
SDOperand DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
MVT NewVT = N->getValueType(0).getVectorElementType();
SDOperand LHS = GetScalarizedVector(N->getOperand(0));
SDOperand RHS = GetScalarizedVector(N->getOperand(1));
SDValue LHS = GetScalarizedVector(N->getOperand(0));
SDValue RHS = GetScalarizedVector(N->getOperand(1));
LHS = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, RHS,
N->getOperand(2));
return
@ -172,7 +172,7 @@ SDOperand DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
DEBUG(cerr << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);
cerr << "\n");
SDOperand Res = SDOperand();
SDValue Res = SDValue();
if (Res.Val == 0) {
switch (N->getOpcode()) {
@ -211,27 +211,27 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
"Invalid operand expansion");
ReplaceValueWith(SDOperand(N, 0), Res);
ReplaceValueWith(SDValue(N, 0), Res);
return false;
}
/// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs
/// to be scalarized, it must be <1 x ty>. Convert the element instead.
SDOperand DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) {
SDOperand Elt = GetScalarizedVector(N->getOperand(0));
SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) {
SDValue Elt = GetScalarizedVector(N->getOperand(0));
return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Elt);
}
/// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
/// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
/// index.
SDOperand DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
return GetScalarizedVector(N->getOperand(0));
}
/// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
/// scalarized, it must be <1 x ty>. Just store the element.
SDOperand DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
assert(ISD::isNormalStore(N) && "Truncating store of one-element vector?");
assert(OpNo == 1 && "Do not know how to scalarize this operand!");
return DAG.getStore(N->getChain(), GetScalarizedVector(N->getOperand(1)),
@ -251,7 +251,7 @@ SDOperand DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
/// splitting.
void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n");
SDOperand Lo, Hi;
SDValue Lo, Hi;
switch (N->getOpcode()) {
default:
@ -309,28 +309,28 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
// If Lo/Hi is null, the sub-method took care of registering results etc.
if (Lo.Val)
SetSplitVector(SDOperand(N, ResNo), Lo, Hi);
SetSplitVector(SDValue(N, ResNo), Lo, Hi);
}
void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
SDOperand LHSLo, LHSHi;
void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
SDValue &Hi) {
SDValue LHSLo, LHSHi;
GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
SDOperand RHSLo, RHSHi;
SDValue RHSLo, RHSHi;
GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
Lo = DAG.getNode(N->getOpcode(), LHSLo.getValueType(), LHSLo, RHSLo);
Hi = DAG.getNode(N->getOpcode(), LHSHi.getValueType(), LHSHi, RHSHi);
}
void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
SDValue &Hi) {
// We know the result is a vector. The input may be either a vector or a
// scalar value.
MVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
SDOperand InOp = N->getOperand(0);
SDValue InOp = N->getOperand(0);
MVT InVT = InOp.getValueType();
// Handle some special cases efficiently.
@ -379,20 +379,20 @@ void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDOperand &Lo,
Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
}
void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
SDValue &Hi) {
MVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
unsigned LoNumElts = LoVT.getVectorNumElements();
SmallVector<SDOperand, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size());
SmallVector<SDOperand, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &HiOps[0], HiOps.size());
}
void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
SDValue &Hi) {
assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
unsigned NumSubvectors = N->getNumOperands() / 2;
if (NumSubvectors == 1) {
@ -404,25 +404,25 @@ void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDOperand &Lo,
MVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
SmallVector<SDOperand, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
Lo = DAG.getNode(ISD::CONCAT_VECTORS, LoVT, &LoOps[0], LoOps.size());
SmallVector<SDOperand, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
Hi = DAG.getNode(ISD::CONCAT_VECTORS, HiVT, &HiOps[0], HiOps.size());
}
void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
SDValue &Hi) {
GetSplitVector(N->getOperand(0), Lo, Hi);
Lo = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Lo, N->getOperand(1));
Hi = DAG.getNode(ISD::FPOWI, Hi.getValueType(), Hi, N->getOperand(1));
}
void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
SDOperand Vec = N->getOperand(0);
SDOperand Elt = N->getOperand(1);
SDOperand Idx = N->getOperand(2);
void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
SDValue &Hi) {
SDValue Vec = N->getOperand(0);
SDValue Elt = N->getOperand(1);
SDValue Idx = N->getOperand(2);
GetSplitVector(Vec, Lo, Hi);
if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
@ -439,29 +439,29 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDOperand &Lo,
// Spill the vector to the stack.
MVT VecVT = Vec.getValueType();
MVT EltVT = VecVT.getVectorElementType();
SDOperand StackPtr = DAG.CreateStackTemporary(VecVT);
SDOperand Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
// Store the new element. This may be larger than the vector element type,
// so use a truncating store.
SDOperand EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
Store = DAG.getTruncStore(Store, Elt, EltPtr, NULL, 0, EltVT);
// Reload the vector from the stack.
SDOperand Load = DAG.getLoad(VecVT, Store, StackPtr, NULL, 0);
SDValue Load = DAG.getLoad(VecVT, Store, StackPtr, NULL, 0);
// Split it.
SplitVecRes_LOAD(cast<LoadSDNode>(Load.Val), Lo, Hi);
}
void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDOperand &Lo,
SDOperand &Hi) {
void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
SDValue &Hi) {
assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
MVT LoVT, HiVT;
GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
SDOperand Ch = LD->getChain();
SDOperand Ptr = LD->getBasePtr();
SDValue Ch = LD->getChain();
SDValue Ptr = LD->getBasePtr();
const Value *SV = LD->getSrcValue();
int SVOffset = LD->getSrcValueOffset();
unsigned Alignment = LD->getAlignment();
@ -490,11 +490,11 @@ void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDOperand &Lo,
// Legalized the chain result - switch anything that used the old chain to
// use the new one.
ReplaceValueWith(SDOperand(LD, 1), Ch);
ReplaceValueWith(SDValue(LD, 1), Ch);
}
void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
SDValue &Hi) {
// Get the dest types - they may not match the input types, e.g. int_to_fp.
MVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
@ -504,11 +504,11 @@ void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDOperand &Lo,
Hi = DAG.getNode(N->getOpcode(), HiVT, Hi);
}
void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
SDValue &Hi) {
// Build the low part.
SDOperand Mask = N->getOperand(2);
SmallVector<SDOperand, 16> Ops;
SDValue Mask = N->getOperand(2);
SmallVector<SDValue, 16> Ops;
MVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
MVT EltVT = LoVT.getVectorElementType();
@ -520,7 +520,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDOperand &Lo,
// to be legalized, so this makes the code simpler.
for (unsigned i = 0; i != LoNumElts; ++i) {
unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
SDOperand InVec = N->getOperand(0);
SDValue InVec = N->getOperand(0);
if (Idx >= NumElements) {
InVec = N->getOperand(1);
Idx -= NumElements;
@ -533,7 +533,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDOperand &Lo,
for (unsigned i = LoNumElts; i != NumElements; ++i) {
unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
SDOperand InVec = N->getOperand(0);
SDValue InVec = N->getOperand(0);
if (Idx >= NumElements) {
InVec = N->getOperand(1);
Idx -= NumElements;
@ -544,12 +544,12 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDOperand &Lo,
Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &Ops[0], Ops.size());
}
void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDValue &Lo,
SDValue &Hi) {
MVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
SDOperand LL, LH, RL, RH;
SDValue LL, LH, RL, RH;
GetSplitVector(N->getOperand(0), LL, LH);
GetSplitVector(N->getOperand(1), RL, RH);
@ -568,7 +568,7 @@ void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDOperand &Lo,
/// node may need legalization as well as the specified one.
bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
SDOperand Res = SDOperand();
SDValue Res = SDValue();
if (Res.Val == 0) {
switch (N->getOpcode()) {
@ -605,15 +605,15 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
"Invalid operand expansion");
ReplaceValueWith(SDOperand(N, 0), Res);
ReplaceValueWith(SDValue(N, 0), Res);
return false;
}
SDOperand DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
// For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
// end up being split all the way down to individual components. Convert the
// split pieces into integers and reassemble.
SDOperand Lo, Hi;
SDValue Lo, Hi;
GetSplitVector(N->getOperand(0), Lo, Hi);
Lo = BitConvertToInteger(Lo);
Hi = BitConvertToInteger(Hi);
@ -625,12 +625,12 @@ SDOperand DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
JoinIntegers(Lo, Hi));
}
SDOperand DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
// We know that the extracted result type is legal. For now, assume the index
// is a constant.
MVT SubVT = N->getValueType(0);
SDOperand Idx = N->getOperand(1);
SDOperand Lo, Hi;
SDValue Idx = N->getOperand(1);
SDValue Lo, Hi;
GetSplitVector(N->getOperand(0), Lo, Hi);
uint64_t LoElts = Lo.getValueType().getVectorNumElements();
@ -646,48 +646,48 @@ SDOperand DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
}
}
SDOperand DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
SDOperand Vec = N->getOperand(0);
SDOperand Idx = N->getOperand(1);
SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
SDValue Vec = N->getOperand(0);
SDValue Idx = N->getOperand(1);
MVT VecVT = Vec.getValueType();
if (isa<ConstantSDNode>(Idx)) {
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue();
assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
SDOperand Lo, Hi;
SDValue Lo, Hi;
GetSplitVector(Vec, Lo, Hi);
uint64_t LoElts = Lo.getValueType().getVectorNumElements();
if (IdxVal < LoElts)
return DAG.UpdateNodeOperands(SDOperand(N, 0), Lo, Idx);
return DAG.UpdateNodeOperands(SDValue(N, 0), Lo, Idx);
else
return DAG.UpdateNodeOperands(SDOperand(N, 0), Hi,
return DAG.UpdateNodeOperands(SDValue(N, 0), Hi,
DAG.getConstant(IdxVal - LoElts,
Idx.getValueType()));
}
// Store the vector to the stack.
MVT EltVT = VecVT.getVectorElementType();
SDOperand StackPtr = DAG.CreateStackTemporary(VecVT);
SDOperand Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
// Load back the required element.
StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
return DAG.getLoad(EltVT, Store, StackPtr, NULL, 0);
}
SDOperand DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
assert(ISD::isNormalStore(N) && "Truncating store of vector?");
assert(OpNo == 1 && "Can only split the stored value");
SDOperand Ch = N->getChain();
SDOperand Ptr = N->getBasePtr();
SDValue Ch = N->getChain();
SDValue Ptr = N->getBasePtr();
int SVOffset = N->getSrcValueOffset();
unsigned Alignment = N->getAlignment();
bool isVol = N->isVolatile();
SDOperand Lo, Hi;
SDValue Lo, Hi;
GetSplitVector(N->getOperand(1), Lo, Hi);
unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
@ -703,9 +703,9 @@ SDOperand DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
}
SDOperand DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo){
SDValue DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo){
assert(OpNo == 2 && "Shuffle source type differs from result type?");
SDOperand Mask = N->getOperand(2);
SDValue Mask = N->getOperand(2);
unsigned MaskLength = Mask.getValueType().getVectorNumElements();
unsigned LargestMaskEntryPlusOne = 2 * MaskLength;
unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne);
@ -740,13 +740,13 @@ SDOperand DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo){
continue;
// Success! Rebuild the vector using the legal types.
SmallVector<SDOperand, 16> Ops(MaskLength);
SmallVector<SDValue, 16> Ops(MaskLength);
for (unsigned i = 0; i < MaskLength; ++i) {
uint64_t Idx =
cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
Ops[i] = DAG.getConstant(Idx, OpVT);
}
return DAG.UpdateNodeOperands(SDOperand(N,0),
return DAG.UpdateNodeOperands(SDValue(N,0),
N->getOperand(0), N->getOperand(1),
DAG.getNode(ISD::BUILD_VECTOR,
VecVT, &Ops[0], Ops.size()));
@ -756,5 +756,5 @@ SDOperand DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo){
break;
}
assert(false && "Failed to find an appropriate mask type!");
return SDOperand(N, 0);
return SDValue(N, 0);
}

40
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
View File

@ -136,7 +136,7 @@ void ScheduleDAG::BuildSchedUnits() {
// have a user of the flag operand.
N = NI;
while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
SDOperand FlagVal(N, N->getNumValues()-1);
SDValue FlagVal(N, N->getNumValues()-1);
// There are either zero or one users of the Flag result.
bool HasFlagUse = false;
@ -408,11 +408,11 @@ getInstrOperandRegClass(const TargetRegisterInfo *TRI,
/// implicit physical register output.
void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
bool IsClone, unsigned SrcReg,
DenseMap<SDOperand, unsigned> &VRBaseMap) {
DenseMap<SDValue, unsigned> &VRBaseMap) {
unsigned VRBase = 0;
if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
// Just use the input register directly!
SDOperand Op(Node, ResNo);
SDValue Op(Node, ResNo);
if (IsClone)
VRBaseMap.erase(Op);
bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
@ -439,7 +439,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
Match = false;
} else {
for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
SDOperand Op = User->getOperand(i);
SDValue Op = User->getOperand(i);
if (Op.Val != Node || Op.ResNo != ResNo)
continue;
MVT VT = Node->getValueType(Op.ResNo);
@ -472,7 +472,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
TII->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, DstRC, SrcRC);
}
SDOperand Op(Node, ResNo);
SDValue Op(Node, ResNo);
if (IsClone)
VRBaseMap.erase(Op);
bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
@ -500,7 +500,7 @@ unsigned ScheduleDAG::getDstOfOnlyCopyToRegUse(SDNode *Node,
void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
const TargetInstrDesc &II,
DenseMap<SDOperand, unsigned> &VRBaseMap) {
DenseMap<SDValue, unsigned> &VRBaseMap) {
assert(Node->getMachineOpcode() != TargetInstrInfo::IMPLICIT_DEF &&
"IMPLICIT_DEF should have been handled as a special case elsewhere!");
@ -533,7 +533,7 @@ void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
MI->addOperand(MachineOperand::CreateReg(VRBase, true));
}
SDOperand Op(Node, i);
SDValue Op(Node, i);
bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
isNew = isNew; // Silence compiler warning.
assert(isNew && "Node emitted out of order - early");
@ -542,8 +542,8 @@ void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
/// getVR - Return the virtual register corresponding to the specified result
/// of the specified node.
unsigned ScheduleDAG::getVR(SDOperand Op,
DenseMap<SDOperand, unsigned> &VRBaseMap) {
unsigned ScheduleDAG::getVR(SDValue Op,
DenseMap<SDValue, unsigned> &VRBaseMap) {
if (Op.isMachineOpcode() &&
Op.getMachineOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
// Add an IMPLICIT_DEF instruction before every use.
@ -558,7 +558,7 @@ unsigned ScheduleDAG::getVR(SDOperand Op,
return VReg;
}
DenseMap<SDOperand, unsigned>::iterator I = VRBaseMap.find(Op);
DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
assert(I != VRBaseMap.end() && "Node emitted out of order - late");
return I->second;
}
@ -568,10 +568,10 @@ unsigned ScheduleDAG::getVR(SDOperand Op,
/// specifies the instruction information for the node, and IIOpNum is the
/// operand number (in the II) that we are adding. IIOpNum and II are used for
/// assertions only.
void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
void ScheduleDAG::AddOperand(MachineInstr *MI, SDValue Op,
unsigned IIOpNum,
const TargetInstrDesc *II,
DenseMap<SDOperand, unsigned> &VRBaseMap) {
DenseMap<SDValue, unsigned> &VRBaseMap) {
if (Op.isMachineOpcode()) {
// Note that this case is redundant with the final else block, but we
// include it because it is the most common and it makes the logic
@ -702,7 +702,7 @@ getSuperRegisterRegClass(const TargetRegisterClass *TRC,
/// EmitSubregNode - Generate machine code for subreg nodes.
///
void ScheduleDAG::EmitSubregNode(SDNode *Node,
DenseMap<SDOperand, unsigned> &VRBaseMap) {
DenseMap<SDValue, unsigned> &VRBaseMap) {
unsigned VRBase = 0;
unsigned Opc = Node->getMachineOpcode();
@ -752,9 +752,9 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
BB->push_back(MI);
} else if (Opc == TargetInstrInfo::INSERT_SUBREG ||
Opc == TargetInstrInfo::SUBREG_TO_REG) {
SDOperand N0 = Node->getOperand(0);
SDOperand N1 = Node->getOperand(1);
SDOperand N2 = Node->getOperand(2);
SDValue N0 = Node->getOperand(0);
SDValue N1 = Node->getOperand(1);
SDValue N2 = Node->getOperand(2);
unsigned SubReg = getVR(N1, VRBaseMap);
unsigned SubIdx = cast<ConstantSDNode>(N2)->getValue();
@ -788,7 +788,7 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
} else
assert(0 && "Node is not insert_subreg, extract_subreg, or subreg_to_reg");
SDOperand Op(Node, 0);
SDValue Op(Node, 0);
bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
isNew = isNew; // Silence compiler warning.
assert(isNew && "Node emitted out of order - early");
@ -797,7 +797,7 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
/// EmitNode - Generate machine code for an node and needed dependencies.
///
void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone,
DenseMap<SDOperand, unsigned> &VRBaseMap) {
DenseMap<SDValue, unsigned> &VRBaseMap) {
// If machine instruction
if (Node->isMachineOpcode()) {
unsigned Opc = Node->getMachineOpcode();
@ -891,7 +891,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone,
break;
case ISD::CopyToReg: {
unsigned SrcReg;
SDOperand SrcVal = Node->getOperand(2);
SDValue SrcVal = Node->getOperand(2);
if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
SrcReg = R->getReg();
else
@ -1099,7 +1099,7 @@ MachineBasicBlock *ScheduleDAG::EmitSchedule() {
}
// Finally, emit the code for all of the scheduled instructions.
DenseMap<SDOperand, unsigned> VRBaseMap;
DenseMap<SDValue, unsigned> VRBaseMap;
DenseMap<SUnit*, unsigned> CopyVRBaseMap;
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
SUnit *SU = Sequence[i];

8
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
View File

@ -651,7 +651,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
TryUnfold = true;
}
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
const SDOperand &Op = N->getOperand(i);
const SDValue &Op = N->getOperand(i);
MVT VT = Op.Val->getValueType(Op.ResNo);
if (VT == MVT::Flag)
return NULL;
@ -670,9 +670,9 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
unsigned NumVals = N->getNumValues();
unsigned OldNumVals = SU->Node->getNumValues();
for (unsigned i = 0; i != NumVals; ++i)
DAG.ReplaceAllUsesOfValueWith(SDOperand(SU->Node, i), SDOperand(N, i));
DAG.ReplaceAllUsesOfValueWith(SDOperand(SU->Node, OldNumVals-1),
SDOperand(LoadNode, 1));
DAG.ReplaceAllUsesOfValueWith(SDValue(SU->Node, i), SDValue(N, i));
DAG.ReplaceAllUsesOfValueWith(SDValue(SU->Node, OldNumVals-1),
SDValue(LoadNode, 1));
SUnit *NewSU = CreateNewSUnit(N);
assert(N->getNodeId() == -1 && "Node already inserted!");

744
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

File diff suppressed because it is too large Load Diff

494
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

File diff suppressed because it is too large Load Diff

2
lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
View File

@ -80,7 +80,7 @@ namespace llvm {
/// edge, override this method.
template<typename EdgeIter>
static std::string getEdgeAttributes(const void *Node, EdgeIter EI) {
SDOperand Op = EI.getNode()->getOperand(EI.getOperand());
SDValue Op = EI.getNode()->getOperand(EI.getOperand());
MVT VT = Op.getValueType();
if (VT == MVT::Flag)
return "color=red,style=bold";

108
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -516,7 +516,7 @@ const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
}
MVT TargetLowering::getSetCCResultType(const SDOperand &) const {
MVT TargetLowering::getSetCCResultType(const SDValue &) const {
return getValueType(TD->getIntPtrType());
}
@ -582,8 +582,8 @@ unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
return TD->getCallFrameTypeAlignment(Ty);
}
SDOperand TargetLowering::getPICJumpTableRelocBase(SDOperand Table,
SelectionDAG &DAG) const {
SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
SelectionDAG &DAG) const {
if (usesGlobalOffsetTable())
return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
return Table;
@ -597,7 +597,7 @@ SDOperand TargetLowering::getPICJumpTableRelocBase(SDOperand Table,
/// specified instruction is a constant integer. If so, check to see if there
/// are any bits set in the constant that are not demanded. If so, shrink the
/// constant and return true.
bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op,
bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
const APInt &Demanded) {
// FIXME: ISD::SELECT, ISD::SELECT_CC
switch(Op.getOpcode()) {
@ -608,7 +608,7 @@ bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op,
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
if (C->getAPIntValue().intersects(~Demanded)) {
MVT VT = Op.getValueType();
SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
SDValue New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
DAG.getConstant(Demanded &
C->getAPIntValue(),
VT));
@ -626,7 +626,7 @@ bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op,
/// analyze the expression and return a mask of KnownOne and KnownZero bits for
/// the expression (used to simplify the caller). The KnownZero/One bits may
/// only be accurate for those bits in the DemandedMask.
bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
bool TargetLowering::SimplifyDemandedBits(SDValue Op,
const APInt &DemandedMask,
APInt &KnownZero,
APInt &KnownOne,
@ -780,7 +780,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
if ((KnownOne & KnownOne2) == KnownOne) {
MVT VT = Op.getValueType();
SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0),
ANDC));
}
@ -795,7 +795,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
if (Expanded.isAllOnesValue()) {
if (Expanded != C->getAPIntValue()) {
MVT VT = Op.getValueType();
SDOperand New = TLO.DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
SDValue New = TLO.DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
TLO.DAG.getConstant(Expanded, VT));
return TLO.CombineTo(Op, New);
}
@ -848,7 +848,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
case ISD::SHL:
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
unsigned ShAmt = SA->getValue();
SDOperand InOp = Op.getOperand(0);
SDValue InOp = Op.getOperand(0);
// If the shift count is an invalid immediate, don't do anything.
if (ShAmt >= BitWidth)
@ -868,7 +868,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
Opc = ISD::SRL;
}
SDOperand NewSA =
SDValue NewSA =
TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
MVT VT = Op.getValueType();
return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
@ -890,7 +890,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
MVT VT = Op.getValueType();
unsigned ShAmt = SA->getValue();
unsigned VTSize = VT.getSizeInBits();
SDOperand InOp = Op.getOperand(0);
SDValue InOp = Op.getOperand(0);
// If the shift count is an invalid immediate, don't do anything.
if (ShAmt >= BitWidth)
@ -910,7 +910,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
Opc = ISD::SHL;
}
SDOperand NewSA =
SDValue NewSA =
TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
InOp.getOperand(0), NewSA));
@ -1099,7 +1099,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
// If the input is only used by this truncate, see if we can shrink it based
// on the known demanded bits.
if (Op.getOperand(0).Val->hasOneUse()) {
SDOperand In = Op.getOperand(0);
SDValue In = Op.getOperand(0);
unsigned InBitWidth = In.getValueSizeInBits();
switch (In.getOpcode()) {
default: break;
@ -1115,7 +1115,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
if (ShAmt->getValue() < BitWidth && !(HighBits & NewMask)) {
// None of the shifted in bits are needed. Add a truncate of the
// shift input, then shift it.
SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE,
SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE,
Op.getValueType(),
In.getOperand(0));
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(),
@ -1152,10 +1152,10 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
// Make a FGETSIGN + SHL to move the sign bit into the appropriate
// place. We expect the SHL to be eliminated by other optimizations.
SDOperand Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
Op.getOperand(0));
unsigned ShVal = Op.getValueType().getSizeInBits()-1;
SDOperand ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
Sign, ShAmt));
}
@ -1179,7 +1179,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
/// computeMaskedBitsForTargetNode - Determine which of the bits specified
/// in Mask are known to be either zero or one and return them in the
/// KnownZero/KnownOne bitsets.
void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
APInt &KnownZero,
APInt &KnownOne,
@ -1197,7 +1197,7 @@ void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
/// ComputeNumSignBitsForTargetNode - This method can be implemented by
/// targets that want to expose additional information about sign bits to the
/// DAG Combiner.
unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op,
unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
unsigned Depth) const {
assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
@ -1210,9 +1210,9 @@ unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op,
/// SimplifySetCC - Try to simplify a setcc built with the specified operands
/// and cc. If it is unable to simplify it, return a null SDOperand.
SDOperand
TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1,
/// and cc. If it is unable to simplify it, return a null SDValue.
SDValue
TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
ISD::CondCode Cond, bool foldBooleans,
DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
@ -1249,7 +1249,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1,
// (srl (ctlz x), 5) == 1 -> X == 0
Cond = ISD::SETEQ;
}
SDOperand Zero = DAG.getConstant(0, N0.getValueType());
SDValue Zero = DAG.getConstant(0, N0.getValueType());
return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
Zero, Cond);
}
@ -1313,7 +1313,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1,
if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
return DAG.getConstant(Cond == ISD::SETNE, VT);
SDOperand ZextOp;
SDValue ZextOp;
MVT Op0Ty = N0.getOperand(0).getValueType();
if (Op0Ty == ExtSrcTy) {
ZextOp = N0.getOperand(0);
@ -1360,7 +1360,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1,
APInt::getHighBitsSet(BitWidth,
BitWidth-1))) {
// Okay, get the un-inverted input value.
SDOperand Val;
SDValue Val;
if (N0.getOpcode() == ISD::XOR)
Val = N0.getOperand(0);
else {
@ -1467,7 +1467,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1,
if (isa<ConstantFPSDNode>(N0.Val)) {
// Constant fold or commute setcc.
SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond);
SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond);
if (O.Val) return O;
} else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.Val)) {
// If the RHS of an FP comparison is a constant, simplify it away in
@ -1574,7 +1574,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1,
else if (N0.Val->hasOneUse()) {
assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
// (Z-X) == X --> Z == X<<1
SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(),
N1,
DAG.getConstant(1, getShiftAmountTy()));
if (!DCI.isCalledByLegalizer())
@ -1597,7 +1597,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1,
} else if (N1.Val->hasOneUse()) {
assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
// X == (Z-X) --> X<<1 == Z
SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
DAG.getConstant(1, getShiftAmountTy()));
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(SH.Val);
@ -1608,7 +1608,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1,
}
// Fold away ALL boolean setcc's.
SDOperand Temp;
SDValue Temp;
if (N0.getValueType() == MVT::i1 && foldBooleans) {
switch (Cond) {
default: assert(0 && "Unknown integer setcc!");
@ -1658,7 +1658,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1,
}
// Could not fold it.
return SDOperand();
return SDValue();
}
/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
@ -1673,8 +1673,8 @@ bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA,
}
if (N->getOpcode() == ISD::ADD) {
SDOperand N1 = N->getOperand(0);
SDOperand N2 = N->getOperand(1);
SDValue N1 = N->getOperand(0);
SDValue N2 = N->getOperand(1);
if (isGAPlusOffset(N1.Val, GA, Offset)) {
ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
if (V) {
@ -1705,8 +1705,8 @@ bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base,
if (VT.getSizeInBits() / 8 != Bytes)
return false;
SDOperand Loc = LD->getOperand(1);
SDOperand BaseLoc = Base->getOperand(1);
SDValue Loc = LD->getOperand(1);
SDValue BaseLoc = Base->getOperand(1);
if (Loc.getOpcode() == ISD::FrameIndex) {
if (BaseLoc.getOpcode() != ISD::FrameIndex)
return false;
@ -1730,10 +1730,10 @@ bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base,
}
SDOperand TargetLowering::
SDValue TargetLowering::
PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
// Default implementation: no optimization.
return SDOperand();
return SDValue();
}
//===----------------------------------------------------------------------===//
@ -1787,9 +1787,9 @@ const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops.
void TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
char ConstraintLetter,
std::vector<SDOperand> &Ops,
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const {
switch (ConstraintLetter) {
default: break;
@ -1931,7 +1931,7 @@ static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
///
static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
const TargetLowering &TLI,
SDOperand Op, SelectionDAG *DAG) {
SDValue Op, SelectionDAG *DAG) {
assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
unsigned BestIdx = 0;
TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
@ -1949,7 +1949,7 @@ static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
if (CType == TargetLowering::C_Other && Op.Val) {
assert(OpInfo.Codes[i].size() == 1 &&
"Unhandled multi-letter 'other' constraint");
std::vector<SDOperand> ResultOps;
std::vector<SDValue> ResultOps;
TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0],
ResultOps, *DAG);
if (!ResultOps.empty()) {
@ -1976,7 +1976,7 @@ static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
/// type to use for the specific AsmOperandInfo, setting
/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
SDOperand Op,
SDValue Op,
SelectionDAG *DAG) const {
assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
@ -2221,28 +2221,28 @@ static mu magicu64(uint64_t d)
/// return a DAG expression to select that will generate the same value by
/// multiplying by a magic number. See:
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
std::vector<SDNode*>* Created) const {
SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
std::vector<SDNode*>* Created) const {
MVT VT = N->getValueType(0);
// Check to see if we can do this.
if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
return SDOperand(); // BuildSDIV only operates on i32 or i64
return SDValue(); // BuildSDIV only operates on i32 or i64
int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
// Multiply the numerator (operand 0) by the magic value
SDOperand Q;
SDValue Q;
if (isOperationLegal(ISD::MULHS, VT))
Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
DAG.getConstant(magics.m, VT));
else if (isOperationLegal(ISD::SMUL_LOHI, VT))
Q = SDOperand(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT),
Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT),
N->getOperand(0),
DAG.getConstant(magics.m, VT)).Val, 1);
else
return SDOperand(); // No mulhs or equvialent
return SDValue(); // No mulhs or equvialent
// If d > 0 and m < 0, add the numerator
if (d > 0 && magics.m < 0) {
Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
@ -2263,7 +2263,7 @@ SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
Created->push_back(Q.Val);
}
// Extract the sign bit and add it to the quotient
SDOperand T =
SDValue T =
DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
getShiftAmountTy()));
if (Created)
@ -2275,28 +2275,28 @@ SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
/// return a DAG expression to select that will generate the same value by
/// multiplying by a magic number. See:
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
std::vector<SDNode*>* Created) const {
SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
std::vector<SDNode*>* Created) const {
MVT VT = N->getValueType(0);
// Check to see if we can do this.
if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
return SDOperand(); // BuildUDIV only operates on i32 or i64
return SDValue(); // BuildUDIV only operates on i32 or i64
uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
// Multiply the numerator (operand 0) by the magic value
SDOperand Q;
SDValue Q;
if (isOperationLegal(ISD::MULHU, VT))
Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
DAG.getConstant(magics.m, VT));
else if (isOperationLegal(ISD::UMUL_LOHI, VT))
Q = SDOperand(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT),
Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT),
N->getOperand(0),
DAG.getConstant(magics.m, VT)).Val, 1);
else
return SDOperand(); // No mulhu or equvialent
return SDValue(); // No mulhu or equvialent
if (Created)
Created->push_back(Q.Val);
@ -2304,7 +2304,7 @@ SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
return DAG.getNode(ISD::SRL, VT, Q,
DAG.getConstant(magics.s, getShiftAmountTy()));
} else {
SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
SDValue NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
if (Created)
Created->push_back(NPQ.Val);
NPQ = DAG.getNode(ISD::SRL, VT, NPQ,

2
lib/Target/ARM/ARMAddressingModes.h
View File

@ -46,7 +46,7 @@ namespace ARM_AM {
}
}
static inline ShiftOpc getShiftOpcForNode(SDOperand N) {
static inline ShiftOpc getShiftOpcForNode(SDValue N) {
switch (N.getOpcode()) {
default: return ARM_AM::no_shift;
case ISD::SHL: return ARM_AM::lsl;

236
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -53,38 +53,38 @@ public:
return "ARM Instruction Selection";
}
SDNode *Select(SDOperand Op);
SDNode *Select(SDValue Op);
virtual void InstructionSelect(SelectionDAG &DAG);
bool SelectAddrMode2(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Offset, SDOperand &Opc);
bool SelectAddrMode2Offset(SDOperand Op, SDOperand N,
SDOperand &Offset, SDOperand &Opc);
bool SelectAddrMode3(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Offset, SDOperand &Opc);
bool SelectAddrMode3Offset(SDOperand Op, SDOperand N,
SDOperand &Offset, SDOperand &Opc);
bool SelectAddrMode5(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Offset);
bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
SDValue &Offset, SDValue &Opc);
bool SelectAddrMode2Offset(SDValue Op, SDValue N,
SDValue &Offset, SDValue &Opc);
bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
SDValue &Offset, SDValue &Opc);
bool SelectAddrMode3Offset(SDValue Op, SDValue N,
SDValue &Offset, SDValue &Opc);
bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
SDValue &Offset);
bool SelectAddrModePC(SDOperand Op, SDOperand N, SDOperand &Offset,
SDOperand &Label);
bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
SDValue &Label);
bool SelectThumbAddrModeRR(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Offset);
bool SelectThumbAddrModeRI5(SDOperand Op, SDOperand N, unsigned Scale,
SDOperand &Base, SDOperand &OffImm,
SDOperand &Offset);
bool SelectThumbAddrModeS1(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &OffImm, SDOperand &Offset);
bool SelectThumbAddrModeS2(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &OffImm, SDOperand &Offset);
bool SelectThumbAddrModeS4(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &OffImm, SDOperand &Offset);
bool SelectThumbAddrModeSP(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &OffImm);
bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
SDValue &Offset);
bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
SDValue &Base, SDValue &OffImm,
SDValue &Offset);
bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
SDValue &OffImm, SDValue &Offset);
bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
SDValue &OffImm, SDValue &Offset);
bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
SDValue &OffImm, SDValue &Offset);
bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
SDValue &OffImm);
bool SelectShifterOperandReg(SDOperand Op, SDOperand N, SDOperand &A,
SDOperand &B, SDOperand &C);
bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
SDValue &B, SDValue &C);
// Include the pieces autogenerated from the target description.
#include "ARMGenDAGISel.inc"
@ -98,9 +98,9 @@ void ARMDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
DAG.RemoveDeadNodes();
}
bool ARMDAGToDAGISel::SelectAddrMode2(SDOperand Op, SDOperand N,
SDOperand &Base, SDOperand &Offset,
SDOperand &Opc) {
bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
SDValue &Base, SDValue &Offset,
SDValue &Opc) {
if (N.getOpcode() == ISD::MUL) {
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
// X * [3,5,9] -> X + X * [2,4,8] etc.
@ -206,8 +206,8 @@ bool ARMDAGToDAGISel::SelectAddrMode2(SDOperand Op, SDOperand N,
return true;
}
bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDOperand Op, SDOperand N,
SDOperand &Offset, SDOperand &Opc) {
bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
SDValue &Offset, SDValue &Opc) {
unsigned Opcode = Op.getOpcode();
ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
? cast<LoadSDNode>(Op)->getAddressingMode()
@ -245,9 +245,9 @@ bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDOperand Op, SDOperand N,
}
bool ARMDAGToDAGISel::SelectAddrMode3(SDOperand Op, SDOperand N,
SDOperand &Base, SDOperand &Offset,
SDOperand &Opc) {
bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
SDValue &Base, SDValue &Offset,
SDValue &Opc) {
if (N.getOpcode() == ISD::SUB) {
// X - C is canonicalize to X + -C, no need to handle it here.
Base = N.getOperand(0);
@ -295,8 +295,8 @@ bool ARMDAGToDAGISel::SelectAddrMode3(SDOperand Op, SDOperand N,
return true;
}
bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDOperand Op, SDOperand N,
SDOperand &Offset, SDOperand &Opc) {
bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
SDValue &Offset, SDValue &Opc) {
unsigned Opcode = Op.getOpcode();
ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
? cast<LoadSDNode>(Op)->getAddressingMode()
@ -318,8 +318,8 @@ bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDOperand Op, SDOperand N,
}
bool ARMDAGToDAGISel::SelectAddrMode5(SDOperand Op, SDOperand N,
SDOperand &Base, SDOperand &Offset) {
bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
SDValue &Base, SDValue &Offset) {
if (N.getOpcode() != ISD::ADD) {
Base = N;
if (N.getOpcode() == ISD::FrameIndex) {
@ -364,11 +364,11 @@ bool ARMDAGToDAGISel::SelectAddrMode5(SDOperand Op, SDOperand N,
return true;
}
bool ARMDAGToDAGISel::SelectAddrModePC(SDOperand Op, SDOperand N,
SDOperand &Offset, SDOperand &Label) {
bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
SDValue &Offset, SDValue &Label) {
if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
Offset = N.getOperand(0);
SDOperand N1 = N.getOperand(1);
SDValue N1 = N.getOperand(1);
Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getValue(),
MVT::i32);
return true;
@ -376,14 +376,14 @@ bool ARMDAGToDAGISel::SelectAddrModePC(SDOperand Op, SDOperand N,
return false;
}
bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDOperand Op, SDOperand N,
SDOperand &Base, SDOperand &Offset){
bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
SDValue &Base, SDValue &Offset){
if (N.getOpcode() != ISD::ADD) {
Base = N;
// We must materialize a zero in a reg! Returning an constant here won't
// work since its node is -1 so it won't get added to the selection queue.
// Explicitly issue a tMOVri8 node!
Offset = SDOperand(CurDAG->getTargetNode(ARM::tMOVi8, MVT::i32,
Offset = SDValue(CurDAG->getTargetNode(ARM::tMOVi8, MVT::i32,
CurDAG->getTargetConstant(0, MVT::i32)), 0);
return true;
}
@ -394,11 +394,11 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDOperand Op, SDOperand N,
}
bool
ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDOperand Op, SDOperand N,
unsigned Scale, SDOperand &Base,
SDOperand &OffImm, SDOperand &Offset) {
ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
unsigned Scale, SDValue &Base,
SDValue &OffImm, SDValue &Offset) {
if (Scale == 4) {
SDOperand TmpBase, TmpOffImm;
SDValue TmpBase, TmpOffImm;
if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
return false; // We want to select tLDRspi / tSTRspi instead.
if (N.getOpcode() == ARMISD::Wrapper &&
@ -444,26 +444,26 @@ ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDOperand Op, SDOperand N,
return true;
}
bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDOperand Op, SDOperand N,
SDOperand &Base, SDOperand &OffImm,
SDOperand &Offset) {
bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
SDValue &Base, SDValue &OffImm,
SDValue &Offset) {
return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
}
bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDOperand Op, SDOperand N,
SDOperand &Base, SDOperand &OffImm,
SDOperand &Offset) {
bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
SDValue &Base, SDValue &OffImm,
SDValue &Offset) {
return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
}
bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDOperand Op, SDOperand N,
SDOperand &Base, SDOperand &OffImm,
SDOperand &Offset) {
bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
SDValue &Base, SDValue &OffImm,
SDValue &Offset) {
return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
}
bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDOperand Op, SDOperand N,
SDOperand &Base, SDOperand &OffImm) {
bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
SDValue &Base, SDValue &OffImm) {
if (N.getOpcode() == ISD::FrameIndex) {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
@ -498,11 +498,11 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDOperand Op, SDOperand N,
return false;
}
bool ARMDAGToDAGISel::SelectShifterOperandReg(SDOperand Op,
SDOperand N,
SDOperand &BaseReg,
SDOperand &ShReg,
SDOperand &Opc) {
bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
SDValue N,
SDValue &BaseReg,
SDValue &ShReg,
SDValue &Opc) {
ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
// Don't match base register only case. That is matched to a separate
@ -523,12 +523,12 @@ bool ARMDAGToDAGISel::SelectShifterOperandReg(SDOperand Op,
}
/// getAL - Returns a ARMCC::AL immediate node.
static inline SDOperand getAL(SelectionDAG *CurDAG) {
static inline SDValue getAL(SelectionDAG *CurDAG) {
return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
}
SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.Val;
if (N->isMachineOpcode())
@ -548,7 +548,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
ARM_AM::getSOImmVal(~Val) == -1 && // MVN
!ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
if (UseCP) {
SDOperand CPIdx =
SDValue CPIdx =
CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
TLI.getPointerTy());
@ -557,7 +557,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
ResNode = CurDAG->getTargetNode(ARM::tLDRcp, MVT::i32, MVT::Other,
CPIdx, CurDAG->getEntryNode());
else {
SDOperand Ops[] = {
SDValue Ops[] = {
CPIdx,
CurDAG->getRegister(0, MVT::i32),
CurDAG->getTargetConstant(0, MVT::i32),
@ -567,7 +567,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
};
ResNode=CurDAG->getTargetNode(ARM::LDRcp, MVT::i32, MVT::Other, Ops, 6);
}
ReplaceUses(Op, SDOperand(ResNode, 0));
ReplaceUses(Op, SDValue(ResNode, 0));
return NULL;
}
@ -577,12 +577,12 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
case ISD::FrameIndex: {
// Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
int FI = cast<FrameIndexSDNode>(N)->getIndex();
SDOperand TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
if (Subtarget->isThumb())
return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
CurDAG->getTargetConstant(0, MVT::i32));
else {
SDOperand Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) };
return CurDAG->SelectNodeTo(N, ARM::ADDri, MVT::i32, Ops, 5);
@ -590,8 +590,8 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
}
case ISD::ADD: {
// Select add sp, c to tADDhirr.
SDOperand N0 = Op.getOperand(0);
SDOperand N1 = Op.getOperand(1);
SDValue N0 = Op.getOperand(0);
SDValue N1 = Op.getOperand(1);
RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(Op.getOperand(0));
RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(Op.getOperand(1));
if (LHSR && LHSR->getReg() == ARM::SP) {
@ -612,20 +612,20 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
unsigned RHSV = C->getValue();
if (!RHSV) break;
if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
SDOperand V = Op.getOperand(0);
SDValue V = Op.getOperand(0);
AddToISelQueue(V);
unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1));
SDOperand Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
CurDAG->getTargetConstant(ShImm, MVT::i32),
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) };
return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
}
if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
SDOperand V = Op.getOperand(0);
SDValue V = Op.getOperand(0);
AddToISelQueue(V);
unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV+1));
SDOperand Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
CurDAG->getTargetConstant(ShImm, MVT::i32),
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) };
@ -641,7 +641,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
case ISD::UMUL_LOHI: {
AddToISelQueue(Op.getOperand(0));
AddToISelQueue(Op.getOperand(1));
SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1),
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) };
return CurDAG->getTargetNode(ARM::UMULL, MVT::i32, MVT::i32, Ops, 5);
@ -649,7 +649,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
case ISD::SMUL_LOHI: {
AddToISelQueue(Op.getOperand(0));
AddToISelQueue(Op.getOperand(1));
SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1),
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) };
return CurDAG->getTargetNode(ARM::SMULL, MVT::i32, MVT::i32, Ops, 5);
@ -659,7 +659,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
ISD::MemIndexedMode AM = LD->getAddressingMode();
MVT LoadedVT = LD->getMemoryVT();
if (AM != ISD::UNINDEXED) {
SDOperand Offset, AMOpc;
SDValue Offset, AMOpc;
bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
unsigned Opcode = 0;
bool Match = false;
@ -688,12 +688,12 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
}
if (Match) {
SDOperand Chain = LD->getChain();
SDOperand Base = LD->getBasePtr();
SDValue Chain = LD->getChain();
SDValue Base = LD->getBasePtr();
AddToISelQueue(Chain);
AddToISelQueue(Base);
AddToISelQueue(Offset);
SDOperand Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
CurDAG->getRegister(0, MVT::i32), Chain };
return CurDAG->getTargetNode(Opcode, MVT::i32, MVT::i32,
MVT::Other, Ops, 6);
@ -712,11 +712,11 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
// Pattern complexity = 6 cost = 1 size = 0
unsigned Opc = Subtarget->isThumb() ? ARM::tBcc : ARM::Bcc;
SDOperand Chain = Op.getOperand(0);
SDOperand N1 = Op.getOperand(1);
SDOperand N2 = Op.getOperand(2);
SDOperand N3 = Op.getOperand(3);
SDOperand InFlag = Op.getOperand(4);
SDValue Chain = Op.getOperand(0);
SDValue N1 = Op.getOperand(1);
SDValue N2 = Op.getOperand(2);
SDValue N3 = Op.getOperand(3);
SDValue InFlag = Op.getOperand(4);
assert(N1.getOpcode() == ISD::BasicBlock);
assert(N2.getOpcode() == ISD::Constant);
assert(N3.getOpcode() == ISD::Register);
@ -724,35 +724,35 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
AddToISelQueue(Chain);
AddToISelQueue(N1);
AddToISelQueue(InFlag);
SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
SDOperand Ops[] = { N1, Tmp2, N3, Chain, InFlag };
SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
SDNode *ResNode = CurDAG->getTargetNode(Opc, MVT::Other, MVT::Flag, Ops, 5);
Chain = SDOperand(ResNode, 0);
Chain = SDValue(ResNode, 0);
if (Op.Val->getNumValues() == 2) {
InFlag = SDOperand(ResNode, 1);
ReplaceUses(SDOperand(Op.Val, 1), InFlag);
InFlag = SDValue(ResNode, 1);
ReplaceUses(SDValue(Op.Val, 1), InFlag);
}
ReplaceUses(SDOperand(Op.Val, 0), SDOperand(Chain.Val, Chain.ResNo));
ReplaceUses(SDValue(Op.Val, 0), SDValue(Chain.Val, Chain.ResNo));
return NULL;
}
case ARMISD::CMOV: {
bool isThumb = Subtarget->isThumb();
MVT VT = Op.getValueType();
SDOperand N0 = Op.getOperand(0);
SDOperand N1 = Op.getOperand(1);
SDOperand N2 = Op.getOperand(2);
SDOperand N3 = Op.getOperand(3);
SDOperand InFlag = Op.getOperand(4);
SDValue N0 = Op.getOperand(0);
SDValue N1 = Op.getOperand(1);
SDValue N2 = Op.getOperand(2);
SDValue N3 = Op.getOperand(3);
SDValue InFlag = Op.getOperand(4);
assert(N2.getOpcode() == ISD::Constant);
assert(N3.getOpcode() == ISD::Register);
// Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
// Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
// Pattern complexity = 18 cost = 1 size = 0
SDOperand CPTmp0;
SDOperand CPTmp1;
SDOperand CPTmp2;
SDValue CPTmp0;
SDValue CPTmp1;
SDValue CPTmp2;
if (!isThumb && VT == MVT::i32 &&
SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
AddToISelQueue(N0);
@ -760,9 +760,9 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
AddToISelQueue(CPTmp1);
AddToISelQueue(CPTmp2);
AddToISelQueue(InFlag);
SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
SDOperand Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
return CurDAG->SelectNodeTo(Op.Val, ARM::MOVCCs, MVT::i32, Ops, 7);
}
@ -777,12 +777,12 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
Predicate_so_imm(N3.Val)) {
AddToISelQueue(N0);
AddToISelQueue(InFlag);
SDOperand Tmp1 = CurDAG->getTargetConstant(((unsigned)
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N1)->getValue()), MVT::i32);
Tmp1 = Transform_so_imm_XFORM(Tmp1.Val);
SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
SDOperand Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
return CurDAG->SelectNodeTo(Op.Val, ARM::MOVCCi, MVT::i32, Ops, 5);
}
@ -798,9 +798,9 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
AddToISelQueue(N0);
AddToISelQueue(N1);
AddToISelQueue(InFlag);
SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
SDOperand Ops[] = { N0, N1, Tmp2, N3, InFlag };
SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
unsigned Opc = 0;
switch (VT.getSimpleVT()) {
default: assert(false && "Illegal conditional move type!");
@ -819,20 +819,20 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
}
case ARMISD::CNEG: {
MVT VT = Op.getValueType();
SDOperand N0 = Op.getOperand(0);
SDOperand N1 = Op.getOperand(1);
SDOperand N2 = Op.getOperand(2);
SDOperand N3 = Op.getOperand(3);
SDOperand InFlag = Op.getOperand(4);
SDValue N0 = Op.getOperand(0);
SDValue N1 = Op.getOperand(1);
SDValue N2 = Op.getOperand(2);
SDValue N3 = Op.getOperand(3);
SDValue InFlag = Op.getOperand(4);
assert(N2.getOpcode() == ISD::Constant);
assert(N3.getOpcode() == ISD::Register);
AddToISelQueue(N0);
AddToISelQueue(N1);
AddToISelQueue(InFlag);
SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
SDOperand Ops[] = { N0, N1, Tmp2, N3, InFlag };
SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
unsigned Opc = 0;
switch (VT.getSimpleVT()) {
default: assert(false && "Illegal conditional move type!");

320
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -399,13 +399,13 @@ HowToPassArgument(MVT ObjectVT, unsigned NumGPRs,
/// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
/// nodes.
SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
MVT RetVT= Op.Val->getValueType(0);
SDOperand Chain = Op.getOperand(0);
SDValue Chain = Op.getOperand(0);
unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
assert((CallConv == CallingConv::C ||
CallConv == CallingConv::Fast) && "unknown calling convention");
SDOperand Callee = Op.getOperand(4);
SDValue Callee = Op.getOperand(4);
unsigned NumOps = (Op.getNumOperands() - 5) / 2;
unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
unsigned NumGPRs = 0; // GPRs used for parameter passing.
@ -433,17 +433,17 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
Chain = DAG.getCALLSEQ_START(Chain,
DAG.getConstant(NumBytes, MVT::i32));
SDOperand StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
static const unsigned GPRArgRegs[] = {
ARM::R0, ARM::R1, ARM::R2, ARM::R3
};
NumGPRs = 0;
std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
std::vector<SDOperand> MemOpChains;
std::vector<std::pair<unsigned, SDValue> > RegsToPass;
std::vector<SDValue> MemOpChains;
for (unsigned i = 0; i != NumOps; ++i) {
SDOperand Arg = Op.getOperand(5+2*i);
SDValue Arg = Op.getOperand(5+2*i);
ISD::ArgFlagsTy Flags =
cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags();
MVT ArgVT = Arg.getValueType();
@ -467,22 +467,22 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg)));
break;
case MVT::i64: {
SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
DAG.getConstant(0, getPointerTy()));
SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
DAG.getConstant(1, getPointerTy()));
RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo));
if (ObjGPRs == 2)
RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi));
else {
SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0));
}
break;
}
case MVT::f64: {
SDOperand Cvt = DAG.getNode(ARMISD::FMRRD,
SDValue Cvt = DAG.getNode(ARMISD::FMRRD,
DAG.getVTList(MVT::i32, MVT::i32),
&Arg, 1);
RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt));
@ -490,7 +490,7 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1],
Cvt.getValue(1)));
else {
SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff,
NULL, 0));
@ -500,7 +500,7 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
}
} else {
assert(ObjSize != 0);
SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
}
@ -515,7 +515,7 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
// Build a sequence of copy-to-reg nodes chained together with token chain
// and flag operands which copy the outgoing args into the appropriate regs.
SDOperand InFlag;
SDValue InFlag;
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
InFlag);
@ -542,10 +542,10 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
ARMCP::CPStub, 4);
SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
} else
Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
@ -559,10 +559,10 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
ARMCP::CPStub, 4);
SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
} else
Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
@ -587,7 +587,7 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
InFlag = Chain.getValue(1);
}
std::vector<SDOperand> Ops;
std::vector<SDValue> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
@ -611,7 +611,7 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
if (RetVT != MVT::Other)
InFlag = Chain.getValue(1);
std::vector<SDOperand> ResultVals;
std::vector<SDValue> ResultVals;
// If the call has results, copy the values out of the ret val registers.
switch (RetVT.getSimpleVT()) {
@ -634,8 +634,8 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
Chain.getValue(0)));
break;
case MVT::f64: {
SDOperand Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag);
SDOperand Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2));
SDValue Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag);
SDValue Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2));
ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi));
break;
}
@ -645,19 +645,19 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
return Chain;
ResultVals.push_back(Chain);
SDOperand Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size());
SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size());
return Res.getValue(Op.ResNo);
}
static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
SDOperand Copy;
SDOperand Chain = Op.getOperand(0);
static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
SDValue Copy;
SDValue Chain = Op.getOperand(0);
switch(Op.getNumOperands()) {
default:
assert(0 && "Do not know how to return this many arguments!");
abort();
case 1: {
SDOperand LR = DAG.getRegister(ARM::LR, MVT::i32);
SDValue LR = DAG.getRegister(ARM::LR, MVT::i32);
return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain);
}
case 3:
@ -668,16 +668,16 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
// Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
// available.
Op = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Op,1);
SDOperand Sign = DAG.getConstant(0, MVT::i32);
SDValue Sign = DAG.getConstant(0, MVT::i32);
return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign,
Op.getValue(1), Sign);
}
Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand());
Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDValue());
if (DAG.getMachineFunction().getRegInfo().liveout_empty())
DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
break;
case 5:
Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand());
Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDValue());
Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
// If we haven't noted the R0+R1 are live out, do so now.
if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
@ -686,7 +686,7 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
}
break;
case 9: // i128 -> 4 regs
Copy = DAG.getCopyToReg(Chain, ARM::R3, Op.getOperand(7), SDOperand());
Copy = DAG.getCopyToReg(Chain, ARM::R3, Op.getOperand(7), SDValue());
Copy = DAG.getCopyToReg(Copy , ARM::R2, Op.getOperand(5), Copy.getValue(1));
Copy = DAG.getCopyToReg(Copy , ARM::R1, Op.getOperand(3), Copy.getValue(1));
Copy = DAG.getCopyToReg(Copy , ARM::R0, Op.getOperand(1), Copy.getValue(1));
@ -711,10 +711,10 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
// be used to form addressing mode. These wrapped nodes will be selected
// into MOVi.
static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
MVT PtrVT = Op.getValueType();
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
SDOperand Res;
SDValue Res;
if (CP->isMachineConstantPoolEntry())
Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
CP->getAlignment());
@ -725,7 +725,7 @@ static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
}
// Lower ISD::GlobalTLSAddress using the "general dynamic" model
SDOperand
SDValue
ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
SelectionDAG &DAG) {
MVT PtrVT = getPointerTy();
@ -733,12 +733,12 @@ ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
ARMConstantPoolValue *CPV =
new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
PCAdj, "tlsgd", true);
SDOperand Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2);
SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2);
Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument);
Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0);
SDOperand Chain = Argument.getValue(1);
SDValue Chain = Argument.getValue(1);
SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel);
// call __tls_get_addr.
@ -747,7 +747,7 @@ ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
Entry.Node = Argument;
Entry.Ty = (const Type *) Type::Int32Ty;
Args.push_back(Entry);
std::pair<SDOperand, SDOperand> CallResult =
std::pair<SDValue, SDValue> CallResult =
LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false,
CallingConv::C, false,
DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG);
@ -756,15 +756,15 @@ ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
// Lower ISD::GlobalTLSAddress using the "initial exec" or
// "local exec" model.
SDOperand
SDValue
ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
SelectionDAG &DAG) {
GlobalValue *GV = GA->getGlobal();
SDOperand Offset;
SDOperand Chain = DAG.getEntryNode();
SDValue Offset;
SDValue Chain = DAG.getEntryNode();
MVT PtrVT = getPointerTy();
// Get the Thread Pointer
SDOperand ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
if (GV->isDeclaration()){
// initial exec model
@ -777,7 +777,7 @@ ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
Chain = Offset.getValue(1);
SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel);
Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
@ -795,8 +795,8 @@ ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
}
SDOperand
ARMTargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
SDValue
ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
// TODO: implement the "local dynamic" model
assert(Subtarget->isTargetELF() &&
"TLS not implemented for non-ELF targets");
@ -809,7 +809,7 @@ ARMTargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
return LowerToTLSExecModels(GA, DAG);
}
SDOperand ARMTargetLowering::LowerGlobalAddressELF(SDOperand Op,
SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
SelectionDAG &DAG) {
MVT PtrVT = getPointerTy();
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
@ -818,17 +818,17 @@ SDOperand ARMTargetLowering::LowerGlobalAddressELF(SDOperand Op,
bool UseGOTOFF = GV->hasInternalLinkage() || GV->hasHiddenVisibility();
ARMConstantPoolValue *CPV =
new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
SDOperand Chain = Result.getValue(1);
SDOperand GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT);
SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
SDValue Chain = Result.getValue(1);
SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT);
Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT);
if (!UseGOTOFF)
Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
return Result;
} else {
SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
}
@ -842,13 +842,13 @@ static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
(GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode()));
}
SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op,
SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
SelectionDAG &DAG) {
MVT PtrVT = getPointerTy();
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Reloc::Model RelocM = getTargetMachine().getRelocationModel();
bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
SDOperand CPAddr;
SDValue CPAddr;
if (RelocM == Reloc::Static)
CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
else {
@ -862,11 +862,11 @@ SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op,
}
CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
SDOperand Chain = Result.getValue(1);
SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
SDValue Chain = Result.getValue(1);
if (RelocM == Reloc::PIC_) {
SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
}
if (IsIndirect)
@ -875,7 +875,7 @@ SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op,
return Result;
}
SDOperand ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDOperand Op,
SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
SelectionDAG &DAG){
assert(Subtarget->isTargetELF() &&
"GLOBAL OFFSET TABLE not implemented for non-ELF targets");
@ -884,40 +884,40 @@ SDOperand ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDOperand Op,
ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
ARMPCLabelIndex,
ARMCP::CPValue, PCAdj);
SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
}
static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
switch (IntNo) {
default: return SDOperand(); // Don't custom lower most intrinsics.
default: return SDValue(); // Don't custom lower most intrinsics.
case Intrinsic::arm_thread_pointer:
return DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
}
}
static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
unsigned VarArgsFrameIndex) {
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
}
static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
static SDValue LowerFORMAL_ARGUMENT(SDValue Op, SelectionDAG &DAG,
unsigned ArgNo, unsigned &NumGPRs,
unsigned &ArgOffset) {
MachineFunction &MF = DAG.getMachineFunction();
MVT ObjectVT = Op.getValue(ArgNo).getValueType();
SDOperand Root = Op.getOperand(0);
std::vector<SDOperand> ArgValues;
SDValue Root = Op.getOperand(0);
std::vector<SDValue> ArgValues;
MachineRegisterInfo &RegInfo = MF.getRegInfo();
static const unsigned GPRArgRegs[] = {
@ -935,7 +935,7 @@ static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
NumGPRs += GPRPad;
ArgOffset += StackPad;
SDOperand ArgValue;
SDValue ArgValue;
if (ObjGPRs == 1) {
unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
@ -949,7 +949,7 @@ static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
SDValue ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
@ -959,11 +959,11 @@ static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
if (ObjSize) {
MachineFrameInfo *MFI = MF.getFrameInfo();
int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
if (ObjGPRs == 0)
ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
else {
SDOperand ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0);
SDValue ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0);
assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
}
@ -974,10 +974,10 @@ static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
return ArgValue;
}
SDOperand
ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
std::vector<SDOperand> ArgValues;
SDOperand Root = Op.getOperand(0);
SDValue
ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
std::vector<SDValue> ArgValues;
SDValue Root = Op.getOperand(0);
unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
unsigned NumGPRs = 0; // GPRs used for parameter passing.
@ -1006,14 +1006,14 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
AFI->setVarArgsRegSaveSize(VARegSaveSize);
VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
VARegSaveSize - VARegSize);
SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
SmallVector<SDOperand, 4> MemOps;
SmallVector<SDValue, 4> MemOps;
for (; NumGPRs < 4; ++NumGPRs) {
unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
MemOps.push_back(Store);
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
DAG.getConstant(4, getPointerTy()));
@ -1034,13 +1034,13 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
}
/// isFloatingPointZero - Return true if this is +0.0.
static bool isFloatingPointZero(SDOperand Op) {
static bool isFloatingPointZero(SDValue Op) {
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
return CFP->getValueAPF().isPosZero();
else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
// Maybe this has already been legalized into the constant pool?
if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
SDOperand WrapperOp = Op.getOperand(1).getOperand(0);
SDValue WrapperOp = Op.getOperand(1).getOperand(0);
if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
return CFP->getValueAPF().isPosZero();
@ -1056,8 +1056,8 @@ static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
/// the given operands.
static SDOperand getARMCmp(SDOperand LHS, SDOperand RHS, ISD::CondCode CC,
SDOperand &ARMCC, SelectionDAG &DAG, bool isThumb) {
static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
SDValue &ARMCC, SelectionDAG &DAG, bool isThumb) {
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) {
unsigned C = RHSC->getValue();
if (!isLegalCmpImmediate(C, isThumb)) {
@ -1115,8 +1115,8 @@ static SDOperand getARMCmp(SDOperand LHS, SDOperand RHS, ISD::CondCode CC,
}
/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
static SDOperand getVFPCmp(SDOperand LHS, SDOperand RHS, SelectionDAG &DAG) {
SDOperand Cmp;
static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG) {
SDValue Cmp;
if (!isFloatingPointZero(RHS))
Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS);
else
@ -1124,19 +1124,19 @@ static SDOperand getVFPCmp(SDOperand LHS, SDOperand RHS, SelectionDAG &DAG) {
return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp);
}
static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG,
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *ST) {
MVT VT = Op.getValueType();
SDOperand LHS = Op.getOperand(0);
SDOperand RHS = Op.getOperand(1);
SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
SDOperand TrueVal = Op.getOperand(2);
SDOperand FalseVal = Op.getOperand(3);
SDValue TrueVal = Op.getOperand(2);
SDValue FalseVal = Op.getOperand(3);
if (LHS.getValueType() == MVT::i32) {
SDOperand ARMCC;
SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
SDValue ARMCC;
SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp);
}
@ -1144,32 +1144,32 @@ static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG,
if (FPCCToARMCC(CC, CondCode, CondCode2))
std::swap(TrueVal, FalseVal);
SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
SDOperand Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal,
SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
SDValue Cmp = getVFPCmp(LHS, RHS, DAG);
SDValue Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal,
ARMCC, CCR, Cmp);
if (CondCode2 != ARMCC::AL) {
SDOperand ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
// FIXME: Needs another CMP because flag can have but one use.
SDOperand Cmp2 = getVFPCmp(LHS, RHS, DAG);
SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG);
Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, CCR, Cmp2);
}
return Result;
}
static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG,
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *ST) {
SDOperand Chain = Op.getOperand(0);
SDValue Chain = Op.getOperand(0);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
SDOperand LHS = Op.getOperand(2);
SDOperand RHS = Op.getOperand(3);
SDOperand Dest = Op.getOperand(4);
SDValue LHS = Op.getOperand(2);
SDValue RHS = Op.getOperand(3);
SDValue Dest = Op.getOperand(4);
if (LHS.getValueType() == MVT::i32) {
SDOperand ARMCC;
SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
SDValue ARMCC;
SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, CCR,Cmp);
}
@ -1179,33 +1179,33 @@ static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG,
// Swap the LHS/RHS of the comparison if needed.
std::swap(LHS, RHS);
SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
SDValue Cmp = getVFPCmp(LHS, RHS, DAG);
SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
SDOperand Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
SDValue Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
if (CondCode2 != ARMCC::AL) {
ARMCC = DAG.getConstant(CondCode2, MVT::i32);
SDOperand Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
}
return Res;
}
SDOperand ARMTargetLowering::LowerBR_JT(SDOperand Op, SelectionDAG &DAG) {
SDOperand Chain = Op.getOperand(0);
SDOperand Table = Op.getOperand(1);
SDOperand Index = Op.getOperand(2);
SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
SDValue Chain = Op.getOperand(0);
SDValue Table = Op.getOperand(1);
SDValue Index = Op.getOperand(2);
MVT PTy = getPointerTy();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
SDOperand UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId);
Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy));
SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy,
Chain, Addr, NULL, 0);
@ -1215,14 +1215,14 @@ SDOperand ARMTargetLowering::LowerBR_JT(SDOperand Op, SelectionDAG &DAG) {
return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId);
}
static SDOperand LowerFP_TO_INT(SDOperand Op, SelectionDAG &DAG) {
static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
unsigned Opc =
Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0));
return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
}
static SDOperand LowerINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
unsigned Opc =
Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
@ -1231,39 +1231,39 @@ static SDOperand LowerINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
return DAG.getNode(Opc, VT, Op);
}
static SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
// Implement fcopysign with a fabs and a conditional fneg.
SDOperand Tmp0 = Op.getOperand(0);
SDOperand Tmp1 = Op.getOperand(1);
SDValue Tmp0 = Op.getOperand(0);
SDValue Tmp1 = Op.getOperand(1);
MVT VT = Op.getValueType();
MVT SrcVT = Tmp1.getValueType();
SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0);
SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG);
SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
SDValue AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0);
SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG);
SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
}
SDOperand
SDValue
ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
SDOperand Chain,
SDOperand Dst, SDOperand Src,
SDOperand Size, unsigned Align,
SDValue Chain,
SDValue Dst, SDValue Src,
SDValue Size, unsigned Align,
bool AlwaysInline,
const Value *DstSV, uint64_t DstSVOff,
const Value *SrcSV, uint64_t SrcSVOff){
// Do repeated 4-byte loads and stores. To be improved.
// This requires 4-byte alignment.
if ((Align & 3) != 0)
return SDOperand();
return SDValue();
// This requires the copy size to be a constant, preferrably
// within a subtarget-specific limit.
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
if (!ConstantSize)
return SDOperand();
return SDValue();
uint64_t SizeVal = ConstantSize->getValue();
if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
return SDOperand();
return SDValue();
unsigned BytesLeft = SizeVal & 3;
unsigned NumMemOps = SizeVal >> 2;
@ -1272,8 +1272,8 @@ ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
unsigned VTSize = 4;
unsigned i = 0;
const unsigned MAX_LOADS_IN_LDM = 6;
SDOperand TFOps[MAX_LOADS_IN_LDM];
SDOperand Loads[MAX_LOADS_IN_LDM];
SDValue TFOps[MAX_LOADS_IN_LDM];
SDValue Loads[MAX_LOADS_IN_LDM];
uint64_t SrcOff = 0, DstOff = 0;
// Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
@ -1357,8 +1357,8 @@ static SDNode *ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
assert(N->getValueType(0) == MVT::i64 &&
N->getOperand(0).getValueType() == MVT::f64);
SDOperand Op = N->getOperand(0);
SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32),
SDValue Op = N->getOperand(0);
SDValue Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32),
&Op, 1);
// Merge the pieces into a single i64 value.
@ -1379,9 +1379,9 @@ static SDNode *ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) {
if (ST->isThumb()) return 0;
// Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
DAG.getConstant(0, MVT::i32));
SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
DAG.getConstant(1, MVT::i32));
// First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
@ -1397,7 +1397,7 @@ static SDNode *ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) {
}
SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
default: assert(0 && "Don't know how to custom lower this!"); abort();
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
@ -1424,11 +1424,11 @@ SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
// FIXME: Remove these when LegalizeDAGTypes lands.
case ISD::BIT_CONVERT: return SDOperand(ExpandBIT_CONVERT(Op.Val, DAG), 0);
case ISD::BIT_CONVERT: return SDValue(ExpandBIT_CONVERT(Op.Val, DAG), 0);
case ISD::SRL:
case ISD::SRA: return SDOperand(ExpandSRx(Op.Val, DAG,Subtarget),0);
case ISD::SRA: return SDValue(ExpandSRx(Op.Val, DAG,Subtarget),0);
}
return SDOperand();
return SDValue();
}
@ -1516,23 +1516,23 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
//===----------------------------------------------------------------------===//
/// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
static SDOperand PerformFMRRDCombine(SDNode *N,
static SDValue PerformFMRRDCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI) {
// fmrrd(fmdrr x, y) -> x,y
SDOperand InDouble = N->getOperand(0);
SDValue InDouble = N->getOperand(0);
if (InDouble.getOpcode() == ARMISD::FMDRR)
return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
return SDOperand();
return SDValue();
}
SDOperand ARMTargetLowering::PerformDAGCombine(SDNode *N,
SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
switch (N->getOpcode()) {
default: break;
case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
}
return SDOperand();
return SDValue();
}
@ -1654,8 +1654,8 @@ bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
static bool getIndexedAddressParts(SDNode *Ptr, MVT VT,
bool isSEXTLoad, SDOperand &Base,
SDOperand &Offset, bool &isInc,
bool isSEXTLoad, SDValue &Base,
SDValue &Offset, bool &isInc,
SelectionDAG &DAG) {
if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
return false;
@ -1713,15 +1713,15 @@ static bool getIndexedAddressParts(SDNode *Ptr, MVT VT,
/// offset pointer and addressing mode by reference if the node's address
/// can be legally represented as pre-indexed load / store address.
bool
ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
SDOperand &Offset,
ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
SDValue &Offset,
ISD::MemIndexedMode &AM,
SelectionDAG &DAG) {
if (Subtarget->isThumb())
return false;
MVT VT;
SDOperand Ptr;
SDValue Ptr;
bool isSEXTLoad = false;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
Ptr = LD->getBasePtr();
@ -1747,15 +1747,15 @@ ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
/// offset pointer and addressing mode by reference if this node can be
/// combined with a load / store to form a post-indexed load / store.
bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
SDOperand &Base,
SDOperand &Offset,
SDValue &Base,
SDValue &Offset,
ISD::MemIndexedMode &AM,
SelectionDAG &DAG) {
if (Subtarget->isThumb())
return false;
MVT VT;
SDOperand Ptr;
SDValue Ptr;
bool isSEXTLoad = false;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
VT = LD->getMemoryVT();
@ -1775,7 +1775,7 @@ bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
return false;
}
void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
APInt &KnownZero,
APInt &KnownOne,

38
lib/Target/ARM/ARMISelLowering.h
View File

@ -75,10 +75,10 @@ namespace llvm {
public:
explicit ARMTargetLowering(TargetMachine &TM);
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
virtual SDNode *ReplaceNodeResults(SDNode *N, SelectionDAG &DAG);
virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
virtual const char *getTargetNodeName(unsigned Opcode) const;
@ -92,8 +92,8 @@ namespace llvm {
/// getPreIndexedAddressParts - returns true by value, base pointer and
/// offset pointer and addressing mode by reference if the node's address
/// can be legally represented as pre-indexed load / store address.
virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
SDOperand &Offset,
virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
SDValue &Offset,
ISD::MemIndexedMode &AM,
SelectionDAG &DAG);
@ -101,11 +101,11 @@ namespace llvm {
/// offset pointer and addressing mode by reference if this node can be
/// combined with a load / store to form a post-indexed load / store.
virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
SDOperand &Base, SDOperand &Offset,
SDValue &Base, SDValue &Offset,
ISD::MemIndexedMode &AM,
SelectionDAG &DAG);
virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
virtual void computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
APInt &KnownZero,
APInt &KnownOne,
@ -132,22 +132,22 @@ namespace llvm {
///
unsigned ARMPCLabelIndex;
SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerGlobalAddressDarwin(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerGlobalAddressELF(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG);
SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG);
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
SelectionDAG &DAG);
SDOperand LowerToTLSExecModels(GlobalAddressSDNode *GA,
SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
SelectionDAG &DAG);
SDOperand LowerGLOBAL_OFFSET_TABLE(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerBR_JT(SDOperand Op, SelectionDAG &DAG);
SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG);
SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG);
SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG);
SDOperand EmitTargetCodeForMemcpy(SelectionDAG &DAG,
SDOperand Chain,
SDOperand Dst, SDOperand Src,
SDOperand Size, unsigned Align,
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG,
SDValue Chain,
SDValue Dst, SDValue Src,
SDValue Size, unsigned Align,
bool AlwaysInline,
const Value *DstSV, uint64_t DstSVOff,
const Value *SrcSV, uint64_t SrcSVOff);

2
lib/Target/ARM/ARMInstrInfo.td
View File

@ -152,7 +152,7 @@ def so_imm_not :
// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
def sext_16_node : PatLeaf<(i32 GPR:$a), [{
return CurDAG->ComputeNumSignBits(SDOperand(N,0)) >= 17;
return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
}]>;

100
lib/Target/Alpha/AlphaISelDAGToDAG.cpp
View File

@ -65,7 +65,7 @@ namespace {
/// that the bits 1-7 of LHS are already zero. If LHS is non-null, we are
/// in checking mode. If LHS is null, we assume that the mask has already
/// been validated before.
uint64_t get_zapImm(SDOperand LHS, uint64_t Constant) {
uint64_t get_zapImm(SDValue LHS, uint64_t Constant) {
uint64_t BitsToCheck = 0;
unsigned Result = 0;
for (unsigned i = 0; i != 8; ++i) {
@ -132,15 +132,15 @@ namespace {
return (x - y) == r;
}
static bool isFPZ(SDOperand N) {
static bool isFPZ(SDValue N) {
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
return (CN && (CN->getValueAPF().isZero()));
}
static bool isFPZn(SDOperand N) {
static bool isFPZn(SDValue N) {
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
return (CN && CN->getValueAPF().isNegZero());
}
static bool isFPZp(SDOperand N) {
static bool isFPZp(SDValue N) {
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
return (CN && CN->getValueAPF().isPosZero());
}
@ -153,13 +153,13 @@ namespace {
/// getI64Imm - Return a target constant with the specified value, of type
/// i64.
inline SDOperand getI64Imm(int64_t Imm) {
inline SDValue getI64Imm(int64_t Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i64);
}
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
SDNode *Select(SDOperand Op);
SDNode *Select(SDValue Op);
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
@ -171,11 +171,11 @@ namespace {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
std::vector<SDOperand> &OutOps,
std::vector<SDValue> &OutOps,
SelectionDAG &DAG) {
SDOperand Op0;
SDValue Op0;
switch (ConstraintCode) {
default: return true;
case 'm': // memory
@ -192,9 +192,9 @@ namespace {
#include "AlphaGenDAGISel.inc"
private:
SDOperand getGlobalBaseReg();
SDOperand getGlobalRetAddr();
void SelectCALL(SDOperand Op);
SDValue getGlobalBaseReg();
SDValue getGlobalRetAddr();
void SelectCALL(SDValue Op);
};
}
@ -202,7 +202,7 @@ private:
/// getGlobalBaseReg - Output the instructions required to put the
/// GOT address into a register.
///
SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
SDValue AlphaDAGToDAGISel::getGlobalBaseReg() {
unsigned GP = 0;
for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(),
ee = RegInfo->livein_end(); ii != ee; ++ii)
@ -217,7 +217,7 @@ SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
/// getRASaveReg - Grab the return address
///
SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() {
SDValue AlphaDAGToDAGISel::getGlobalRetAddr() {
unsigned RA = 0;
for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(),
ee = RegInfo->livein_end(); ii != ee; ++ii)
@ -242,7 +242,7 @@ void AlphaDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
SDNode *AlphaDAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.Val;
if (N->isMachineOpcode()) {
return NULL; // Already selected.
@ -261,26 +261,26 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
getI64Imm(0));
}
case ISD::GLOBAL_OFFSET_TABLE: {
SDOperand Result = getGlobalBaseReg();
SDValue Result = getGlobalBaseReg();
ReplaceUses(Op, Result);
return NULL;
}
case AlphaISD::GlobalRetAddr: {
SDOperand Result = getGlobalRetAddr();
SDValue Result = getGlobalRetAddr();
ReplaceUses(Op, Result);
return NULL;
}
case AlphaISD::DivCall: {
SDOperand Chain = CurDAG->getEntryNode();
SDOperand N0 = Op.getOperand(0);
SDOperand N1 = Op.getOperand(1);
SDOperand N2 = Op.getOperand(2);
SDValue Chain = CurDAG->getEntryNode();
SDValue N0 = Op.getOperand(0);
SDValue N1 = Op.getOperand(1);
SDValue N2 = Op.getOperand(2);
AddToISelQueue(N0);
AddToISelQueue(N1);
AddToISelQueue(N2);
Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1,
SDOperand(0,0));
SDValue(0,0));
Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2,
Chain.getValue(1));
Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0,
@ -289,12 +289,12 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
Chain, Chain.getValue(1));
Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
SDOperand(CNode, 1));
SDValue(CNode, 1));
return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain);
}
case ISD::READCYCLECOUNTER: {
SDOperand Chain = N->getOperand(0);
SDValue Chain = N->getOperand(0);
AddToISelQueue(Chain); //Select chain
return CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other,
Chain);
@ -304,7 +304,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
uint64_t uval = cast<ConstantSDNode>(N)->getValue();
if (uval == 0) {
SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
Alpha::R31, MVT::i64);
ReplaceUses(Op, Result);
return NULL;
@ -321,11 +321,11 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
break; //(zext (LDAH (LDA)))
//Else use the constant pool
ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval);
SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
getGlobalBaseReg());
return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
CPI, SDValue(Tmp, 0), CurDAG->getEntryNode());
}
case ISD::TargetConstantFP: {
ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
@ -371,13 +371,13 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
case ISD::SETUO:
Opc = Alpha::CMPTUN; break;
};
SDOperand tmp1 = N->getOperand(rev?1:0);
SDOperand tmp2 = N->getOperand(rev?0:1);
SDValue tmp1 = N->getOperand(rev?1:0);
SDValue tmp2 = N->getOperand(rev?0:1);
AddToISelQueue(tmp1);
AddToISelQueue(tmp2);
SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64, tmp1, tmp2);
if (inv)
cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDOperand(cmp, 0),
cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDValue(cmp, 0),
CurDAG->getRegister(Alpha::F31, MVT::f64));
switch(CC) {
case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE:
@ -386,16 +386,16 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, MVT::f64,
tmp1, tmp2);
cmp = CurDAG->getTargetNode(Alpha::ADDT, MVT::f64,
SDOperand(cmp2, 0), SDOperand(cmp, 0));
SDValue(cmp2, 0), SDValue(cmp, 0));
break;
}
default: break;
}
SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, MVT::i64, SDOperand(cmp, 0));
SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, MVT::i64, SDValue(cmp, 0));
return CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
CurDAG->getRegister(Alpha::R31, MVT::i64),
SDOperand(LD,0));
SDValue(LD,0));
}
break;
@ -408,16 +408,16 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
// so that things like this can be caught in fall though code
//move int to fp
bool isDouble = N->getValueType(0) == MVT::f64;
SDOperand cond = N->getOperand(0);
SDOperand TV = N->getOperand(1);
SDOperand FV = N->getOperand(2);
SDValue cond = N->getOperand(0);
SDValue TV = N->getOperand(1);
SDValue FV = N->getOperand(2);
AddToISelQueue(cond);
AddToISelQueue(TV);
AddToISelQueue(FV);
SDNode* LD = CurDAG->getTargetNode(Alpha::ITOFT, MVT::f64, cond);
return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
MVT::f64, FV, TV, SDOperand(LD,0));
MVT::f64, FV, TV, SDValue(LD,0));
}
break;
@ -442,8 +442,8 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
if (get_zapImm(mask)) {
AddToISelQueue(N->getOperand(0).getOperand(0));
SDOperand Z =
SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
SDValue Z =
SDValue(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
N->getOperand(0).getOperand(0),
getI64Imm(get_zapImm(mask))), 0);
return CurDAG->getTargetNode(Alpha::SRLr, MVT::i64, Z,
@ -458,16 +458,16 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
return SelectCode(Op);
}
void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
void AlphaDAGToDAGISel::SelectCALL(SDValue Op) {
//TODO: add flag stuff to prevent nondeturministic breakage!
SDNode *N = Op.Val;
SDOperand Chain = N->getOperand(0);
SDOperand Addr = N->getOperand(1);
SDOperand InFlag(0,0); // Null incoming flag value.
SDValue Chain = N->getOperand(0);
SDValue Addr = N->getOperand(1);
SDValue InFlag(0,0); // Null incoming flag value.
AddToISelQueue(Chain);
std::vector<SDOperand> CallOperands;
std::vector<SDValue> CallOperands;
std::vector<MVT> TypeOperands;
//grab the arguments
@ -494,10 +494,10 @@ void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
} else
assert(0 && "Unknown operand");
SDOperand Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8),
SDValue Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8),
CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
Chain };
Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0);
Chain = SDValue(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0);
}
for (int i = 0; i < std::min(6, count); ++i) {
if (TypeOperands[i].isInteger()) {
@ -513,21 +513,21 @@ void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
// Finally, once everything is in registers to pass to the call, emit the
// call itself.
if (Addr.getOpcode() == AlphaISD::GPRelLo) {
SDOperand GOT = getGlobalBaseReg();
SDValue GOT = getGlobalBaseReg();
Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
InFlag = Chain.getValue(1);
Chain = SDOperand(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
Addr.getOperand(0), Chain, InFlag), 0);
} else {
AddToISelQueue(Addr);
Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
InFlag = Chain.getValue(1);
Chain = SDOperand(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
Chain = SDValue(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
Chain, InFlag), 0);
}
InFlag = Chain.getValue(1);
std::vector<SDOperand> CallResults;
std::vector<SDValue> CallResults;
switch (N->getValueType(0).getSimpleVT()) {
default: assert(0 && "Unexpected ret value!");

128
lib/Target/Alpha/AlphaISelLowering.cpp
View File

@ -146,7 +146,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
computeRegisterProperties();
}
MVT AlphaTargetLowering::getSetCCResultType(const SDOperand &) const {
MVT AlphaTargetLowering::getSetCCResultType(const SDValue &) const {
return MVT::i64;
}
@ -168,15 +168,15 @@ const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
}
}
static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
static SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
MVT PtrVT = Op.getValueType();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
SDOperand Zero = DAG.getConstant(0, PtrVT);
SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
SDValue Zero = DAG.getConstant(0, PtrVT);
SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI,
SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI,
DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
return Lo;
}
@ -199,13 +199,13 @@ static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
// //#define GP $29
// //#define SP $30
static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
static SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG,
int &VarArgsBase,
int &VarArgsOffset) {
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
std::vector<SDOperand> ArgValues;
SDOperand Root = Op.getOperand(0);
std::vector<SDValue> ArgValues;
SDValue Root = Op.getOperand(0);
AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass); //GP
AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass); //RA
@ -216,9 +216,9 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
SDOperand argt;
SDValue argt;
MVT ObjectVT = Op.getValue(ArgNo).getValueType();
SDOperand ArgVal;
SDValue ArgVal;
if (ArgNo < 6) {
switch (ObjectVT.getSimpleVT()) {
@ -246,7 +246,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
// Create the SelectionDAG nodes corresponding to a load
//from this parameter
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
}
ArgValues.push_back(ArgVal);
@ -256,14 +256,14 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
if (isVarArg) {
VarArgsOffset = (Op.Val->getNumValues()-1) * 8;
std::vector<SDOperand> LS;
std::vector<SDValue> LS;
for (int i = 0; i < 6; ++i) {
if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
SDOperand argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64);
SDValue argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64);
int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
if (i == 0) VarArgsBase = FI;
SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
SDValue SDFI = DAG.getFrameIndex(FI, MVT::i64);
LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
if (TargetRegisterInfo::isPhysicalRegister(args_float[i]))
@ -285,18 +285,18 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
ArgValues.size());
}
static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
SDValue Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
DAG.getNode(AlphaISD::GlobalRetAddr,
MVT::i64),
SDOperand());
SDValue());
switch (Op.getNumOperands()) {
default:
assert(0 && "Do not know how to return this many arguments!");
abort();
case 1:
break;
//return SDOperand(); // ret void is legal
//return SDValue(); // ret void is legal
case 3: {
MVT ArgVT = Op.getOperand(1).getValueType();
unsigned ArgReg;
@ -315,11 +315,11 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
}
std::pair<SDOperand, SDOperand>
AlphaTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
std::pair<SDValue, SDValue>
AlphaTargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
bool RetSExt, bool RetZExt, bool isVarArg,
unsigned CallingConv, bool isTailCall,
SDOperand Callee, ArgListTy &Args,
SDValue Callee, ArgListTy &Args,
SelectionDAG &DAG) {
int NumBytes = 0;
if (Args.size() > 6)
@ -327,7 +327,7 @@ AlphaTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
Chain = DAG.getCALLSEQ_START(Chain,
DAG.getConstant(NumBytes, getPointerTy()));
std::vector<SDOperand> args_to_use;
std::vector<SDValue> args_to_use;
for (unsigned i = 0, e = Args.size(); i != e; ++i)
{
switch (getValueType(Args[i].Ty).getSimpleVT()) {
@ -363,17 +363,17 @@ AlphaTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
RetVals.push_back(ActualRetTyVT);
RetVals.push_back(MVT::Other);
std::vector<SDOperand> Ops;
std::vector<SDValue> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
SDOperand TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size());
SDValue TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size());
Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
Chain = DAG.getCALLSEQ_END(Chain,
DAG.getConstant(NumBytes, getPointerTy()),
DAG.getConstant(0, getPointerTy()),
SDOperand());
SDOperand RetVal = TheCall;
SDValue());
SDValue RetVal = TheCall;
if (RetTyVT != ActualRetTyVT) {
ISD::NodeType AssertKind = ISD::DELETED_NODE;
@ -392,29 +392,29 @@ AlphaTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
return std::make_pair(RetVal, Chain);
}
void AlphaTargetLowering::LowerVAARG(SDNode *N, SDOperand &Chain,
SDOperand &DataPtr, SelectionDAG &DAG) {
void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain,
SDValue &DataPtr, SelectionDAG &DAG) {
Chain = N->getOperand(0);
SDOperand VAListP = N->getOperand(1);
SDValue VAListP = N->getOperand(1);
const Value *VAListS = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS, 0);
SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
SDValue Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS, 0);
SDValue Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
DAG.getConstant(8, MVT::i64));
SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
Tmp, NULL, 0, MVT::i32);
DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
if (N->getValueType(0).isFloatingPoint())
{
//if fp && Offset < 6*8, then subtract 6*8 from DataPtr
SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
SDValue FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
DAG.getConstant(8*6, MVT::i64));
SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
SDValue CC = DAG.getSetCC(MVT::i64, Offset,
DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
}
SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
SDValue NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
DAG.getConstant(8, MVT::i64));
Chain = DAG.getTruncStore(Offset.getValue(1), NewOffset, Tmp, NULL, 0,
MVT::i32);
@ -422,7 +422,7 @@ void AlphaTargetLowering::LowerVAARG(SDNode *N, SDOperand &Chain,
/// LowerOperation - Provide custom lowering hooks for some operations.
///
SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
default: assert(0 && "Wasn't expecting to be able to lower this!");
case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
@ -435,16 +435,16 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
case ISD::SINT_TO_FP: {
assert(Op.getOperand(0).getValueType() == MVT::i64 &&
"Unhandled SINT_TO_FP type in custom expander!");
SDOperand LD;
SDValue LD;
bool isDouble = Op.getValueType() == MVT::f64;
LD = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
SDValue FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
isDouble?MVT::f64:MVT::f32, LD);
return FP;
}
case ISD::FP_TO_SINT: {
bool isDouble = Op.getOperand(0).getValueType() == MVT::f64;
SDOperand src = Op.getOperand(0);
SDValue src = Op.getOperand(0);
if (!isDouble) //Promote
src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
@ -456,11 +456,11 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
case ISD::ConstantPool: {
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
Constant *C = CP->getConstVal();
SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
SDValue CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
return Lo;
}
case ISD::GlobalTLSAddress:
@ -468,13 +468,13 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
case ISD::GlobalAddress: {
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
GlobalValue *GV = GSDN->getGlobal();
SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
// if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
if (GV->hasInternalLinkage()) {
SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
return Lo;
} else
return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA,
@ -492,7 +492,7 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
//Expand only on constant case
if (Op.getOperand(1).getOpcode() == ISD::Constant) {
MVT VT = Op.Val->getValueType(0);
SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
SDValue Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
BuildUDIV(Op.Val, DAG, NULL) :
BuildSDIV(Op.Val, DAG, NULL);
Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
@ -513,7 +513,7 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
case ISD::UDIV: opstr = "__divqu"; break;
case ISD::SDIV: opstr = "__divq"; break;
}
SDOperand Tmp1 = Op.getOperand(0),
SDValue Tmp1 = Op.getOperand(0),
Tmp2 = Op.getOperand(1),
Addr = DAG.getExternalSymbol(opstr, MVT::i64);
return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
@ -521,10 +521,10 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
break;
case ISD::VAARG: {
SDOperand Chain, DataPtr;
SDValue Chain, DataPtr;
LowerVAARG(Op.Val, Chain, DataPtr, DAG);
SDOperand Result;
SDValue Result;
if (Op.getValueType() == MVT::i32)
Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Chain, DataPtr,
NULL, 0, MVT::i32);
@ -533,30 +533,30 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
return Result;
}
case ISD::VACOPY: {
SDOperand Chain = Op.getOperand(0);
SDOperand DestP = Op.getOperand(1);
SDOperand SrcP = Op.getOperand(2);
SDValue Chain = Op.getOperand(0);
SDValue DestP = Op.getOperand(1);
SDValue SrcP = Op.getOperand(2);
const Value *DestS = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
const Value *SrcS = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS, 0);
SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS, 0);
SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
SDValue Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS, 0);
SDValue Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS, 0);
SDValue NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
DAG.getConstant(8, MVT::i64));
Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32);
SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
SDValue NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
DAG.getConstant(8, MVT::i64));
return DAG.getTruncStore(Val.getValue(1), Val, NPD, NULL, 0, MVT::i32);
}
case ISD::VASTART: {
SDOperand Chain = Op.getOperand(0);
SDOperand VAListP = Op.getOperand(1);
SDValue Chain = Op.getOperand(0);
SDValue VAListP = Op.getOperand(1);
const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
// vastart stores the address of the VarArgsBase and VarArgsOffset
SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS, 0);
SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
SDValue FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
SDValue S1 = DAG.getStore(Chain, FR, VAListP, VAListS, 0);
SDValue SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
DAG.getConstant(8, MVT::i64));
return DAG.getTruncStore(S1, DAG.getConstant(VarArgsOffset, MVT::i64),
SA2, NULL, 0, MVT::i32);
@ -567,7 +567,7 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
case ISD::FRAMEADDR: break;
}
return SDOperand();
return SDValue();
}
SDNode *AlphaTargetLowering::ReplaceNodeResults(SDNode *N,
@ -576,7 +576,7 @@ SDNode *AlphaTargetLowering::ReplaceNodeResults(SDNode *N,
N->getOpcode() == ISD::VAARG &&
"Unknown node to custom promote!");
SDOperand Chain, DataPtr;
SDValue Chain, DataPtr;
LowerVAARG(N, Chain, DataPtr, DAG);
return DAG.getLoad(N->getValueType(0), Chain, DataPtr, NULL, 0).Val;
}

12
lib/Target/Alpha/AlphaISelLowering.h
View File

@ -67,11 +67,11 @@ namespace llvm {
explicit AlphaTargetLowering(TargetMachine &TM);
/// getSetCCResultType - Get the SETCC result ValueType
virtual MVT getSetCCResultType(const SDOperand &) const;
virtual MVT getSetCCResultType(const SDValue &) const;
/// LowerOperation - Provide custom lowering hooks for some operations.
///
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
virtual SDNode *ReplaceNodeResults(SDNode *N, SelectionDAG &DAG);
// Friendly names for dumps
@ -79,9 +79,9 @@ namespace llvm {
/// LowerCallTo - This hook lowers an abstract call to a function into an
/// actual call.
virtual std::pair<SDOperand, SDOperand>
LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee,
virtual std::pair<SDValue, SDValue>
LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
bool isVarArg, unsigned CC, bool isTailCall, SDValue Callee,
ArgListTy &Args, SelectionDAG &DAG);
ConstraintType getConstraintType(const std::string &Constraint) const;
@ -97,7 +97,7 @@ namespace llvm {
private:
// Helpers for custom lowering.
void LowerVAARG(SDNode *N, SDOperand &Chain, SDOperand &DataPtr,
void LowerVAARG(SDNode *N, SDValue &Chain, SDValue &DataPtr,
SelectionDAG &DAG);
};

2
lib/Target/Alpha/AlphaInstrInfo.td
View File

@ -62,7 +62,7 @@ def LH16 : SDNodeXForm<imm, [{ //ldah part of constant (or more if too big)
}]>;
def iZAPX : SDNodeXForm<and, [{ // get imm to ZAPi
ConstantSDNode *RHS = cast<ConstantSDNode>(N->getOperand(1));
return getI64Imm(get_zapImm(SDOperand(), RHS->getValue()));
return getI64Imm(get_zapImm(SDValue(), RHS->getValue()));
}]>;
def nearP2X : SDNodeXForm<imm, [{
return getI64Imm(Log2_64(getNearPower2((uint64_t)N->getValue())));

90
lib/Target/CellSPU/SPUISelDAGToDAG.cpp
View File

@ -151,7 +151,7 @@ namespace {
}
bool
isHighLow(const SDOperand &Op)
isHighLow(const SDValue &Op)
{
return (Op.getOpcode() == SPUISD::IndirectAddr
&& ((Op.getOperand(0).getOpcode() == SPUISD::Hi
@ -242,52 +242,52 @@ public:
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
inline SDOperand getI32Imm(uint32_t Imm) {
inline SDValue getI32Imm(uint32_t Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i32);
}
/// getI64Imm - Return a target constant with the specified value, of type
/// i64.
inline SDOperand getI64Imm(uint64_t Imm) {
inline SDValue getI64Imm(uint64_t Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i64);
}
/// getSmallIPtrImm - Return a target constant of pointer type.
inline SDOperand getSmallIPtrImm(unsigned Imm) {
inline SDValue getSmallIPtrImm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
}
/// Select - Convert the specified operand from a target-independent to a
/// target-specific node if it hasn't already been changed.
SDNode *Select(SDOperand Op);
SDNode *Select(SDValue Op);
//! Returns true if the address N is an A-form (local store) address
bool SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Index);
bool SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
SDValue &Index);
//! D-form address predicate
bool SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Index);
bool SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
SDValue &Index);
/// Alternate D-form address using i7 offset predicate
bool SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
SDOperand &Base);
bool SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
SDValue &Base);
/// D-form address selection workhorse
bool DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Disp,
SDOperand &Base, int minOffset, int maxOffset);
bool DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Disp,
SDValue &Base, int minOffset, int maxOffset);
//! Address predicate if N can be expressed as an indexed [r+r] operation.
bool SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Index);
bool SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
SDValue &Index);
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
std::vector<SDOperand> &OutOps,
std::vector<SDValue> &OutOps,
SelectionDAG &DAG) {
SDOperand Op0, Op1;
SDValue Op0, Op1;
switch (ConstraintCode) {
default: return true;
case 'm': // memory
@ -358,11 +358,11 @@ SPUDAGToDAGISel::InstructionSelect(SelectionDAG &DAG)
\arg Index The base address index
*/
bool
SPUDAGToDAGISel::SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Index) {
SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
SDValue &Index) {
// These match the addr256k operand type:
MVT OffsVT = MVT::i16;
SDOperand Zero = CurDAG->getTargetConstant(0, OffsVT);
SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
switch (N.getOpcode()) {
case ISD::Constant:
@ -384,7 +384,7 @@ SPUDAGToDAGISel::SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
// Just load from memory if there's only a single use of the location,
// otherwise, this will get handled below with D-form offset addresses
if (N.hasOneUse()) {
SDOperand Op0 = N.getOperand(0);
SDValue Op0 = N.getOperand(0);
switch (Op0.getOpcode()) {
case ISD::TargetConstantPool:
case ISD::TargetJumpTable:
@ -410,8 +410,8 @@ SPUDAGToDAGISel::SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
}
bool
SPUDAGToDAGISel::SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
SDOperand &Base) {
SPUDAGToDAGISel::SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
SDValue &Base) {
const int minDForm2Offset = -(1 << 7);
const int maxDForm2Offset = (1 << 7) - 1;
return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
@ -428,19 +428,19 @@ SPUDAGToDAGISel::SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
displacement, [r+I10] (D-form address).
\return true if \a N is a D-form address with \a Base and \a Index set
to non-empty SDOperand instances.
to non-empty SDValue instances.
*/
bool
SPUDAGToDAGISel::SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Index) {
SPUDAGToDAGISel::SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
SDValue &Index) {
return DFormAddressPredicate(Op, N, Base, Index,
SPUFrameInfo::minFrameOffset(),
SPUFrameInfo::maxFrameOffset());
}
bool
SPUDAGToDAGISel::DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Index, int minOffset,
SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
SDValue &Index, int minOffset,
int maxOffset) {
unsigned Opc = N.getOpcode();
MVT PtrTy = SPUtli.getPointerTy();
@ -458,8 +458,8 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Bas
}
} else if (Opc == ISD::ADD) {
// Generated by getelementptr
const SDOperand Op0 = N.getOperand(0);
const SDOperand Op1 = N.getOperand(1);
const SDValue Op0 = N.getOperand(0);
const SDValue Op1 = N.getOperand(1);
if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
|| (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
@ -511,8 +511,8 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Bas
}
} else if (Opc == SPUISD::IndirectAddr) {
// Indirect with constant offset -> D-Form address
const SDOperand Op0 = N.getOperand(0);
const SDOperand Op1 = N.getOperand(1);
const SDValue Op0 = N.getOperand(0);
const SDValue Op1 = N.getOperand(1);
if (Op0.getOpcode() == SPUISD::Hi
&& Op1.getOpcode() == SPUISD::Lo) {
@ -522,7 +522,7 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Bas
return true;
} else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
int32_t offset = 0;
SDOperand idxOp;
SDValue idxOp;
if (isa<ConstantSDNode>(Op1)) {
ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
@ -563,8 +563,8 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Bas
address.
*/
bool
SPUDAGToDAGISel::SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Index) {
SPUDAGToDAGISel::SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
SDValue &Index) {
if (SelectAFormAddr(Op, N, Base, Index)
|| SelectDFormAddr(Op, N, Base, Index))
return false;
@ -579,13 +579,13 @@ SPUDAGToDAGISel::SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
/*!
*/
SDNode *
SPUDAGToDAGISel::Select(SDOperand Op) {
SPUDAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.Val;
unsigned Opc = N->getOpcode();
int n_ops = -1;
unsigned NewOpc;
MVT OpVT = Op.getValueType();
SDOperand Ops[8];
SDValue Ops[8];
if (N->isMachineOpcode()) {
return NULL; // Already selected.
@ -617,7 +617,7 @@ SPUDAGToDAGISel::Select(SDOperand Op) {
}
} else if (Opc == ISD::ZERO_EXTEND) {
// (zero_extend:i16 (and:i8 <arg>, <const>))
const SDOperand &Op1 = N->getOperand(0);
const SDValue &Op1 = N->getOperand(0);
if (Op.getValueType() == MVT::i16 && Op1.getValueType() == MVT::i8) {
if (Op1.getOpcode() == ISD::AND) {
@ -634,8 +634,8 @@ SPUDAGToDAGISel::Select(SDOperand Op) {
} else if (Opc == SPUISD::LDRESULT) {
// Custom select instructions for LDRESULT
MVT VT = N->getValueType(0);
SDOperand Arg = N->getOperand(0);
SDOperand Chain = N->getOperand(1);
SDValue Arg = N->getOperand(0);
SDValue Chain = N->getOperand(1);
SDNode *Result;
const valtype_map_s *vtm = getValueTypeMapEntry(VT);
@ -649,7 +649,7 @@ SPUDAGToDAGISel::Select(SDOperand Op) {
AddToISelQueue(Arg);
Opc = vtm->ldresult_ins;
if (vtm->ldresult_imm) {
SDOperand Zero = CurDAG->getTargetConstant(0, VT);
SDValue Zero = CurDAG->getTargetConstant(0, VT);
AddToISelQueue(Zero);
Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain);
@ -657,16 +657,16 @@ SPUDAGToDAGISel::Select(SDOperand Op) {
Result = CurDAG->getTargetNode(Opc, MVT::Other, Arg, Arg, Chain);
}
Chain = SDOperand(Result, 1);
Chain = SDValue(Result, 1);
AddToISelQueue(Chain);
return Result;
} else if (Opc == SPUISD::IndirectAddr) {
SDOperand Op0 = Op.getOperand(0);
SDValue Op0 = Op.getOperand(0);
if (Op0.getOpcode() == SPUISD::LDRESULT) {
/* || Op0.getOpcode() == SPUISD::AFormAddr) */
// (IndirectAddr (LDRESULT, imm))
SDOperand Op1 = Op.getOperand(1);
SDValue Op1 = Op.getOperand(1);
MVT VT = Op.getValueType();
DEBUG(cerr << "CellSPU: IndirectAddr(LDRESULT, imm):\nOp0 = ");

576
lib/Target/CellSPU/SPUISelLowering.cpp
View File

File diff suppressed because it is too large Load Diff

26
lib/Target/CellSPU/SPUISelLowering.h
View File

@ -78,18 +78,18 @@ namespace llvm {
/// Predicates that are used for node matching:
namespace SPU {
SDOperand get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
MVT ValueType);
SDOperand get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
MVT ValueType);
SDOperand get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
MVT ValueType);
SDOperand get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
MVT ValueType);
SDOperand get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
MVT ValueType);
SDOperand get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
SDOperand get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
}
class SPUTargetMachine; // forward dec'l.
@ -109,15 +109,15 @@ namespace llvm {
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - Return the ValueType for ISD::SETCC
virtual MVT getSetCCResultType(const SDOperand &) const;
virtual MVT getSetCCResultType(const SDValue &) const;
/// LowerOperation - Provide custom lowering hooks for some operations.
///
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
virtual void computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
APInt &KnownZero,
APInt &KnownOne,
@ -130,8 +130,8 @@ namespace llvm {
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT VT) const;
void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter,
std::vector<SDOperand> &Ops,
void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const;
/// isLegalAddressImmediate - Return true if the integer value can be used

4
lib/Target/CellSPU/SPUOperands.td
View File

@ -16,7 +16,7 @@ def LO16 : SDNodeXForm<imm, [{
}]>;
def LO16_vec : SDNodeXForm<scalar_to_vector, [{
SDOperand OpVal(0, 0);
SDValue OpVal(0, 0);
// Transformation function: get the low 16 bit immediate from a build_vector
// node.
@ -43,7 +43,7 @@ def HI16 : SDNodeXForm<imm, [{
// Transformation function: shift the high 16 bit immediate from a build_vector
// node into the low 16 bits, and return a 16-bit constant.
def HI16_vec : SDNodeXForm<scalar_to_vector, [{
SDOperand OpVal(0, 0);
SDValue OpVal(0, 0);
assert(N->getOpcode() == ISD::BUILD_VECTOR
&& "HI16_vec got something other than a BUILD_VECTOR");

198
lib/Target/IA64/IA64ISelDAGToDAG.cpp
View File

@ -51,19 +51,19 @@ namespace {
/// getI64Imm - Return a target constant with the specified value, of type
/// i64.
inline SDOperand getI64Imm(uint64_t Imm) {
inline SDValue getI64Imm(uint64_t Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i64);
}
/// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
/// base register. Return the virtual register that holds this value.
// SDOperand getGlobalBaseReg(); TODO: hmm
// SDValue getGlobalBaseReg(); TODO: hmm
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
SDNode *Select(SDOperand N);
SDNode *Select(SDValue N);
SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
SDNode *SelectIntImmediateExpr(SDValue LHS, SDValue RHS,
unsigned OCHi, unsigned OCLo,
bool IsArithmetic = false,
bool Negate = false);
@ -71,12 +71,12 @@ namespace {
/// SelectCC - Select a comparison of the specified values with the
/// specified condition code, returning the CR# of the expression.
SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC);
/// SelectAddr - Given the specified address, return the two operands for a
/// load/store instruction, and return true if it should be an indexed [r+r]
/// operation.
bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
bool SelectAddr(SDValue Addr, SDValue &Op1, SDValue &Op2);
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
@ -90,7 +90,7 @@ namespace {
#include "IA64GenDAGISel.inc"
private:
SDNode *SelectDIV(SDOperand Op);
SDNode *SelectDIV(SDValue Op);
};
}
@ -104,11 +104,11 @@ void IA64DAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
DAG.RemoveDeadNodes();
}
SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) {
SDNode *N = Op.Val;
SDOperand Chain = N->getOperand(0);
SDOperand Tmp1 = N->getOperand(0);
SDOperand Tmp2 = N->getOperand(1);
SDValue Chain = N->getOperand(0);
SDValue Tmp1 = N->getOperand(0);
SDValue Tmp2 = N->getOperand(1);
AddToISelQueue(Chain);
AddToISelQueue(Tmp1);
@ -133,40 +133,40 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
// TODO: check for integer divides by powers of 2 (or other simple patterns?)
SDOperand TmpPR, TmpPR2;
SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
SDValue TmpPR, TmpPR2;
SDValue TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
SDValue TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
SDNode *Result;
// we'll need copies of F0 and F1
SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
SDValue F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
SDValue F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
// OK, emit some code:
if(!isFP) {
// first, load the inputs into FP regs.
TmpF1 =
SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0);
SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0);
Chain = TmpF1.getValue(1);
TmpF2 =
SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0);
SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0);
Chain = TmpF2.getValue(1);
// next, convert the inputs to FP
if(isSigned) {
TmpF3 =
SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0);
SDValue(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0);
Chain = TmpF3.getValue(1);
TmpF4 =
SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0);
SDValue(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0);
Chain = TmpF4.getValue(1);
} else { // is unsigned
TmpF3 =
SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0);
SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0);
Chain = TmpF3.getValue(1);
TmpF4 =
SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0);
SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0);
Chain = TmpF4.getValue(1);
}
@ -179,39 +179,39 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
// we start by computing an approximate reciprocal (good to 9 bits?)
// note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
if(isFP)
TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
TmpF3, TmpF4), 0);
else
TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
TmpF3, TmpF4), 0);
TmpPR = TmpF5.getValue(1);
Chain = TmpF5.getValue(2);
SDOperand minusB;
SDValue minusB;
if(isModulus) { // for remainders, it'll be handy to have
// copies of -input_b
minusB = SDOperand(CurDAG->getTargetNode(IA64::SUB, MVT::i64,
minusB = SDValue(CurDAG->getTargetNode(IA64::SUB, MVT::i64,
CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0);
Chain = minusB.getValue(1);
}
SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
SDValue TmpE0, TmpY1, TmpE1, TmpY2;
SDOperand OpsE0[] = { TmpF4, TmpF5, F1, TmpPR };
TmpE0 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
SDValue OpsE0[] = { TmpF4, TmpF5, F1, TmpPR };
TmpE0 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
OpsE0, 4), 0);
Chain = TmpE0.getValue(1);
SDOperand OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR };
TmpY1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
SDValue OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR };
TmpY1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
OpsY1, 4), 0);
Chain = TmpY1.getValue(1);
SDOperand OpsE1[] = { TmpE0, TmpE0, F0, TmpPR };
TmpE1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
SDValue OpsE1[] = { TmpE0, TmpE0, F0, TmpPR };
TmpE1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
OpsE1, 4), 0);
Chain = TmpE1.getValue(1);
SDOperand OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR };
TmpY2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
SDValue OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR };
TmpY2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
OpsY2, 4), 0);
Chain = TmpY2.getValue(1);
@ -219,53 +219,53 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
if(isModulus)
assert(0 && "Sorry, try another FORTRAN compiler.");
SDOperand TmpE2, TmpY3, TmpQ0, TmpR0;
SDValue TmpE2, TmpY3, TmpQ0, TmpR0;
SDOperand OpsE2[] = { TmpE1, TmpE1, F0, TmpPR };
TmpE2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
SDValue OpsE2[] = { TmpE1, TmpE1, F0, TmpPR };
TmpE2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
OpsE2, 4), 0);
Chain = TmpE2.getValue(1);
SDOperand OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR };
TmpY3 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
SDValue OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR };
TmpY3 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
OpsY3, 4), 0);
Chain = TmpY3.getValue(1);
SDOperand OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR };
SDValue OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR };
TmpQ0 =
SDOperand(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
SDValue(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
OpsQ0, 4), 0);
Chain = TmpQ0.getValue(1);
SDOperand OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR };
SDValue OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR };
TmpR0 =
SDOperand(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
SDValue(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
OpsR0, 4), 0);
Chain = TmpR0.getValue(1);
// we want Result to have the same target register as the frcpa, so
// we two-address hack it. See the comment "for this to work..." on
// page 48 of Intel application note #245415
SDOperand Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR };
SDValue Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR };
Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
Ops, 5);
Chain = SDOperand(Result, 1);
Chain = SDValue(Result, 1);
return Result; // XXX: early exit!
} else { // this is *not* an FP divide, so there's a bit left to do:
SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
SDValue TmpQ2, TmpR2, TmpQ3, TmpQ;
SDOperand OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR };
TmpQ2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
SDValue OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR };
TmpQ2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
OpsQ2, 4), 0);
Chain = TmpQ2.getValue(1);
SDOperand OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR };
TmpR2 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
SDValue OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR };
TmpR2 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
OpsR2, 4), 0);
Chain = TmpR2.getValue(1);
// we want TmpQ3 to have the same target register as the frcpa? maybe we
// should two-address hack it. See the comment "for this to work..." on page
// 48 of Intel application note #245415
SDOperand OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR };
TmpQ3 = SDOperand(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
SDValue OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR };
TmpQ3 = SDValue(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
OpsQ3, 5), 0);
Chain = TmpQ3.getValue(1);
@ -274,27 +274,27 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
// arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
if(isSigned)
TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1,
TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1,
MVT::f64, TmpQ3), 0);
else
TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1,
TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1,
MVT::f64, TmpQ3), 0);
Chain = TmpQ.getValue(1);
if(isModulus) {
SDOperand FPminusB =
SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0);
SDValue FPminusB =
SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0);
Chain = FPminusB.getValue(1);
SDOperand Remainder =
SDOperand(CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
SDValue Remainder =
SDValue(CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
TmpQ, FPminusB, TmpF1), 0);
Chain = Remainder.getValue(1);
Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder);
Chain = SDOperand(Result, 1);
Chain = SDValue(Result, 1);
} else { // just an integer divide
Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ);
Chain = SDOperand(Result, 1);
Chain = SDValue(Result, 1);
}
return Result;
@ -303,7 +303,7 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
SDNode *IA64DAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.Val;
if (N->isMachineOpcode())
return NULL; // Already selected.
@ -312,8 +312,8 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
default: break;
case IA64ISD::BRCALL: { // XXX: this is also a hack!
SDOperand Chain = N->getOperand(0);
SDOperand InFlag; // Null incoming flag value.
SDValue Chain = N->getOperand(0);
SDValue InFlag; // Null incoming flag value.
AddToISelQueue(Chain);
if(N->getNumOperands()==3) { // we have an incoming chain, callee and flag
@ -322,7 +322,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
}
unsigned CallOpcode;
SDOperand CallOperand;
SDValue CallOperand;
// if we can call directly, do so
if (GlobalAddressSDNode *GASD =
@ -338,22 +338,22 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
// otherwise we need to load the function descriptor,
// load the branch target (function)'s entry point and GP,
// branch (call) then restore the GP
SDOperand FnDescriptor = N->getOperand(1);
SDValue FnDescriptor = N->getOperand(1);
AddToISelQueue(FnDescriptor);
// load the branch target's entry point [mem] and
// GP value [mem+8]
SDOperand targetEntryPoint=
SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, MVT::Other,
SDValue targetEntryPoint=
SDValue(CurDAG->getTargetNode(IA64::LD8, MVT::i64, MVT::Other,
FnDescriptor, CurDAG->getEntryNode()), 0);
Chain = targetEntryPoint.getValue(1);
SDOperand targetGPAddr=
SDOperand(CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
SDValue targetGPAddr=
SDValue(CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
FnDescriptor,
CurDAG->getConstant(8, MVT::i64)), 0);
Chain = targetGPAddr.getValue(1);
SDOperand targetGP =
SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64,MVT::Other,
SDValue targetGP =
SDValue(CurDAG->getTargetNode(IA64::LD8, MVT::i64,MVT::Other,
targetGPAddr, CurDAG->getEntryNode()), 0);
Chain = targetGP.getValue(1);
@ -368,14 +368,14 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
// Finally, once everything is setup, emit the call itself
if(InFlag.Val)
Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
Chain = SDValue(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
CallOperand, InFlag), 0);
else // there might be no arguments
Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
Chain = SDValue(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
CallOperand, Chain), 0);
InFlag = Chain.getValue(1);
std::vector<SDOperand> CallResults;
std::vector<SDValue> CallResults;
CallResults.push_back(Chain);
CallResults.push_back(InFlag);
@ -386,7 +386,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
}
case IA64ISD::GETFD: {
SDOperand Input = N->getOperand(0);
SDValue Input = N->getOperand(0);
AddToISelQueue(Input);
return CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input);
}
@ -399,9 +399,9 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
return SelectDIV(Op);
case ISD::TargetConstantFP: {
SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
SDValue Chain = CurDAG->getEntryNode(); // this is a constant, so..
SDOperand V;
SDValue V;
ConstantFPSDNode* N2 = cast<ConstantFPSDNode>(N);
if (N2->getValueAPF().isPosZero()) {
V = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
@ -411,7 +411,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
} else
assert(0 && "Unexpected FP constant!");
ReplaceUses(SDOperand(N, 0), V);
ReplaceUses(SDValue(N, 0), V);
return 0;
}
@ -429,7 +429,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
// (ia64 doesn't need one)
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
Constant *C = CP->getConstVal();
SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
CP->getAlignment());
return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
@ -437,9 +437,9 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
case ISD::GlobalAddress: {
GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
SDOperand Tmp =
SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
SDValue GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
SDValue Tmp =
SDValue(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
CurDAG->getRegister(IA64::r1,
MVT::i64), GA), 0);
return CurDAG->getTargetNode(IA64::LD8, MVT::i64, MVT::Other, Tmp,
@ -448,10 +448,10 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
/* XXX
case ISD::ExternalSymbol: {
SDOperand EA = CurDAG->getTargetExternalSymbol(
SDValue EA = CurDAG->getTargetExternalSymbol(
cast<ExternalSymbolSDNode>(N)->getSymbol(),
MVT::i64);
SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
SDValue Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
CurDAG->getRegister(IA64::r1,
MVT::i64),
EA);
@ -461,8 +461,8 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
case ISD::LOAD: { // FIXME: load -1, not 1, for bools?
LoadSDNode *LD = cast<LoadSDNode>(N);
SDOperand Chain = LD->getChain();
SDOperand Address = LD->getBasePtr();
SDValue Chain = LD->getChain();
SDValue Address = LD->getBasePtr();
AddToISelQueue(Chain);
AddToISelQueue(Address);
@ -478,7 +478,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
Opc = IA64::LD1; // first we load a byte, then compare for != 0
if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0),
SDValue(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0),
CurDAG->getRegister(IA64::r0, MVT::i64),
Chain);
}
@ -501,8 +501,8 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
case ISD::STORE: {
StoreSDNode *ST = cast<StoreSDNode>(N);
SDOperand Address = ST->getBasePtr();
SDOperand Chain = ST->getChain();
SDValue Address = ST->getBasePtr();
SDValue Chain = ST->getChain();
AddToISelQueue(Address);
AddToISelQueue(Chain);
@ -513,13 +513,13 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
case MVT::i1: { // this is a bool
Opc = IA64::ST1; // we store either 0 or 1 as a byte
// first load zero!
SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
SDValue Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
Chain = Initial.getValue(1);
// then load 1 into the same reg iff the predicate to store is 1
SDOperand Tmp = ST->getValue();
SDValue Tmp = ST->getValue();
AddToISelQueue(Tmp);
Tmp =
SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
SDValue(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
CurDAG->getTargetConstant(1, MVT::i64),
Tmp), 0);
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
@ -537,16 +537,16 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
}
}
SDOperand N1 = N->getOperand(1);
SDOperand N2 = N->getOperand(2);
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
AddToISelQueue(N1);
AddToISelQueue(N2);
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
}
case ISD::BRCOND: {
SDOperand Chain = N->getOperand(0);
SDOperand CC = N->getOperand(1);
SDValue Chain = N->getOperand(0);
SDValue CC = N->getOperand(1);
AddToISelQueue(Chain);
AddToISelQueue(CC);
MachineBasicBlock *Dest =
@ -561,14 +561,14 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
SDOperand N0 = N->getOperand(0);
SDValue N0 = N->getOperand(0);
AddToISelQueue(N0);
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
}
case ISD::BR:
// FIXME: we don't need long branches all the time!
SDOperand N0 = N->getOperand(0);
SDValue N0 = N->getOperand(0);
AddToISelQueue(N0);
return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
N->getOperand(1), N0);

64
lib/Target/IA64/IA64ISelLowering.cpp
View File

@ -140,12 +140,12 @@ const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const {
}
}
MVT IA64TargetLowering::getSetCCResultType(const SDOperand &) const {
MVT IA64TargetLowering::getSetCCResultType(const SDValue &) const {
return MVT::i1;
}
void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
SmallVectorImpl<SDOperand> &ArgValues) {
SmallVectorImpl<SDValue> &ArgValues) {
//
// add beautiful description of IA64 stack frame format
// here (from intel 24535803.pdf most likely)
@ -177,7 +177,7 @@ void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
{
SDOperand newroot, argt;
SDValue newroot, argt;
if(count < 8) { // need to fix this logic? maybe.
switch (getValueType(I->getType()).getSimpleVT()) {
@ -229,7 +229,7 @@ void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
// Create the SelectionDAG nodes corresponding to a load
//from this parameter
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
argt = newroot = DAG.getLoad(getValueType(I->getType()),
DAG.getEntryNode(), FIN, NULL, 0);
}
@ -302,11 +302,11 @@ void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
}
}
std::pair<SDOperand, SDOperand>
IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
std::pair<SDValue, SDValue>
IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
bool RetSExt, bool RetZExt,
bool isVarArg, unsigned CallingConv,
bool isTailCall, SDOperand Callee,
bool isTailCall, SDValue Callee,
ArgListTy &Args, SelectionDAG &DAG) {
MachineFunction &MF = DAG.getMachineFunction();
@ -335,17 +335,17 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
SDOperand StackPtr;
std::vector<SDOperand> Stores;
std::vector<SDOperand> Converts;
std::vector<SDOperand> RegValuesToPass;
SDValue StackPtr;
std::vector<SDValue> Stores;
std::vector<SDValue> Converts;
std::vector<SDValue> RegValuesToPass;
unsigned ArgOffset = 16;
for (unsigned i = 0, e = Args.size(); i != e; ++i)
{
SDOperand Val = Args[i].Node;
SDValue Val = Args[i].Node;
MVT ObjectVT = Val.getValueType();
SDOperand ValToStore(0, 0), ValToConvert(0, 0);
SDValue ValToStore(0, 0), ValToConvert(0, 0);
unsigned ObjSize=8;
switch (ObjectVT.getSimpleVT()) {
default: assert(0 && "unexpected argument type!");
@ -391,7 +391,7 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
if(!StackPtr.Val) {
StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
}
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
SDValue PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, MVT::i64, StackPtr, PtrOff);
Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
ArgOffset += ObjSize;
@ -416,16 +416,16 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
IA64::F12, IA64::F13, IA64::F14, IA64::F15
};
SDOperand InFlag;
SDValue InFlag;
// save the current GP, SP and RP : FIXME: do we need to do all 3 always?
SDOperand GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64, InFlag);
SDValue GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64, InFlag);
Chain = GPBeforeCall.getValue(1);
InFlag = Chain.getValue(2);
SDOperand SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64, InFlag);
SDValue SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64, InFlag);
Chain = SPBeforeCall.getValue(1);
InFlag = Chain.getValue(2);
SDOperand RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64, InFlag);
SDValue RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64, InFlag);
Chain = RPBeforeCall.getValue(1);
InFlag = Chain.getValue(2);
@ -464,7 +464,7 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
*/
std::vector<MVT> NodeTys;
std::vector<SDOperand> CallOperands;
std::vector<SDValue> CallOperands;
NodeTys.push_back(MVT::Other); // Returns a chain
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
CallOperands.push_back(Chain);
@ -494,17 +494,17 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
RetVals.push_back(MVT::Flag);
MVT RetTyVT = getValueType(RetTy);
SDOperand RetVal;
SDValue RetVal;
if (RetTyVT != MVT::isVoid) {
switch (RetTyVT.getSimpleVT()) {
default: assert(0 && "Unknown value type to return!");
case MVT::i1: { // bools are just like other integers (returned in r8)
// we *could* fall through to the truncate below, but this saves a
// few redundant predicate ops
SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64,InFlag);
SDValue boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64,InFlag);
InFlag = boolInR8.getValue(2);
Chain = boolInR8.getValue(1);
SDOperand zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag);
SDValue zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag);
InFlag = zeroReg.getValue(2);
Chain = zeroReg.getValue(1);
@ -546,18 +546,18 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
Chain = DAG.getCALLSEQ_END(Chain,
DAG.getConstant(NumBytes, getPointerTy()),
DAG.getConstant(0, getPointerTy()),
SDOperand());
SDValue());
return std::make_pair(RetVal, Chain);
}
SDOperand IA64TargetLowering::
LowerOperation(SDOperand Op, SelectionDAG &DAG) {
SDValue IA64TargetLowering::
LowerOperation(SDValue Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
default: assert(0 && "Should not custom lower this!");
case ISD::GlobalTLSAddress:
assert(0 && "TLS not implemented for IA64.");
case ISD::RET: {
SDOperand AR_PFSVal, Copy;
SDValue AR_PFSVal, Copy;
switch(Op.getNumOperands()) {
default:
@ -575,22 +575,22 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64);
Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), ArgReg, Op.getOperand(1),
SDOperand());
SDValue());
AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), IA64::AR_PFS, AR_PFSVal,
Copy.getValue(1));
return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other,
AR_PFSVal, AR_PFSVal.getValue(1));
}
}
return SDOperand();
return SDValue();
}
case ISD::VAARG: {
MVT VT = getPointerTy();
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1),
SDValue VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1),
SV, 0);
// Increment the pointer, VAList, to the next vaarg
SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList,
SDValue VAIncr = DAG.getNode(ISD::ADD, VT, VAList,
DAG.getConstant(VT.getSizeInBits()/8,
VT));
// Store the incremented VAList to the legalized pointer
@ -602,7 +602,7 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
case ISD::VASTART: {
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
}
@ -610,5 +610,5 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
case ISD::RETURNADDR: break;
case ISD::FRAMEADDR: break;
}
return SDOperand();
return SDValue();
}

12
lib/Target/IA64/IA64ISelLowering.h
View File

@ -49,24 +49,24 @@ namespace llvm {
const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType: return ISD::SETCC's result type.
virtual MVT getSetCCResultType(const SDOperand &) const;
virtual MVT getSetCCResultType(const SDValue &) const;
/// LowerArguments - This hook must be implemented to indicate how we should
/// lower the arguments for the specified function, into the specified DAG.
virtual void LowerArguments(Function &F, SelectionDAG &DAG,
SmallVectorImpl<SDOperand> &ArgValues);
SmallVectorImpl<SDValue> &ArgValues);
/// LowerCallTo - This hook lowers an abstract call to a function into an
/// actual call.
virtual std::pair<SDOperand, SDOperand>
LowerCallTo(SDOperand Chain, const Type *RetTy,
virtual std::pair<SDValue, SDValue>
LowerCallTo(SDValue Chain, const Type *RetTy,
bool RetSExt, bool RetZExt, bool isVarArg,
unsigned CC, bool isTailCall,
SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
SDValue Callee, ArgListTy &Args, SelectionDAG &DAG);
/// LowerOperation - for custom lowering specific ops
/// (currently, only "ret void")
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
};
}

76
lib/Target/Mips/MipsISelDAGToDAG.cpp
View File

@ -78,17 +78,17 @@ private:
// Include the pieces autogenerated from the target description.
#include "MipsGenDAGISel.inc"
SDOperand getGlobalBaseReg();
SDNode *Select(SDOperand N);
SDValue getGlobalBaseReg();
SDNode *Select(SDValue N);
// Complex Pattern.
bool SelectAddr(SDOperand Op, SDOperand N,
SDOperand &Base, SDOperand &Offset);
bool SelectAddr(SDValue Op, SDValue N,
SDValue &Base, SDValue &Offset);
// getI32Imm - Return a target constant with the specified
// value, of type i32.
inline SDOperand getI32Imm(unsigned Imm) {
inline SDValue getI32Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i32);
}
@ -124,7 +124,7 @@ InstructionSelect(SelectionDAG &SD)
/// getGlobalBaseReg - Output the instructions required to put the
/// GOT address into a register.
SDOperand MipsDAGToDAGISel::getGlobalBaseReg() {
SDValue MipsDAGToDAGISel::getGlobalBaseReg() {
MachineFunction* MF = BB->getParent();
unsigned GP = 0;
for(MachineRegisterInfo::livein_iterator ii = MF->getRegInfo().livein_begin(),
@ -141,7 +141,7 @@ SDOperand MipsDAGToDAGISel::getGlobalBaseReg() {
/// ComplexPattern used on MipsInstrInfo
/// Used on Mips Load/Store instructions
bool MipsDAGToDAGISel::
SelectAddr(SDOperand Op, SDOperand Addr, SDOperand &Offset, SDOperand &Base)
SelectAddr(SDValue Op, SDValue Addr, SDValue &Offset, SDValue &Base)
{
// if Address is FI, get the TargetFrameIndex.
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
@ -191,7 +191,7 @@ SelectAddr(SDOperand Op, SDOperand Addr, SDOperand &Offset, SDOperand &Base)
/// Select instructions not customized! Used for
/// expanded, promoted and normal instructions
SDNode* MipsDAGToDAGISel::
Select(SDOperand N)
Select(SDValue N)
{
SDNode *Node = N.Val;
unsigned Opcode = Node->getOpcode();
@ -225,7 +225,7 @@ Select(SDOperand N)
case ISD::SUBE:
case ISD::ADDE: {
SDOperand InFlag = Node->getOperand(2), CmpLHS;
SDValue InFlag = Node->getOperand(2), CmpLHS;
unsigned Opc = InFlag.getOpcode(), MOp;
assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
@ -240,20 +240,20 @@ Select(SDOperand N)
MOp = Mips::SUBu;
}
SDOperand Ops[] = { CmpLHS, InFlag.getOperand(1) };
SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
SDOperand LHS = Node->getOperand(0);
SDOperand RHS = Node->getOperand(1);
SDValue LHS = Node->getOperand(0);
SDValue RHS = Node->getOperand(1);
AddToISelQueue(LHS);
AddToISelQueue(RHS);
MVT VT = LHS.getValueType();
SDNode *Carry = CurDAG->getTargetNode(Mips::SLTu, VT, Ops, 2);
SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, VT,
SDOperand(Carry,0), RHS);
SDValue(Carry,0), RHS);
return CurDAG->SelectNodeTo(N.Val, MOp, VT, MVT::Flag,
LHS, SDOperand(AddCarry,0));
LHS, SDValue(AddCarry,0));
}
/// Mul/Div with two results
@ -261,8 +261,8 @@ Select(SDOperand N)
case ISD::UDIVREM:
case ISD::SMUL_LOHI:
case ISD::UMUL_LOHI: {
SDOperand Op1 = Node->getOperand(0);
SDOperand Op2 = Node->getOperand(1);
SDValue Op1 = Node->getOperand(0);
SDValue Op2 = Node->getOperand(1);
AddToISelQueue(Op1);
AddToISelQueue(Op2);
@ -274,17 +274,17 @@ Select(SDOperand N)
SDNode *Node = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2);
SDOperand InFlag = SDOperand(Node, 0);
SDValue InFlag = SDValue(Node, 0);
SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, MVT::i32,
MVT::Flag, InFlag);
InFlag = SDOperand(Lo,1);
InFlag = SDValue(Lo,1);
SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, MVT::i32, InFlag);
if (!N.getValue(0).use_empty())
ReplaceUses(N.getValue(0), SDOperand(Lo,0));
ReplaceUses(N.getValue(0), SDValue(Lo,0));
if (!N.getValue(1).use_empty())
ReplaceUses(N.getValue(1), SDOperand(Hi,0));
ReplaceUses(N.getValue(1), SDValue(Hi,0));
return NULL;
}
@ -293,15 +293,15 @@ Select(SDOperand N)
case ISD::MUL:
case ISD::MULHS:
case ISD::MULHU: {
SDOperand MulOp1 = Node->getOperand(0);
SDOperand MulOp2 = Node->getOperand(1);
SDValue MulOp1 = Node->getOperand(0);
SDValue MulOp2 = Node->getOperand(1);
AddToISelQueue(MulOp1);
AddToISelQueue(MulOp2);
unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
SDNode *MulNode = CurDAG->getTargetNode(MulOp, MVT::Flag, MulOp1, MulOp2);
SDOperand InFlag = SDOperand(MulNode, 0);
SDValue InFlag = SDValue(MulNode, 0);
if (MulOp == ISD::MUL)
return CurDAG->getTargetNode(Mips::MFLO, MVT::i32, InFlag);
@ -314,8 +314,8 @@ Select(SDOperand N)
case ISD::UREM:
case ISD::SDIV:
case ISD::UDIV: {
SDOperand Op1 = Node->getOperand(0);
SDOperand Op2 = Node->getOperand(1);
SDValue Op1 = Node->getOperand(0);
SDValue Op2 = Node->getOperand(1);
AddToISelQueue(Op1);
AddToISelQueue(Op2);
@ -329,13 +329,13 @@ Select(SDOperand N)
}
SDNode *Node = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2);
SDOperand InFlag = SDOperand(Node, 0);
SDValue InFlag = SDValue(Node, 0);
return CurDAG->getTargetNode(MOp, MVT::i32, InFlag);
}
// Get target GOT address.
case ISD::GLOBAL_OFFSET_TABLE: {
SDOperand Result = getGlobalBaseReg();
SDValue Result = getGlobalBaseReg();
ReplaceUses(N, Result);
return NULL;
}
@ -347,21 +347,21 @@ Select(SDOperand N)
case MipsISD::JmpLink: {
if (TM.getRelocationModel() == Reloc::PIC_) {
//bool isCodeLarge = (TM.getCodeModel() == CodeModel::Large);
SDOperand Chain = Node->getOperand(0);
SDOperand Callee = Node->getOperand(1);
SDValue Chain = Node->getOperand(0);
SDValue Callee = Node->getOperand(1);
AddToISelQueue(Chain);
SDOperand T9Reg = CurDAG->getRegister(Mips::T9, MVT::i32);
SDOperand InFlag(0, 0);
SDValue T9Reg = CurDAG->getRegister(Mips::T9, MVT::i32);
SDValue InFlag(0, 0);
if ( (isa<GlobalAddressSDNode>(Callee)) ||
(isa<ExternalSymbolSDNode>(Callee)) )
{
/// Direct call for global addresses and external symbols
SDOperand GPReg = CurDAG->getRegister(Mips::GP, MVT::i32);
SDValue GPReg = CurDAG->getRegister(Mips::GP, MVT::i32);
// Use load to get GOT target
SDOperand Ops[] = { Callee, GPReg, Chain };
SDOperand Load = SDOperand(CurDAG->getTargetNode(Mips::LW, MVT::i32,
SDValue Ops[] = { Callee, GPReg, Chain };
SDValue Load = SDValue(CurDAG->getTargetNode(Mips::LW, MVT::i32,
MVT::Other, Ops, 3), 0);
Chain = Load.getValue(1);
AddToISelQueue(Chain);
@ -377,10 +377,10 @@ Select(SDOperand N)
// Emit Jump and Link Register
SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, MVT::Other,
MVT::Flag, T9Reg, Chain);
Chain = SDOperand(ResNode, 0);
InFlag = SDOperand(ResNode, 1);
ReplaceUses(SDOperand(Node, 0), Chain);
ReplaceUses(SDOperand(Node, 1), InFlag);
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
ReplaceUses(SDValue(Node, 0), Chain);
ReplaceUses(SDValue(Node, 1), InFlag);
return ResNode;
}
}

152
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -132,13 +132,13 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
}
MVT MipsTargetLowering::getSetCCResultType(const SDOperand &) const {
MVT MipsTargetLowering::getSetCCResultType(const SDValue &) const {
return MVT::i32;
}
SDOperand MipsTargetLowering::
LowerOperation(SDOperand Op, SelectionDAG &DAG)
SDValue MipsTargetLowering::
LowerOperation(SDValue Op, SelectionDAG &DAG)
{
switch (Op.getOpcode())
{
@ -151,7 +151,7 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG)
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
}
return SDOperand();
return SDValue();
}
MachineBasicBlock *
@ -268,105 +268,105 @@ bool MipsTargetLowering::IsGlobalInSmallSection(GlobalValue *GV)
//===----------------------------------------------------------------------===//
// Misc Lower Operation implementation
//===----------------------------------------------------------------------===//
SDOperand MipsTargetLowering::
LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
SDValue MipsTargetLowering::
LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
{
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
if (!Subtarget->hasABICall()) {
if (isa<Function>(GV)) return GA;
const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
SDOperand Ops[] = { GA };
SDValue Ops[] = { GA };
if (IsGlobalInSmallSection(GV)) { // %gp_rel relocation
SDOperand GPRelNode = DAG.getNode(MipsISD::GPRel, VTs, 1, Ops, 1);
SDOperand GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, VTs, 1, Ops, 1);
SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
return DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
}
// %hi/%lo relocation
SDOperand HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
SDValue HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
return DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
} else { // Abicall relocations, TODO: make this cleaner.
SDOperand ResNode = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
SDValue ResNode = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
// On functions and global targets not internal linked only
// a load from got/GP is necessary for PIC to work.
if (!GV->hasInternalLinkage() || isa<Function>(GV))
return ResNode;
SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
return DAG.getNode(ISD::ADD, MVT::i32, ResNode, Lo);
}
assert(0 && "Dont know how to handle GlobalAddress");
return SDOperand(0,0);
return SDValue(0,0);
}
SDOperand MipsTargetLowering::
LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG)
SDValue MipsTargetLowering::
LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
{
assert(0 && "TLS not implemented for MIPS.");
return SDOperand(); // Not reached
return SDValue(); // Not reached
}
SDOperand MipsTargetLowering::
LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG)
SDValue MipsTargetLowering::
LowerSELECT_CC(SDValue Op, SelectionDAG &DAG)
{
SDOperand LHS = Op.getOperand(0);
SDOperand RHS = Op.getOperand(1);
SDOperand True = Op.getOperand(2);
SDOperand False = Op.getOperand(3);
SDOperand CC = Op.getOperand(4);
SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1);
SDValue True = Op.getOperand(2);
SDValue False = Op.getOperand(3);
SDValue CC = Op.getOperand(4);
const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
SDOperand Ops[] = { LHS, RHS, CC };
SDOperand SetCCRes = DAG.getNode(ISD::SETCC, VTs, 1, Ops, 3);
SDValue Ops[] = { LHS, RHS, CC };
SDValue SetCCRes = DAG.getNode(ISD::SETCC, VTs, 1, Ops, 3);
return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
SetCCRes, True, False);
}
SDOperand MipsTargetLowering::
LowerJumpTable(SDOperand Op, SelectionDAG &DAG)
SDValue MipsTargetLowering::
LowerJumpTable(SDValue Op, SelectionDAG &DAG)
{
SDOperand ResNode;
SDOperand HiPart;
SDValue ResNode;
SDValue HiPart;
MVT PtrVT = Op.getValueType();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
SDOperand Ops[] = { JTI };
SDValue Ops[] = { JTI };
HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
} else // Emit Load from Global Pointer
HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0);
SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
return ResNode;
}
SDOperand MipsTargetLowering::
LowerConstantPool(SDOperand Op, SelectionDAG &DAG)
SDValue MipsTargetLowering::
LowerConstantPool(SDValue Op, SelectionDAG &DAG)
{
SDOperand ResNode;
SDValue ResNode;
ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
Constant *C = N->getConstVal();
SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
// gp_rel relocation
if (!Subtarget->hasABICall() &&
IsInSmallSection(getTargetData()->getABITypeSize(C->getType()))) {
SDOperand GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
SDOperand GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
} else { // %hi/%lo relocation
SDOperand HiPart = DAG.getNode(MipsISD::Hi, MVT::i32, CP);
SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, CP);
SDValue HiPart = DAG.getNode(MipsISD::Hi, MVT::i32, CP);
SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, CP);
ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
}
@ -391,8 +391,8 @@ LowerConstantPool(SDOperand Op, SelectionDAG &DAG)
//===----------------------------------------------------------------------===//
/// Mips custom CALL implementation
SDOperand MipsTargetLowering::
LowerCALL(SDOperand Op, SelectionDAG &DAG)
SDValue MipsTargetLowering::
LowerCALL(SDValue Op, SelectionDAG &DAG)
{
unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
@ -410,13 +410,13 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG)
/// regs to (physical regs)/(stack frame), CALLSEQ_START and
/// CALLSEQ_END are emitted.
/// TODO: isVarArg, isTailCall.
SDOperand MipsTargetLowering::
LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
SDValue MipsTargetLowering::
LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, unsigned CC)
{
MachineFunction &MF = DAG.getMachineFunction();
SDOperand Chain = Op.getOperand(0);
SDOperand Callee = Op.getOperand(4);
SDValue Chain = Op.getOperand(0);
SDValue Callee = Op.getOperand(4);
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
MachineFrameInfo *MFI = MF.getFrameInfo();
@ -440,8 +440,8 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
getPointerTy()));
// With EABI is it possible to have 16 args on registers.
SmallVector<std::pair<unsigned, SDOperand>, 16> RegsToPass;
SmallVector<SDOperand, 8> MemOpChains;
SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
SmallVector<SDValue, 8> MemOpChains;
// First/LastArgStackLoc contains the first/last
// "at stack" argument location.
@ -453,7 +453,7 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
CCValAssign &VA = ArgLocs[i];
// Arguments start after the 5 first operands of ISD::CALL
SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
SDValue Arg = Op.getOperand(5+2*VA.getValNo());
// Promote the value if needed.
switch (VA.getLocInfo()) {
@ -488,7 +488,7 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
LastArgStackLoc);
SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy());
SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
// emit ISD::STORE whichs stores the
// parameter value to a stack Location
@ -505,7 +505,7 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
// chain and flag operands which copy the outgoing args into registers.
// The InFlag in necessary since all emited instructions must be
// stuck together.
SDOperand InFlag;
SDValue InFlag;
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
RegsToPass[i].second, InFlag);
@ -526,7 +526,7 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
//
// Returns a chain & a flag for retval copy to use.
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
SmallVector<SDOperand, 8> Ops;
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
@ -570,17 +570,17 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
// Reload GP value.
FI = MipsFI->getGPFI();
SDOperand FIN = DAG.getFrameIndex(FI,getPointerTy());
SDOperand GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
SDValue GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
Chain = GPLoad.getValue(1);
Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
GPLoad, SDOperand(0,0));
GPLoad, SDValue(0,0));
InFlag = Chain.getValue(1);
}
// Handle result values, copying them out of physregs into vregs that we
// return.
return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
}
/// LowerCallResult - Lower the result values of an ISD::CALL into the
@ -589,7 +589,7 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
/// being lowered. Returns a SDNode with the same number of values as the
/// ISD::CALL.
SDNode *MipsTargetLowering::
LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
LowerCallResult(SDValue Chain, SDValue InFlag, SDNode *TheCall,
unsigned CallingConv, SelectionDAG &DAG) {
bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
@ -599,7 +599,7 @@ LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
SmallVector<SDOperand, 8> ResultVals;
SmallVector<SDValue, 8> ResultVals;
// Copy all of the result registers out of their specified physreg.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
@ -621,8 +621,8 @@ LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
//===----------------------------------------------------------------------===//
/// Mips custom FORMAL_ARGUMENTS implementation
SDOperand MipsTargetLowering::
LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
SDValue MipsTargetLowering::
LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
{
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
switch(CC)
@ -638,10 +638,10 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
/// virtual registers and generate load operations for
/// arguments places on the stack.
/// TODO: isVarArg
SDOperand MipsTargetLowering::
LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
SDValue MipsTargetLowering::
LowerCCCArguments(SDValue Op, SelectionDAG &DAG)
{
SDOperand Root = Op.getOperand(0);
SDValue Root = Op.getOperand(0);
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
@ -659,8 +659,8 @@ LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
SmallVector<SDOperand, 16> ArgValues;
SDOperand StackPtr;
SmallVector<SDValue, 16> ArgValues;
SDValue StackPtr;
unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
@ -689,7 +689,7 @@ LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
// Transform the arguments stored on
// physical registers into virtual ones
unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
// If this is an 8 or 16-bit value, it is really passed promoted
// to 32 bits. Insert an assert[sz]ext to capture this, then
@ -722,7 +722,7 @@ LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
// Arguments are always 32-bit.
int FI = MFI->CreateFixedObject(4, 0);
MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
SDOperand PtrOff = DAG.getFrameIndex(FI, getPointerTy());
SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
// emit ISD::STORE whichs stores the
// parameter value to a stack Location
@ -748,7 +748,7 @@ LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
(FirstStackArgLoc + VA.getLocMemOffset())));
// Create load nodes to retrieve arguments from the stack
SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
}
}
@ -762,7 +762,7 @@ LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
MipsFI->setSRetReturnReg(Reg);
}
SDOperand Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
}
@ -777,8 +777,8 @@ LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
// Return Value Calling Convention Implementation
//===----------------------------------------------------------------------===//
SDOperand MipsTargetLowering::
LowerRET(SDOperand Op, SelectionDAG &DAG)
SDValue MipsTargetLowering::
LowerRET(SDValue Op, SelectionDAG &DAG)
{
// CCValAssign - represent the assignment of
// the return value to a location
@ -801,8 +801,8 @@ LowerRET(SDOperand Op, SelectionDAG &DAG)
}
// The chain is always operand #0
SDOperand Chain = Op.getOperand(0);
SDOperand Flag;
SDValue Chain = Op.getOperand(0);
SDValue Flag;
// Copy the result values into the output registers.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
@ -829,7 +829,7 @@ LowerRET(SDOperand Op, SelectionDAG &DAG)
if (!Reg)
assert(0 && "sret virtual register not created in the entry block");
SDOperand Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
Chain = DAG.getCopyToReg(Chain, Mips::V0, Val, Flag);
Flag = Chain.getValue(1);

26
lib/Target/Mips/MipsISelLowering.h
View File

@ -66,36 +66,36 @@ namespace llvm {
explicit MipsTargetLowering(MipsTargetMachine &TM);
/// LowerOperation - Provide custom lowering hooks for some operations.
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
/// getTargetNodeName - This method returns the name of a target specific
// DAG node.
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - get the ISD::SETCC result ValueType
MVT getSetCCResultType(const SDOperand &) const;
MVT getSetCCResultType(const SDValue &) const;
private:
// Subtarget Info
const MipsSubtarget *Subtarget;
// Lower Operand helpers
SDOperand LowerCCCArguments(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC);
SDNode *LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode*TheCall,
SDValue LowerCCCArguments(SDValue Op, SelectionDAG &DAG);
SDValue LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, unsigned CC);
SDNode *LowerCallResult(SDValue Chain, SDValue InFlag, SDNode*TheCall,
unsigned CallingConv, SelectionDAG &DAG);
bool IsGlobalInSmallSection(GlobalValue *GV);
bool IsInSmallSection(unsigned Size);
// Lower Operand specifics
SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG);
SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG);
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB);

28
lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
View File

@ -71,20 +71,20 @@ private:
// Include the pieces autogenerated from the target description.
#include "PIC16GenDAGISel.inc"
SDNode *Select(SDOperand N);
SDNode *Select(SDValue N);
// Select addressing mode. currently assume base + offset addr mode.
bool SelectAM(SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset);
bool SelectDirectAM(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Offset);
bool StoreInDirectAM(SDOperand Op, SDOperand N, SDOperand &fsr);
bool LoadFSR(SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset);
bool LoadNothing(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Offset);
bool SelectAM(SDValue Op, SDValue N, SDValue &Base, SDValue &Offset);
bool SelectDirectAM(SDValue Op, SDValue N, SDValue &Base,
SDValue &Offset);
bool StoreInDirectAM(SDValue Op, SDValue N, SDValue &fsr);
bool LoadFSR(SDValue Op, SDValue N, SDValue &Base, SDValue &Offset);
bool LoadNothing(SDValue Op, SDValue N, SDValue &Base,
SDValue &Offset);
// getI8Imm - Return a target constant with the specified
// value, of type i8.
inline SDOperand getI8Imm(unsigned Imm) {
inline SDValue getI8Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i8);
}
@ -118,7 +118,7 @@ void PIC16DAGToDAGISel::InstructionSelect(SelectionDAG &SD)
bool PIC16DAGToDAGISel::
SelectDirectAM (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset)
SelectDirectAM (SDValue Op, SDValue N, SDValue &Base, SDValue &Offset)
{
GlobalAddressSDNode *GA;
ConstantSDNode *GC;
@ -160,7 +160,7 @@ SelectDirectAM (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset)
// FIXME: must also account for preinc/predec/postinc/postdec.
bool PIC16DAGToDAGISel::
StoreInDirectAM (SDOperand Op, SDOperand N, SDOperand &fsr)
StoreInDirectAM (SDValue Op, SDValue N, SDValue &fsr)
{
RegisterSDNode *Reg;
if (N.getOpcode() == ISD::LOAD) {
@ -186,7 +186,7 @@ StoreInDirectAM (SDOperand Op, SDOperand N, SDOperand &fsr)
}
bool PIC16DAGToDAGISel::
LoadFSR (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset)
LoadFSR (SDValue Op, SDValue N, SDValue &Base, SDValue &Offset)
{
GlobalAddressSDNode *GA;
@ -207,7 +207,7 @@ LoadFSR (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset)
// LoadNothing - Don't thake this seriously, it will change.
bool PIC16DAGToDAGISel::
LoadNothing (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset)
LoadNothing (SDValue Op, SDValue N, SDValue &Base, SDValue &Offset)
{
GlobalAddressSDNode *GA;
if (N.getOpcode() == ISD::GlobalAddress) {
@ -225,7 +225,7 @@ LoadNothing (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset)
/// Select - Select instructions not customized! Used for
/// expanded, promoted and normal instructions.
SDNode* PIC16DAGToDAGISel::Select(SDOperand N)
SDNode* PIC16DAGToDAGISel::Select(SDValue N)
{
SDNode *Node = N.Val;
unsigned Opcode = Node->getOpcode();

134
lib/Target/PIC16/PIC16ISelLowering.cpp
View File

@ -159,7 +159,7 @@ PIC16TargetLowering(PIC16TargetMachine &TM): TargetLowering(TM)
}
SDOperand PIC16TargetLowering:: LowerOperation(SDOperand Op, SelectionDAG &DAG)
SDValue PIC16TargetLowering:: LowerOperation(SDValue Op, SelectionDAG &DAG)
{
SDVTList VTList16 = DAG.getVTList(MVT::i16, MVT::i16, MVT::Other);
switch (Op.getOpcode()) {
@ -195,7 +195,7 @@ SDOperand PIC16TargetLowering:: LowerOperation(SDOperand Op, SelectionDAG &DAG)
DOUT << "==== lowering BR_CC\n";
return LowerBR_CC(Op, DAG);
} // end switch.
return SDOperand();
return SDValue();
}
@ -203,21 +203,21 @@ SDOperand PIC16TargetLowering:: LowerOperation(SDOperand Op, SelectionDAG &DAG)
// Lower helper functions
//===----------------------------------------------------------------------===//
SDOperand PIC16TargetLowering::LowerBR_CC(SDOperand Op, SelectionDAG &DAG)
SDValue PIC16TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG)
{
MVT VT = Op.getValueType();
SDOperand Chain = Op.getOperand(0);
SDValue Chain = Op.getOperand(0);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
SDOperand LHS = Op.getOperand(2);
SDOperand RHS = Op.getOperand(3);
SDOperand JumpVal = Op.getOperand(4);
SDOperand Result;
SDValue LHS = Op.getOperand(2);
SDValue RHS = Op.getOperand(3);
SDValue JumpVal = Op.getOperand(4);
SDValue Result;
unsigned cmpOpcode;
unsigned branchOpcode;
SDOperand branchOperand;
SDValue branchOperand;
SDOperand StatusReg = DAG.getRegister(PIC16::STATUSREG, MVT::i8);
SDOperand CPUReg = DAG.getRegister(PIC16::WREG, MVT::i8);
SDValue StatusReg = DAG.getRegister(PIC16::STATUSREG, MVT::i8);
SDValue CPUReg = DAG.getRegister(PIC16::WREG, MVT::i8);
switch(CC) {
default:
assert(0 && "This condition code is not handled yet!!");
@ -263,7 +263,7 @@ SDOperand PIC16TargetLowering::LowerBR_CC(SDOperand Op, SelectionDAG &DAG)
} // End of Switch
SDVTList VTList = DAG.getVTList(MVT::i8, MVT::Flag);
SDOperand CmpValue = DAG.getNode(cmpOpcode, VTList, LHS, RHS).getValue(1);
SDValue CmpValue = DAG.getNode(cmpOpcode, VTList, LHS, RHS).getValue(1);
Result = DAG.getNode(branchOpcode, VT, Chain, JumpVal, branchOperand,
StatusReg, CmpValue);
return Result;
@ -276,23 +276,23 @@ SDOperand PIC16TargetLowering::LowerBR_CC(SDOperand Op, SelectionDAG &DAG)
// LowerGlobalAddress - Create a constant pool entry for global value
// and wrap it in a wrapper node.
SDOperand
PIC16TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
SDValue
PIC16TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
{
MVT PtrVT = getPointerTy();
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
GlobalValue *GV = GSDN->getGlobal();
// FIXME: for now only do the ram.
SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
SDOperand CPBank = DAG.getNode(PIC16ISD::SetBank, MVT::i8, CPAddr);
SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
SDValue CPBank = DAG.getNode(PIC16ISD::SetBank, MVT::i8, CPAddr);
CPAddr = DAG.getNode(PIC16ISD::Wrapper, MVT::i8, CPAddr,CPBank);
return CPAddr;
}
SDOperand
PIC16TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG)
SDValue
PIC16TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG)
{
switch(Op.getNumOperands()) {
default:
@ -300,12 +300,12 @@ PIC16TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG)
abort();
case 1:
return SDOperand(); // ret void is legal
return SDValue(); // ret void is legal
}
}
SDOperand
PIC16TargetLowering::LowerFrameIndex(SDOperand N, SelectionDAG &DAG)
SDValue
PIC16TargetLowering::LowerFrameIndex(SDValue N, SelectionDAG &DAG)
{
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
return DAG.getTargetFrameIndex(FIN->getIndex(), MVT::i32);
@ -314,17 +314,17 @@ PIC16TargetLowering::LowerFrameIndex(SDOperand N, SelectionDAG &DAG)
return N;
}
SDOperand
SDValue
PIC16TargetLowering::LowerLOAD(SDNode *N,
SelectionDAG &DAG,
DAGCombinerInfo &DCI) const
{
SDOperand Outs[2];
SDOperand TF; //TokenFactor
SDOperand OutChains[2];
SDOperand Chain = N->getOperand(0);
SDOperand Src = N->getOperand(1);
SDOperand retVal;
SDValue Outs[2];
SDValue TF; //TokenFactor
SDValue OutChains[2];
SDValue Chain = N->getOperand(0);
SDValue Src = N->getOperand(1);
SDValue retVal;
SDVTList VTList;
// If this load is directly stored, replace the load value with the stored
@ -332,7 +332,7 @@ PIC16TargetLowering::LowerLOAD(SDNode *N,
// FIXME: Handle store large -> read small portion.
// FIXME: Handle TRUNCSTORE/LOADEXT
LoadSDNode *LD = cast<LoadSDNode>(N);
SDOperand Ptr = LD->getBasePtr();
SDValue Ptr = LD->getBasePtr();
if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
if (ISD::isNON_TRUNCStore(Chain.Val)) {
StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
@ -343,9 +343,9 @@ PIC16TargetLowering::LowerLOAD(SDNode *N,
}
if (N->getValueType(0) != MVT::i16)
return SDOperand();
return SDValue();
SDOperand toWorklist;
SDValue toWorklist;
Outs[0] = DAG.getLoad(MVT::i8, Chain, Src, NULL, 0);
toWorklist = DAG.getNode(ISD::ADD, MVT::i16, Src,
DAG.getConstant(1, MVT::i16));
@ -367,17 +367,17 @@ PIC16TargetLowering::LowerLOAD(SDNode *N,
return retVal;
}
SDOperand
SDValue
PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
DAGCombinerInfo &DCI) const
{
bool changed = false;
int i;
SDOperand LoOps[3], HiOps[3];
SDOperand OutOps[3]; // [0]:left, [1]:right, [2]:carry
SDOperand InOp[2];
SDOperand retVal;
SDOperand as1,as2;
SDValue LoOps[3], HiOps[3];
SDValue OutOps[3]; // [0]:left, [1]:right, [2]:carry
SDValue InOp[2];
SDValue retVal;
SDValue as1,as2;
SDVTList VTList;
unsigned AS = 0, ASE = 0, ASC=0;
@ -427,7 +427,7 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
for (i = 0; i < 2; i++) {
if (InOp[i].getOpcode() == ISD::GlobalAddress) {
// We don't want to lower subs/adds with global address yet.
return SDOperand();
return SDValue();
}
else if (InOp[i].getOpcode() == ISD::Constant) {
changed = true;
@ -443,7 +443,7 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
changed = true;
// LowerLOAD returns a Package node or it may combine and return
// anything else.
SDOperand lowered = LowerLOAD(InOp[i].Val, DAG, DCI);
SDValue lowered = LowerLOAD(InOp[i].Val, DAG, DCI);
// So If LowerLOAD returns something other than Package,
// then just call ADD again.
@ -462,7 +462,7 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
changed = true;
// Must call LowerADDSUB recursively here,
// LowerADDSUB returns a Package node.
SDOperand lowered = LowerADDSUB(InOp[i].Val, DAG, DCI);
SDValue lowered = LowerADDSUB(InOp[i].Val, DAG, DCI);
LoOps[i] = lowered.getOperand(0);
HiOps[i] = lowered.getOperand(1);
@ -533,11 +533,11 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
//===----------------------------------------------------------------------===//
// FORMAL_ARGUMENTS Calling Convention Implementation
//===----------------------------------------------------------------------===//
SDOperand PIC16TargetLowering::
LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
SDValue PIC16TargetLowering::
LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
{
SmallVector<SDOperand, 8> ArgValues;
SDOperand Root = Op.getOperand(0);
SmallVector<SDValue, 8> ArgValues;
SDValue Root = Op.getOperand(0);
// Return the new list of results.
// FIXME: Just copy right now.
@ -560,7 +560,7 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
// Target Optimization Hooks
//===----------------------------------------------------------------------===//
SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
SDValue PIC16TargetLowering::PerformDAGCombine(SDNode *N,
DAGCombinerInfo &DCI) const
{
int i;
@ -573,14 +573,14 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
case PIC16ISD::Package:
DOUT << "==== combining PIC16ISD::Package\n";
return SDOperand();
return SDValue();
case ISD::ADD:
case ISD::SUB:
if ((N->getOperand(0).getOpcode() == ISD::GlobalAddress) ||
(N->getOperand(0).getOpcode() == ISD::FrameIndex)) {
// Do not touch pointer adds.
return SDOperand ();
return SDValue ();
}
break;
@ -589,11 +589,11 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
case ISD::SUBE :
case ISD::SUBC :
if (N->getValueType(0) == MVT::i16) {
SDOperand retVal = LowerADDSUB(N, DAG,DCI);
SDValue retVal = LowerADDSUB(N, DAG,DCI);
// LowerADDSUB has already combined the result,
// so we just return nothing to avoid assertion failure from llvm
// if N has been deleted already.
return SDOperand();
return SDValue();
}
else if (N->getValueType(0) == MVT::i8) {
// Sanity check ....
@ -609,12 +609,12 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
// FIXME: split this large chunk of code.
case ISD::STORE :
{
SDOperand Chain = N->getOperand(0);
SDOperand Src = N->getOperand(1);
SDOperand Dest = N->getOperand(2);
SDValue Chain = N->getOperand(0);
SDValue Src = N->getOperand(1);
SDValue Dest = N->getOperand(2);
unsigned int DstOff = 0;
int NUM_STORES = 0;
SDOperand Stores[6];
SDValue Stores[6];
// if source operand is expected to be extended to
// some higher type then - remove this extension
@ -652,10 +652,10 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
//create direct addressing a = b
Chain = Src.getOperand(0);
for (i=0; i<NUM_STORES; i++) {
SDOperand ADN = DAG.getNode(ISD::ADD, MVT::i16, Src.getOperand(1),
SDValue ADN = DAG.getNode(ISD::ADD, MVT::i16, Src.getOperand(1),
DAG.getConstant(DstOff, MVT::i16));
SDOperand LDN = DAG.getLoad(MVT::i8, Chain, ADN, NULL, 0);
SDOperand DSTADDR = DAG.getNode(ISD::ADD, MVT::i16, Dest,
SDValue LDN = DAG.getLoad(MVT::i8, Chain, ADN, NULL, 0);
SDValue DSTADDR = DAG.getNode(ISD::ADD, MVT::i16, Dest,
DAG.getConstant(DstOff, MVT::i16));
Stores[i] = DAG.getStore(Chain, LDN, DSTADDR, NULL, 0);
Chain = Stores[i];
@ -670,8 +670,8 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
//create direct addressing a = CONST
CST = dyn_cast<ConstantSDNode>(Src);
for (i = 0; i < NUM_STORES; i++) {
SDOperand CNST = DAG.getConstant(CST->getValue() >> i*8, MVT::i8);
SDOperand ADN = DAG.getNode(ISD::ADD, MVT::i16, Dest,
SDValue CNST = DAG.getConstant(CST->getValue() >> i*8, MVT::i8);
SDValue ADN = DAG.getNode(ISD::ADD, MVT::i16, Dest,
DAG.getConstant(DstOff, MVT::i16));
Stores[i] = DAG.getStore(Chain, CNST, ADN, NULL, 0);
Chain = Stores[i];
@ -686,11 +686,11 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
// Create indirect addressing.
CST = dyn_cast<ConstantSDNode>(Src);
Chain = Dest.getOperand(0);
SDOperand Load;
SDValue Load;
Load = DAG.getLoad(MVT::i16, Chain,Dest.getOperand(1), NULL, 0);
Chain = Load.getValue(1);
for (i=0; i<NUM_STORES; i++) {
SDOperand CNST = DAG.getConstant(CST->getValue() >> i*8, MVT::i8);
SDValue CNST = DAG.getConstant(CST->getValue() >> i*8, MVT::i8);
Stores[i] = DAG.getStore(Chain, CNST, Load, NULL, 0);
Chain = Stores[i];
DstOff += 1;
@ -701,11 +701,11 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
}
else if (isa<LoadSDNode>(Dest) && isa<GlobalAddressSDNode>(Src)) {
// GlobalAddressSDNode *GAD = dyn_cast<GlobalAddressSDNode>(Src);
return SDOperand();
return SDValue();
}
else if (Src.getOpcode() == PIC16ISD::Package) {
StoreSDNode *st = dyn_cast<StoreSDNode>(N);
SDOperand toWorkList, retVal;
SDValue toWorkList, retVal;
Chain = N->getOperand(0);
if (st->isTruncatingStore()) {
@ -739,7 +739,7 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
case ISD::LOAD :
{
SDOperand Ptr = N->getOperand(1);
SDValue Ptr = N->getOperand(1);
if (Ptr.getOpcode() == PIC16ISD::Package) {
assert (0 && "not implemented yet");
}
@ -747,20 +747,20 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
break;
} // end switch.
return SDOperand();
return SDValue();
}
//===----------------------------------------------------------------------===//
// Utility functions
//===----------------------------------------------------------------------===//
const SDOperand *PIC16TargetLowering::
findLoadi8(const SDOperand &Src, SelectionDAG &DAG) const
const SDValue *PIC16TargetLowering::
findLoadi8(const SDValue &Src, SelectionDAG &DAG) const
{
unsigned int i;
if ((Src.getOpcode() == ISD::LOAD) && (Src.getValueType() == MVT::i8))
return &Src;
for (i=0; i<Src.getNumOperands(); i++) {
const SDOperand *retVal = findLoadi8(Src.getOperand(i),DAG);
const SDValue *retVal = findLoadi8(Src.getOperand(i),DAG);
if (retVal) return retVal;
}

22
lib/Target/PIC16/PIC16ISelLowering.h
View File

@ -64,28 +64,28 @@ namespace llvm {
explicit PIC16TargetLowering(PIC16TargetMachine &TM);
/// LowerOperation - Provide custom lowering hooks for some operations.
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerFrameIndex(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG);
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG);
SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG);
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG);
SDOperand RemoveHiLo(SDNode *, SelectionDAG &DAG,
SDValue RemoveHiLo(SDNode *, SelectionDAG &DAG,
DAGCombinerInfo &DCI) const;
SDOperand LowerADDSUB(SDNode *, SelectionDAG &DAG,
SDValue LowerADDSUB(SDNode *, SelectionDAG &DAG,
DAGCombinerInfo &DCI) const;
SDOperand LowerLOAD(SDNode *, SelectionDAG &DAG,
SDValue LowerLOAD(SDNode *, SelectionDAG &DAG,
DAGCombinerInfo &DCI) const;
/// getTargetNodeName - This method returns the name of a target specific
// DAG node.
virtual const char *getTargetNodeName(unsigned Opcode) const;
virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
// utility function.
const SDOperand *findLoadi8(const SDOperand &Src, SelectionDAG &DAG) const;
const SDValue *findLoadi8(const SDValue &Src, SelectionDAG &DAG) const;
};
} // namespace llvm

2
lib/Target/PowerPC/PPCHazardRecognizers.cpp
View File

@ -86,7 +86,7 @@ PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
/// isLoadOfStoredAddress - If we have a load from the previously stored pointer
/// as indicated by StorePtr1/StorePtr2/StoreSize, return true.
bool PPCHazardRecognizer970::
isLoadOfStoredAddress(unsigned LoadSize, SDOperand Ptr1, SDOperand Ptr2) const {
isLoadOfStoredAddress(unsigned LoadSize, SDValue Ptr1, SDValue Ptr2) const {
for (unsigned i = 0, e = NumStores; i != e; ++i) {
// Handle exact and commuted addresses.
if (Ptr1 == StorePtr1[i] && Ptr2 == StorePtr2[i])

4
lib/Target/PowerPC/PPCHazardRecognizers.h
View File

@ -41,7 +41,7 @@ class PPCHazardRecognizer970 : public HazardRecognizer {
//
// This is null if we haven't seen a store yet. We keep track of both
// operands of the store here, since we support [r+r] and [r+i] addressing.
SDOperand StorePtr1[4], StorePtr2[4];
SDValue StorePtr1[4], StorePtr2[4];
unsigned StoreSize[4];
unsigned NumStores;
@ -64,7 +64,7 @@ private:
bool &isLoad, bool &isStore);
bool isLoadOfStoredAddress(unsigned LoadSize,
SDOperand Ptr1, SDOperand Ptr2) const;
SDValue Ptr1, SDValue Ptr2) const;
};
} // end namespace llvm

216
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -61,18 +61,18 @@ namespace {
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
inline SDOperand getI32Imm(unsigned Imm) {
inline SDValue getI32Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i32);
}
/// getI64Imm - Return a target constant with the specified value, of type
/// i64.
inline SDOperand getI64Imm(uint64_t Imm) {
inline SDValue getI64Imm(uint64_t Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i64);
}
/// getSmallIPtrImm - Return a target constant of pointer type.
inline SDOperand getSmallIPtrImm(unsigned Imm) {
inline SDValue getSmallIPtrImm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
}
@ -94,25 +94,25 @@ namespace {
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
SDNode *Select(SDOperand Op);
SDNode *Select(SDValue Op);
SDNode *SelectBitfieldInsert(SDNode *N);
/// SelectCC - Select a comparison of the specified values with the
/// specified condition code, returning the CR# of the expression.
SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC);
/// SelectAddrImm - Returns true if the address N can be represented by
/// a base register plus a signed 16-bit displacement [r+imm].
bool SelectAddrImm(SDOperand Op, SDOperand N, SDOperand &Disp,
SDOperand &Base) {
bool SelectAddrImm(SDValue Op, SDValue N, SDValue &Disp,
SDValue &Base) {
return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
}
/// SelectAddrImmOffs - Return true if the operand is valid for a preinc
/// immediate field. Because preinc imms have already been validated, just
/// accept it.
bool SelectAddrImmOffs(SDOperand Op, SDOperand N, SDOperand &Out) const {
bool SelectAddrImmOffs(SDValue Op, SDValue N, SDValue &Out) const {
Out = N;
return true;
}
@ -120,33 +120,33 @@ namespace {
/// SelectAddrIdx - Given the specified addressed, check to see if it can be
/// represented as an indexed [r+r] operation. Returns false if it can
/// be represented by [r+imm], which are preferred.
bool SelectAddrIdx(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Index) {
bool SelectAddrIdx(SDValue Op, SDValue N, SDValue &Base,
SDValue &Index) {
return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
}
/// SelectAddrIdxOnly - Given the specified addressed, force it to be
/// represented as an indexed [r+r] operation.
bool SelectAddrIdxOnly(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Index) {
bool SelectAddrIdxOnly(SDValue Op, SDValue N, SDValue &Base,
SDValue &Index) {
return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
}
/// SelectAddrImmShift - Returns true if the address N can be represented by
/// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
/// for use by STD and friends.
bool SelectAddrImmShift(SDOperand Op, SDOperand N, SDOperand &Disp,
SDOperand &Base) {
bool SelectAddrImmShift(SDValue Op, SDValue N, SDValue &Disp,
SDValue &Base) {
return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG);
}
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
std::vector<SDOperand> &OutOps,
std::vector<SDValue> &OutOps,
SelectionDAG &DAG) {
SDOperand Op0, Op1;
SDValue Op0, Op1;
switch (ConstraintCode) {
default: return true;
case 'm': // memory
@ -170,8 +170,8 @@ namespace {
return false;
}
SDOperand BuildSDIVSequence(SDNode *N);
SDOperand BuildUDIVSequence(SDNode *N);
SDValue BuildSDIVSequence(SDNode *N);
SDValue BuildUDIVSequence(SDNode *N);
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
@ -197,7 +197,7 @@ namespace {
#include "PPCGenDAGISel.inc"
private:
SDNode *SelectSETCC(SDOperand Op);
SDNode *SelectSETCC(SDValue Op);
};
}
@ -313,7 +313,7 @@ static bool isIntS16Immediate(SDNode *N, short &Imm) {
return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
}
static bool isIntS16Immediate(SDOperand Op, short &Imm) {
static bool isIntS16Immediate(SDValue Op, short &Imm) {
return isIntS16Immediate(Op.Val, Imm);
}
@ -340,7 +340,7 @@ static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
// isInt32Immediate - This method tests to see if a constant operand.
// If so Imm will receive the 32 bit value.
static bool isInt32Immediate(SDOperand N, unsigned &Imm) {
static bool isInt32Immediate(SDValue N, unsigned &Imm) {
return isInt32Immediate(N.Val, Imm);
}
@ -418,8 +418,8 @@ bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
/// SelectBitfieldInsert - turn an or of two masked values into
/// the rotate left word immediate then mask insert (rlwimi) instruction.
SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
SDOperand Op0 = N->getOperand(0);
SDOperand Op1 = N->getOperand(1);
SDValue Op0 = N->getOperand(0);
SDValue Op1 = N->getOperand(1);
APInt LKZ, LKO, RKZ, RKO;
CurDAG->ComputeMaskedBits(Op0, APInt::getAllOnesValue(32), LKZ, LKO);
@ -458,7 +458,7 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
unsigned MB, ME;
if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
SDOperand Tmp1, Tmp2, Tmp3;
SDValue Tmp1, Tmp2, Tmp3;
bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF;
if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
@ -481,7 +481,7 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
AddToISelQueue(Tmp3);
AddToISelQueue(Op1);
SH &= 31;
SDOperand Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB),
SDValue Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB),
getI32Imm(ME) };
return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
}
@ -491,7 +491,7 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
/// SelectCC - Select a comparison of the specified values with the specified
/// condition code, returning the CR# of the expression.
SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
ISD::CondCode CC) {
// Always select the LHS.
AddToISelQueue(LHS);
@ -503,11 +503,11 @@ SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
if (isInt32Immediate(RHS, Imm)) {
// SETEQ/SETNE comparison with 16-bit immediate, fold it.
if (isUInt16(Imm))
return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
// If this is a 16-bit signed immediate, fold it.
if (isInt16((int)Imm))
return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
return SDValue(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
// For non-equality comparisons, the default code would materialize the
@ -519,21 +519,21 @@ SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
// xoris r0,r3,0x1234
// cmplwi cr0,r0,0x5678
// beq cr0,L6
SDOperand Xor(CurDAG->getTargetNode(PPC::XORIS, MVT::i32, LHS,
SDValue Xor(CurDAG->getTargetNode(PPC::XORIS, MVT::i32, LHS,
getI32Imm(Imm >> 16)), 0);
return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, Xor,
return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, Xor,
getI32Imm(Imm & 0xFFFF)), 0);
}
Opc = PPC::CMPLW;
} else if (ISD::isUnsignedIntSetCC(CC)) {
if (isInt32Immediate(RHS, Imm) && isUInt16(Imm))
return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
Opc = PPC::CMPLW;
} else {
short SImm;
if (isIntS16Immediate(RHS, SImm))
return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
return SDValue(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
getI32Imm((int)SImm & 0xFFFF)),
0);
Opc = PPC::CMPW;
@ -544,11 +544,11 @@ SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
if (isInt64Immediate(RHS.Val, Imm)) {
// SETEQ/SETNE comparison with 16-bit immediate, fold it.
if (isUInt16(Imm))
return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
// If this is a 16-bit signed immediate, fold it.
if (isInt16(Imm))
return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
return SDValue(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
// For non-equality comparisons, the default code would materialize the
@ -561,22 +561,22 @@ SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
// cmpldi cr0,r0,0x5678
// beq cr0,L6
if (isUInt32(Imm)) {
SDOperand Xor(CurDAG->getTargetNode(PPC::XORIS8, MVT::i64, LHS,
SDValue Xor(CurDAG->getTargetNode(PPC::XORIS8, MVT::i64, LHS,
getI64Imm(Imm >> 16)), 0);
return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, Xor,
return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, Xor,
getI64Imm(Imm & 0xFFFF)), 0);
}
}
Opc = PPC::CMPLD;
} else if (ISD::isUnsignedIntSetCC(CC)) {
if (isInt64Immediate(RHS.Val, Imm) && isUInt16(Imm))
return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
getI64Imm(Imm & 0xFFFF)), 0);
Opc = PPC::CMPLD;
} else {
short SImm;
if (isIntS16Immediate(RHS, SImm))
return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
return SDValue(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
getI64Imm(SImm & 0xFFFF)),
0);
Opc = PPC::CMPD;
@ -588,7 +588,7 @@ SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
Opc = PPC::FCMPUD;
}
AddToISelQueue(RHS);
return SDOperand(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0);
return SDValue(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0);
}
static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
@ -653,7 +653,7 @@ static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) {
return 0;
}
SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) {
SDNode *N = Op.Val;
unsigned Imm;
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
@ -662,64 +662,64 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
// Check for those cases here.
// setcc op, 0
if (Imm == 0) {
SDOperand Op = N->getOperand(0);
SDValue Op = N->getOperand(0);
AddToISelQueue(Op);
switch (CC) {
default: break;
case ISD::SETEQ: {
Op = SDOperand(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0);
SDOperand Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
Op = SDValue(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0);
SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
case ISD::SETNE: {
SDOperand AD =
SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
SDValue AD =
SDValue(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
Op, getI32Imm(~0U)), 0);
return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
AD.getValue(1));
}
case ISD::SETLT: {
SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
case ISD::SETGT: {
SDOperand T =
SDOperand(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0);
T = SDOperand(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0);
SDOperand Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
SDValue T =
SDValue(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0);
T = SDValue(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0);
SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
}
} else if (Imm == ~0U) { // setcc op, -1
SDOperand Op = N->getOperand(0);
SDValue Op = N->getOperand(0);
AddToISelQueue(Op);
switch (CC) {
default: break;
case ISD::SETEQ:
Op = SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
Op = SDValue(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
Op, getI32Imm(1)), 0);
return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
SDOperand(CurDAG->getTargetNode(PPC::LI, MVT::i32,
SDValue(CurDAG->getTargetNode(PPC::LI, MVT::i32,
getI32Imm(0)), 0),
Op.getValue(1));
case ISD::SETNE: {
Op = SDOperand(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0);
Op = SDValue(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0);
SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
Op, getI32Imm(~0U));
return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDOperand(AD, 0),
Op, SDOperand(AD, 1));
return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
Op, SDValue(AD, 1));
}
case ISD::SETLT: {
SDOperand AD = SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
SDValue AD = SDValue(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
getI32Imm(1)), 0);
SDOperand AN = SDOperand(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD,
SDValue AN = SDValue(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD,
Op), 0);
SDOperand Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
case ISD::SETGT: {
SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
Op = SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
getI32Imm(1));
}
@ -730,30 +730,30 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
bool Inv;
int OtherCondIdx;
unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx);
SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
SDOperand IntCR;
SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
SDValue IntCR;
// Force the ccreg into CR7.
SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
SDOperand InFlag(0, 0); // Null incoming flag value.
SDValue InFlag(0, 0); // Null incoming flag value.
CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg,
InFlag).getValue(1);
if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1)
IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg,
IntCR = SDValue(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg,
CCReg), 0);
else
IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0);
IntCR = SDValue(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0);
SDOperand Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
getI32Imm(31), getI32Imm(31) };
if (OtherCondIdx == -1 && !Inv)
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
// Get the specified bit.
SDOperand Tmp =
SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
SDValue Tmp =
SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
if (Inv) {
assert(OtherCondIdx == -1 && "Can't have split plus negation");
return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
@ -764,8 +764,8 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
// Get the other bit of the comparison.
Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31);
SDOperand OtherCond =
SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
SDValue OtherCond =
SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond);
}
@ -773,7 +773,7 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.Val;
if (N->isMachineOpcode())
return NULL; // Already selected.
@ -824,7 +824,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
Result = CurDAG->getTargetNode(OpC, MVT::i64, getI32Imm(Hi));
// And Lo bits.
Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64,
SDOperand(Result, 0), getI32Imm(Lo));
SDValue(Result, 0), getI32Imm(Lo));
} else {
// Just the Hi bits.
Result = CurDAG->getTargetNode(PPC::LIS8, MVT::i64, getI32Imm(Hi));
@ -836,18 +836,18 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
// Shift for next step if the upper 32-bits were not zero.
if (Imm) {
Result = CurDAG->getTargetNode(PPC::RLDICR, MVT::i64,
SDOperand(Result, 0),
SDValue(Result, 0),
getI32Imm(Shift), getI32Imm(63 - Shift));
}
// Add in the last bits as required.
if ((Hi = (Remainder >> 16) & 0xFFFF)) {
Result = CurDAG->getTargetNode(PPC::ORIS8, MVT::i64,
SDOperand(Result, 0), getI32Imm(Hi));
SDValue(Result, 0), getI32Imm(Hi));
}
if ((Lo = Remainder & 0xFFFF)) {
Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64,
SDOperand(Result, 0), getI32Imm(Lo));
SDValue(Result, 0), getI32Imm(Lo));
}
return Result;
@ -862,7 +862,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
SDOperand TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
SDValue TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
if (N->hasOneUse())
return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI,
@ -872,7 +872,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
}
case PPCISD::MFCR: {
SDOperand InFlag = N->getOperand(1);
SDValue InFlag = N->getOperand(1);
AddToISelQueue(InFlag);
// Use MFOCRF if supported.
if (PPCSubTarget.isGigaProcessor())
@ -890,21 +890,21 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
// sra/addze rather than having to handle sdiv ourselves. oh well.
unsigned Imm;
if (isInt32Immediate(N->getOperand(1), Imm)) {
SDOperand N0 = N->getOperand(0);
SDValue N0 = N->getOperand(0);
AddToISelQueue(N0);
if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
SDNode *Op =
CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
N0, getI32Imm(Log2_32(Imm)));
return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
SDOperand(Op, 0), SDOperand(Op, 1));
SDValue(Op, 0), SDValue(Op, 1));
} else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
SDNode *Op =
CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
N0, getI32Imm(Log2_32(-Imm)));
SDOperand PT =
SDOperand(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32,
SDOperand(Op, 0), SDOperand(Op, 1)),
SDValue PT =
SDValue(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32,
SDValue(Op, 0), SDValue(Op, 1)),
0);
return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
}
@ -923,7 +923,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
if (LD->getAddressingMode() != ISD::PRE_INC)
break;
SDOperand Offset = LD->getOffset();
SDValue Offset = LD->getOffset();
if (isa<ConstantSDNode>(Offset) ||
Offset.getOpcode() == ISD::TargetGlobalAddress) {
@ -954,12 +954,12 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
}
}
SDOperand Chain = LD->getChain();
SDOperand Base = LD->getBasePtr();
SDValue Chain = LD->getChain();
SDValue Base = LD->getBasePtr();
AddToISelQueue(Chain);
AddToISelQueue(Base);
AddToISelQueue(Offset);
SDOperand Ops[] = { Offset, Base, Chain };
SDValue Ops[] = { Offset, Base, Chain };
// FIXME: PPC64
return CurDAG->getTargetNode(Opcode, LD->getValueType(0),
PPCLowering.getPointerTy(),
@ -976,9 +976,9 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
// with a mask, emit rlwinm
if (isInt32Immediate(N->getOperand(1), Imm) &&
isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
SDOperand Val = N->getOperand(0).getOperand(0);
SDValue Val = N->getOperand(0).getOperand(0);
AddToISelQueue(Val);
SDOperand Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
// If this is just a masked value where the input is not handled above, and
@ -986,15 +986,15 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
if (isInt32Immediate(N->getOperand(1), Imm) &&
isRunOfOnes(Imm, MB, ME) &&
N->getOperand(0).getOpcode() != ISD::ROTL) {
SDOperand Val = N->getOperand(0);
SDValue Val = N->getOperand(0);
AddToISelQueue(Val);
SDOperand Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
// AND X, 0 -> 0, not "rlwinm 32".
if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
AddToISelQueue(N->getOperand(1));
ReplaceUses(SDOperand(N, 0), N->getOperand(1));
ReplaceUses(SDValue(N, 0), N->getOperand(1));
return NULL;
}
// ISD::OR doesn't get all the bitfield insertion fun.
@ -1007,7 +1007,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
if (isRunOfOnes(Imm, MB, ME)) {
AddToISelQueue(N->getOperand(0).getOperand(0));
AddToISelQueue(N->getOperand(0).getOperand(1));
SDOperand Ops[] = { N->getOperand(0).getOperand(0),
SDValue Ops[] = { N->getOperand(0).getOperand(0),
N->getOperand(0).getOperand(1),
getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
@ -1029,7 +1029,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
isRotateAndMask(N, Imm, true, SH, MB, ME)) {
AddToISelQueue(N->getOperand(0).getOperand(0));
SDOperand Ops[] = { N->getOperand(0).getOperand(0),
SDValue Ops[] = { N->getOperand(0).getOperand(0),
getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
@ -1042,7 +1042,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
isRotateAndMask(N, Imm, true, SH, MB, ME)) {
AddToISelQueue(N->getOperand(0).getOperand(0));
SDOperand Ops[] = { N->getOperand(0).getOperand(0),
SDValue Ops[] = { N->getOperand(0).getOperand(0),
getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
@ -1066,11 +1066,11 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
N->getOperand(0), getI32Imm(~0U));
return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
SDOperand(Tmp, 0), N->getOperand(0),
SDOperand(Tmp, 1));
SDValue(Tmp, 0), N->getOperand(0),
SDValue(Tmp, 1));
}
SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
unsigned BROpc = getPredicateForSetCC(CC);
unsigned SelectCCOp;
@ -1087,7 +1087,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
AddToISelQueue(N->getOperand(2));
AddToISelQueue(N->getOperand(3));
SDOperand Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
getI32Imm(BROpc) };
return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
}
@ -1098,28 +1098,28 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
// Op #3 is the Dest MBB
AddToISelQueue(N->getOperand(4)); // Op #4 is the Flag.
// Prevent PPC::PRED_* from being selected into LI.
SDOperand Pred =
SDValue Pred =
getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getValue());
SDOperand Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
N->getOperand(0), N->getOperand(4) };
return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
}
case ISD::BR_CC: {
AddToISelQueue(N->getOperand(0));
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
SDOperand Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
N->getOperand(4), N->getOperand(0) };
return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
}
case ISD::BRIND: {
// FIXME: Should custom lower this.
SDOperand Chain = N->getOperand(0);
SDOperand Target = N->getOperand(1);
SDValue Chain = N->getOperand(0);
SDValue Target = N->getOperand(1);
AddToISelQueue(Chain);
AddToISelQueue(Target);
unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Target,
Chain = SDValue(CurDAG->getTargetNode(Opc, MVT::Other, Target,
Chain), 0);
return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
}

746
lib/Target/PowerPC/PPCISelLowering.cpp
View File

File diff suppressed because it is too large Load Diff

102
lib/Target/PowerPC/PPCISelLowering.h
View File

@ -215,7 +215,7 @@ namespace llvm {
/// formed by using a vspltis[bhw] instruction of the specified element
/// size, return the constant being splatted. The ByteSize field indicates
/// the number of bytes of each element [124] -> [bhw].
SDOperand get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
}
class PPCTargetLowering : public TargetLowering {
@ -236,49 +236,49 @@ namespace llvm {
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - Return the ISD::SETCC ValueType
virtual MVT getSetCCResultType(const SDOperand &) const;
virtual MVT getSetCCResultType(const SDValue &) const;
/// getPreIndexedAddressParts - returns true by value, base pointer and
/// offset pointer and addressing mode by reference if the node's address
/// can be legally represented as pre-indexed load / store address.
virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
SDOperand &Offset,
virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
SDValue &Offset,
ISD::MemIndexedMode &AM,
SelectionDAG &DAG);
/// SelectAddressRegReg - Given the specified addressed, check to see if it
/// can be represented as an indexed [r+r] operation. Returns false if it
/// can be more efficiently represented with [r+imm].
bool SelectAddressRegReg(SDOperand N, SDOperand &Base, SDOperand &Index,
bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
SelectionDAG &DAG);
/// SelectAddressRegImm - Returns true if the address N can be represented
/// by a base register plus a signed 16-bit displacement [r+imm], and if it
/// is not better represented as reg+reg.
bool SelectAddressRegImm(SDOperand N, SDOperand &Disp, SDOperand &Base,
bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
SelectionDAG &DAG);
/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
/// represented as an indexed [r+r] operation.
bool SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, SDOperand &Index,
bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
SelectionDAG &DAG);
/// SelectAddressRegImmShift - Returns true if the address N can be
/// represented by a base register plus a signed 14-bit displacement
/// [r+imm*4]. Suitable for use by STD and friends.
bool SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, SDOperand &Base,
bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base,
SelectionDAG &DAG);
/// LowerOperation - Provide custom lowering hooks for some operations.
///
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
virtual SDNode *ReplaceNodeResults(SDNode *N, SelectionDAG &DAG);
virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
virtual void computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
APInt &KnownZero,
APInt &KnownOne,
@ -300,9 +300,9 @@ namespace llvm {
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops.
virtual void LowerAsmOperandForConstraint(SDOperand Op,
virtual void LowerAsmOperandForConstraint(SDValue Op,
char ConstraintLetter,
std::vector<SDOperand> &Ops,
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const;
/// isLegalAddressingMode - Return true if the addressing mode represented
@ -321,63 +321,63 @@ namespace llvm {
/// IsEligibleForTailCallOptimization - Check whether the call is eligible
/// for tail call optimization. Target which want to do tail call
/// optimization should implement this function.
virtual bool IsEligibleForTailCallOptimization(SDOperand Call,
SDOperand Ret,
virtual bool IsEligibleForTailCallOptimization(SDValue Call,
SDValue Ret,
SelectionDAG &DAG) const;
private:
SDOperand getFramePointerFrameIndex(SelectionDAG & DAG) const;
SDOperand getReturnAddrFrameIndex(SelectionDAG & DAG) const;
SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
SDOperand EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
int SPDiff,
SDOperand Chain,
SDOperand &LROpOut,
SDOperand &FPOpOut);
SDValue Chain,
SDValue &LROpOut,
SDValue &FPOpOut);
SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG);
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
int VarArgsFrameIndex, int VarArgsStackOffset,
unsigned VarArgsNumGPR, unsigned VarArgsNumFPR,
const PPCSubtarget &Subtarget);
SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG, int VarArgsFrameIndex,
SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, int VarArgsFrameIndex,
int VarArgsStackOffset, unsigned VarArgsNumGPR,
unsigned VarArgsNumFPR, const PPCSubtarget &Subtarget);
SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG,
int &VarArgsFrameIndex,
int &VarArgsStackOffset,
unsigned &VarArgsNumGPR,
unsigned &VarArgsNumFPR,
const PPCSubtarget &Subtarget);
SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
SDValue LowerCALL(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget, TargetMachine &TM);
SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM);
SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,
SDValue LowerRET(SDValue Op, SelectionDAG &DAG, TargetMachine &TM);
SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget);
SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG,
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget);
SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerAtomicLOAD_ADD(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerAtomicCMP_SWAP(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerAtomicSWAP(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerFP_ROUND_INREG(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG);
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
SDValue LowerAtomicLOAD_ADD(SDValue Op, SelectionDAG &DAG);
SDValue LowerAtomicCMP_SWAP(SDValue Op, SelectionDAG &DAG);
SDValue LowerAtomicSWAP(SDValue Op, SelectionDAG &DAG);
SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG);
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG);
SDValue LowerFP_ROUND_INREG(SDValue Op, SelectionDAG &DAG);
SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG);
SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG);
SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG);
SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG);
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG);
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG);
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG);
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG);
};
}

34
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -40,12 +40,12 @@ public:
Subtarget(TM.getSubtarget<SparcSubtarget>()) {
}
SDNode *Select(SDOperand Op);
SDNode *Select(SDValue Op);
// Complex Pattern Selectors.
bool SelectADDRrr(SDOperand Op, SDOperand N, SDOperand &R1, SDOperand &R2);
bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Offset);
bool SelectADDRrr(SDValue Op, SDValue N, SDValue &R1, SDValue &R2);
bool SelectADDRri(SDValue Op, SDValue N, SDValue &Base,
SDValue &Offset);
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
@ -70,8 +70,8 @@ void SparcDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
DAG.RemoveDeadNodes();
}
bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr,
SDOperand &Base, SDOperand &Offset) {
bool SparcDAGToDAGISel::SelectADDRri(SDValue Op, SDValue Addr,
SDValue &Base, SDValue &Offset) {
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
Offset = CurDAG->getTargetConstant(0, MVT::i32);
@ -111,8 +111,8 @@ bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr,
return true;
}
bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr,
SDOperand &R1, SDOperand &R2) {
bool SparcDAGToDAGISel::SelectADDRrr(SDValue Op, SDValue Addr,
SDValue &R1, SDValue &R2) {
if (Addr.getOpcode() == ISD::FrameIndex) return false;
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress)
@ -135,7 +135,7 @@ bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr,
return true;
}
SDNode *SparcDAGToDAGISel::Select(SDOperand Op) {
SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.Val;
if (N->isMachineOpcode())
return NULL; // Already selected.
@ -145,20 +145,20 @@ SDNode *SparcDAGToDAGISel::Select(SDOperand Op) {
case ISD::SDIV:
case ISD::UDIV: {
// FIXME: should use a custom expander to expose the SRA to the dag.
SDOperand DivLHS = N->getOperand(0);
SDOperand DivRHS = N->getOperand(1);
SDValue DivLHS = N->getOperand(0);
SDValue DivRHS = N->getOperand(1);
AddToISelQueue(DivLHS);
AddToISelQueue(DivRHS);
// Set the Y register to the high-part.
SDOperand TopPart;
SDValue TopPart;
if (N->getOpcode() == ISD::SDIV) {
TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
TopPart = SDValue(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
CurDAG->getTargetConstant(31, MVT::i32)), 0);
} else {
TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
}
TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
TopPart = SDValue(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
CurDAG->getRegister(SP::G0, MVT::i32)), 0);
// FIXME: Handle div by immediate.
@ -169,15 +169,15 @@ SDNode *SparcDAGToDAGISel::Select(SDOperand Op) {
case ISD::MULHU:
case ISD::MULHS: {
// FIXME: Handle mul by immediate.
SDOperand MulLHS = N->getOperand(0);
SDOperand MulRHS = N->getOperand(1);
SDValue MulLHS = N->getOperand(0);
SDValue MulRHS = N->getOperand(1);
AddToISelQueue(MulLHS);
AddToISelQueue(MulRHS);
unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
MulLHS, MulRHS);
// The high part is in the Y register.
return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
return NULL;
}
}

168
lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -30,7 +30,7 @@ using namespace llvm;
#include "SparcGenCallingConv.inc"
static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
// CCValAssign - represent the assignment of the return value to locations.
SmallVector<CCValAssign, 16> RVLocs;
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
@ -50,8 +50,8 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
}
SDOperand Chain = Op.getOperand(0);
SDOperand Flag;
SDValue Chain = Op.getOperand(0);
SDValue Flag;
// Copy the result values into the output registers.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
@ -76,7 +76,7 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
/// in FP registers for fastcc functions.
void
SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
SmallVectorImpl<SDOperand> &ArgValues) {
SmallVectorImpl<SDValue> &ArgValues) {
MachineFunction &MF = DAG.getMachineFunction();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
@ -87,8 +87,8 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
unsigned ArgOffset = 68;
SDOperand Root = DAG.getRoot();
std::vector<SDOperand> OutChains;
SDValue Root = DAG.getRoot();
std::vector<SDValue> OutChains;
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
MVT ObjectVT = getValueType(I->getType());
@ -105,7 +105,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
} else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
SDValue Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
if (ObjectVT != MVT::i32) {
unsigned AssertOp = ISD::AssertSext;
Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
@ -115,8 +115,8 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
ArgValues.push_back(Arg);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDOperand Load;
SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDValue Load;
if (ObjectVT == MVT::i32) {
Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
} else {
@ -143,14 +143,14 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
// FP value is passed in an integer register.
unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
SDValue Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
ArgValues.push_back(Arg);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDValue Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
ArgValues.push_back(Load);
}
ArgOffset += 4;
@ -163,30 +163,30 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
if (CurArgReg < ArgRegEnd) ++CurArgReg;
ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
} else {
SDOperand HiVal;
SDValue HiVal;
if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
}
SDOperand LoVal;
SDValue LoVal;
if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
}
// Compose the two halves together into an i64 unit.
SDOperand WholeValue =
SDValue WholeValue =
DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
// If we want a double, do a bit convert.
@ -208,10 +208,10 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
ArgOffset += 4;
@ -223,10 +223,10 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
&OutChains[0], OutChains.size()));
}
static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) {
unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
SDOperand Chain = Op.getOperand(0);
SDOperand Callee = Op.getOperand(4);
SDValue Chain = Op.getOperand(0);
SDValue Callee = Op.getOperand(4);
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
#if 0
@ -270,8 +270,8 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize));
SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
SmallVector<SDOperand, 8> MemOpChains;
SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
SmallVector<SDValue, 8> MemOpChains;
#if 0
// Walk the register/memloc assignments, inserting copies/loads.
@ -279,7 +279,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
CCValAssign &VA = ArgLocs[i];
// Arguments start after the 5 first operands of ISD::CALL
SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
SDValue Arg = Op.getOperand(5+2*VA.getValNo());
// Promote the value if needed.
switch (VA.getLocInfo()) {
@ -306,9 +306,9 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
assert(VA.isMemLoc());
// Create a store off the stack pointer for this argument.
SDOperand StackPtr = DAG.getRegister(SP::O6, MVT::i32);
SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
// FIXME: VERIFY THAT 68 IS RIGHT.
SDOperand PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68);
SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68);
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
}
@ -320,9 +320,9 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
unsigned ArgOffset = 68;
for (unsigned i = 5, e = Op.getNumOperands(); i != e; i += 2) {
SDOperand Val = Op.getOperand(i);
SDValue Val = Op.getOperand(i);
MVT ObjectVT = Val.getValueType();
SDOperand ValToStore(0, 0);
SDValue ValToStore(0, 0);
unsigned ObjSize;
switch (ObjectVT.getSimpleVT()) {
default: assert(0 && "Unhandled argument type!");
@ -358,9 +358,9 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
}
// Split the value into top and bottom part. Top part goes in a reg.
SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
DAG.getConstant(1, MVT::i32));
SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
DAG.getConstant(0, MVT::i32));
RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
@ -375,8 +375,8 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
}
if (ValToStore.Val) {
SDOperand StackPtr = DAG.getRegister(SP::O6, MVT::i32);
SDOperand PtrOff = DAG.getConstant(ArgOffset, MVT::i32);
SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32);
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
}
@ -393,7 +393,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
// chain and flag operands which copy the outgoing args into registers.
// The InFlag in necessary since all emited instructions must be
// stuck together.
SDOperand InFlag;
SDValue InFlag;
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
unsigned Reg = RegsToPass[i].first;
// Remap I0->I7 -> O0->O7.
@ -415,7 +415,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
std::vector<MVT> NodeTys;
NodeTys.push_back(MVT::Other); // Returns a chain
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
SDOperand Ops[] = { Chain, Callee, InFlag };
SDValue Ops[] = { Chain, Callee, InFlag };
Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2);
InFlag = Chain.getValue(1);
@ -429,7 +429,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
CCState RVInfo(CallingConv, isVarArg, DAG.getTarget(), RVLocs);
RVInfo.AnalyzeCallResult(Op.Val, RetCC_Sparc32);
SmallVector<SDOperand, 8> ResultVals;
SmallVector<SDValue, 8> ResultVals;
// Copy all of the result registers out of their specified physreg.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
@ -650,7 +650,7 @@ const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
/// be zero. Op is expected to be a target specific node. Used by DAG
/// combiner.
void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
APInt &KnownZero,
APInt &KnownOne,
@ -679,7 +679,7 @@ void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
ISD::CondCode CC, unsigned &SPCC) {
if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 &&
CC == ISD::SETNE &&
@ -691,50 +691,50 @@ static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
isa<ConstantSDNode>(LHS.getOperand(1)) &&
cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 &&
cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) {
SDOperand CMPCC = LHS.getOperand(3);
SDValue CMPCC = LHS.getOperand(3);
SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
LHS = CMPCC.getOperand(0);
RHS = CMPCC.getOperand(1);
}
}
static SDOperand LowerGLOBALADDRESS(SDOperand Op, SelectionDAG &DAG) {
static SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) {
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
SDValue Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
SDValue Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
}
static SDOperand LowerCONSTANTPOOL(SDOperand Op, SelectionDAG &DAG) {
static SDValue LowerCONSTANTPOOL(SDValue Op, SelectionDAG &DAG) {
ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
Constant *C = N->getConstVal();
SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
SDValue Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
SDValue Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
}
static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
// Convert the fp value to integer in an FP register.
assert(Op.getValueType() == MVT::i32);
Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
}
static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
assert(Op.getOperand(0).getValueType() == MVT::i32);
SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
// Convert the int value to FP in an FP register.
return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
}
static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
SDOperand Chain = Op.getOperand(0);
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
SDValue Chain = Op.getOperand(0);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
SDOperand LHS = Op.getOperand(2);
SDOperand RHS = Op.getOperand(3);
SDOperand Dest = Op.getOperand(4);
SDValue LHS = Op.getOperand(2);
SDValue RHS = Op.getOperand(3);
SDValue Dest = Op.getOperand(4);
unsigned Opc, SPCC = ~0U;
// If this is a br_cc of a "setcc", and if the setcc got lowered into
@ -742,12 +742,12 @@ static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
LookThroughSetCC(LHS, RHS, CC, SPCC);
// Get the condition flag.
SDOperand CompareFlag;
SDValue CompareFlag;
if (LHS.getValueType() == MVT::i32) {
std::vector<MVT> VTs;
VTs.push_back(MVT::i32);
VTs.push_back(MVT::Flag);
SDOperand Ops[2] = { LHS, RHS };
SDValue Ops[2] = { LHS, RHS };
CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
Opc = SPISD::BRICC;
@ -760,24 +760,24 @@ static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
DAG.getConstant(SPCC, MVT::i32), CompareFlag);
}
static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
SDOperand LHS = Op.getOperand(0);
SDOperand RHS = Op.getOperand(1);
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
SDOperand TrueVal = Op.getOperand(2);
SDOperand FalseVal = Op.getOperand(3);
SDValue TrueVal = Op.getOperand(2);
SDValue FalseVal = Op.getOperand(3);
unsigned Opc, SPCC = ~0U;
// If this is a select_cc of a "setcc", and if the setcc got lowered into
// an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
LookThroughSetCC(LHS, RHS, CC, SPCC);
SDOperand CompareFlag;
SDValue CompareFlag;
if (LHS.getValueType() == MVT::i32) {
std::vector<MVT> VTs;
VTs.push_back(LHS.getValueType()); // subcc returns a value
VTs.push_back(MVT::Flag);
SDOperand Ops[2] = { LHS, RHS };
SDValue Ops[2] = { LHS, RHS };
CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
Opc = SPISD::SELECT_ICC;
if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
@ -790,11 +790,11 @@ static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
DAG.getConstant(SPCC, MVT::i32), CompareFlag);
}
static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
SparcTargetLowering &TLI) {
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
SDValue Offset = DAG.getNode(ISD::ADD, MVT::i32,
DAG.getRegister(SP::I6, MVT::i32),
DAG.getConstant(TLI.getVarArgsFrameOffset(),
MVT::i32));
@ -802,15 +802,15 @@ static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0);
}
static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG) {
static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
SDNode *Node = Op.Val;
MVT VT = Node->getValueType(0);
SDOperand InChain = Node->getOperand(0);
SDOperand VAListPtr = Node->getOperand(1);
SDValue InChain = Node->getOperand(0);
SDValue VAListPtr = Node->getOperand(1);
const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
SDOperand VAList = DAG.getLoad(MVT::i32, InChain, VAListPtr, SV, 0);
SDValue VAList = DAG.getLoad(MVT::i32, InChain, VAListPtr, SV, 0);
// Increment the pointer, VAList, to the next vaarg
SDOperand NextPtr = DAG.getNode(ISD::ADD, MVT::i32, VAList,
SDValue NextPtr = DAG.getNode(ISD::ADD, MVT::i32, VAList,
DAG.getConstant(VT.getSizeInBits()/8,
MVT::i32));
// Store the incremented VAList to the legalized pointer
@ -822,41 +822,41 @@ static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG) {
return DAG.getLoad(VT, InChain, VAList, NULL, 0);
// Otherwise, load it as i64, then do a bitconvert.
SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
SDValue V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
// Bit-Convert the value to f64.
SDOperand Ops[2] = {
SDValue Ops[2] = {
DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V),
V.getValue(1)
};
return DAG.getMergeValues(Ops, 2);
}
static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG) {
SDOperand Chain = Op.getOperand(0); // Legalize the chain.
SDOperand Size = Op.getOperand(1); // Legalize the size.
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
SDValue Chain = Op.getOperand(0); // Legalize the chain.
SDValue Size = Op.getOperand(1); // Legalize the size.
unsigned SPReg = SP::O6;
SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value
SDValue SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
SDValue NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value
Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain
// The resultant pointer is actually 16 words from the bottom of the stack,
// to provide a register spill area.
SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
SDValue NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
DAG.getConstant(96, MVT::i32));
SDOperand Ops[2] = { NewVal, Chain };
SDValue Ops[2] = { NewVal, Chain };
return DAG.getMergeValues(Ops, 2);
}
SDOperand SparcTargetLowering::
LowerOperation(SDOperand Op, SelectionDAG &DAG) {
SDValue SparcTargetLowering::
LowerOperation(SDValue Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
default: assert(0 && "Should not custom lower this!");
// Frame & Return address. Currently unimplemented
case ISD::RETURNADDR: return SDOperand();
case ISD::FRAMEADDR: return SDOperand();
case ISD::RETURNADDR: return SDValue();
case ISD::FRAMEADDR: return SDValue();
case ISD::GlobalTLSAddress:
assert(0 && "TLS not implemented for Sparc.");
case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);

6
lib/Target/Sparc/SparcISelLowering.h
View File

@ -43,14 +43,14 @@ namespace llvm {
int VarArgsFrameOffset; // Frame offset to start of varargs area.
public:
SparcTargetLowering(TargetMachine &TM);
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
int getVarArgsFrameOffset() const { return VarArgsFrameOffset; }
/// computeMaskedBitsForTargetNode - Determine which of the bits specified
/// in Mask are known to be either zero or one and return them in the
/// KnownZero/KnownOne bitsets.
virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
virtual void computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
APInt &KnownZero,
APInt &KnownOne,
@ -58,7 +58,7 @@ namespace llvm {
unsigned Depth = 0) const;
virtual void LowerArguments(Function &F, SelectionDAG &DAG,
SmallVectorImpl<SDOperand> &ArgValues);
SmallVectorImpl<SDValue> &ArgValues);
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB);

258
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -50,7 +50,7 @@ STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
namespace {
/// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
/// SDOperand's instead of register numbers for the leaves of the matched
/// SDValue's instead of register numbers for the leaves of the matched
/// tree.
struct X86ISelAddressMode {
enum {
@ -59,13 +59,13 @@ namespace {
} BaseType;
struct { // This is really a union, discriminated by BaseType!
SDOperand Reg;
SDValue Reg;
int FrameIndex;
} Base;
bool isRIPRel; // RIP as base?
unsigned Scale;
SDOperand IndexReg;
SDValue IndexReg;
unsigned Disp;
GlobalValue *GV;
Constant *CP;
@ -143,38 +143,38 @@ namespace {
#include "X86GenDAGISel.inc"
private:
SDNode *Select(SDOperand N);
SDNode *Select(SDValue N);
bool MatchAddress(SDOperand N, X86ISelAddressMode &AM,
bool MatchAddress(SDValue N, X86ISelAddressMode &AM,
bool isRoot = true, unsigned Depth = 0);
bool MatchAddressBase(SDOperand N, X86ISelAddressMode &AM,
bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM,
bool isRoot, unsigned Depth);
bool SelectAddr(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Scale, SDOperand &Index, SDOperand &Disp);
bool SelectLEAAddr(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Scale, SDOperand &Index, SDOperand &Disp);
bool SelectScalarSSELoad(SDOperand Op, SDOperand Pred,
SDOperand N, SDOperand &Base, SDOperand &Scale,
SDOperand &Index, SDOperand &Disp,
SDOperand &InChain, SDOperand &OutChain);
bool TryFoldLoad(SDOperand P, SDOperand N,
SDOperand &Base, SDOperand &Scale,
SDOperand &Index, SDOperand &Disp);
bool SelectAddr(SDValue Op, SDValue N, SDValue &Base,
SDValue &Scale, SDValue &Index, SDValue &Disp);
bool SelectLEAAddr(SDValue Op, SDValue N, SDValue &Base,
SDValue &Scale, SDValue &Index, SDValue &Disp);
bool SelectScalarSSELoad(SDValue Op, SDValue Pred,
SDValue N, SDValue &Base, SDValue &Scale,
SDValue &Index, SDValue &Disp,
SDValue &InChain, SDValue &OutChain);
bool TryFoldLoad(SDValue P, SDValue N,
SDValue &Base, SDValue &Scale,
SDValue &Index, SDValue &Disp);
void PreprocessForRMW(SelectionDAG &DAG);
void PreprocessForFPConvert(SelectionDAG &DAG);
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
std::vector<SDOperand> &OutOps,
std::vector<SDValue> &OutOps,
SelectionDAG &DAG);
void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
inline void getAddressOperands(X86ISelAddressMode &AM, SDOperand &Base,
SDOperand &Scale, SDOperand &Index,
SDOperand &Disp) {
inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
SDValue &Scale, SDValue &Index,
SDValue &Disp) {
Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
AM.Base.Reg;
@ -196,19 +196,19 @@ namespace {
/// getI8Imm - Return a target constant with the specified value, of type
/// i8.
inline SDOperand getI8Imm(unsigned Imm) {
inline SDValue getI8Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i8);
}
/// getI16Imm - Return a target constant with the specified value, of type
/// i16.
inline SDOperand getI16Imm(unsigned Imm) {
inline SDValue getI16Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i16);
}
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
inline SDOperand getI32Imm(unsigned Imm) {
inline SDValue getI32Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i32);
}
@ -218,7 +218,7 @@ namespace {
/// getTruncate - return an SDNode that implements a subreg based truncate
/// of the specified operand to the the specified value type.
SDNode *getTruncate(SDOperand N0, MVT VT);
SDNode *getTruncate(SDValue N0, MVT VT);
#ifndef NDEBUG
unsigned Indent;
@ -233,7 +233,7 @@ static SDNode *findFlagUse(SDNode *N) {
for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
SDNode *User = *I;
for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
SDOperand Op = User->getOperand(i);
SDValue Op = User->getOperand(i);
if (Op.Val == N && Op.ResNo == FlagResNo)
return User;
}
@ -352,9 +352,9 @@ bool X86DAGToDAGISel::CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const {
/// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
/// and move load below the TokenFactor. Replace store's chain operand with
/// load's chain result.
static void MoveBelowTokenFactor(SelectionDAG &DAG, SDOperand Load,
SDOperand Store, SDOperand TF) {
std::vector<SDOperand> Ops;
static void MoveBelowTokenFactor(SelectionDAG &DAG, SDValue Load,
SDValue Store, SDValue TF) {
std::vector<SDValue> Ops;
for (unsigned i = 0, e = TF.Val->getNumOperands(); i != e; ++i)
if (Load.Val == TF.Val->getOperand(i).Val)
Ops.push_back(Load.Val->getOperand(0));
@ -368,8 +368,8 @@ static void MoveBelowTokenFactor(SelectionDAG &DAG, SDOperand Load,
/// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG.
///
static bool isRMWLoad(SDOperand N, SDOperand Chain, SDOperand Address,
SDOperand &Load) {
static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
SDValue &Load) {
if (N.getOpcode() == ISD::BIT_CONVERT)
N = N.getOperand(0);
@ -437,19 +437,19 @@ void X86DAGToDAGISel::PreprocessForRMW(SelectionDAG &DAG) {
E = DAG.allnodes_end(); I != E; ++I) {
if (!ISD::isNON_TRUNCStore(I))
continue;
SDOperand Chain = I->getOperand(0);
SDValue Chain = I->getOperand(0);
if (Chain.Val->getOpcode() != ISD::TokenFactor)
continue;
SDOperand N1 = I->getOperand(1);
SDOperand N2 = I->getOperand(2);
SDValue N1 = I->getOperand(1);
SDValue N2 = I->getOperand(2);
if ((N1.getValueType().isFloatingPoint() &&
!N1.getValueType().isVector()) ||
!N1.hasOneUse())
continue;
bool RModW = false;
SDOperand Load;
SDValue Load;
unsigned Opcode = N1.Val->getOpcode();
switch (Opcode) {
case ISD::ADD:
@ -460,8 +460,8 @@ void X86DAGToDAGISel::PreprocessForRMW(SelectionDAG &DAG) {
case ISD::ADDC:
case ISD::ADDE:
case ISD::VECTOR_SHUFFLE: {
SDOperand N10 = N1.getOperand(0);
SDOperand N11 = N1.getOperand(1);
SDValue N10 = N1.getOperand(0);
SDValue N11 = N1.getOperand(1);
RModW = isRMWLoad(N10, Chain, N2, Load);
if (!RModW)
RModW = isRMWLoad(N11, Chain, N2, Load);
@ -477,14 +477,14 @@ void X86DAGToDAGISel::PreprocessForRMW(SelectionDAG &DAG) {
case ISD::SUBE:
case X86ISD::SHLD:
case X86ISD::SHRD: {
SDOperand N10 = N1.getOperand(0);
SDValue N10 = N1.getOperand(0);
RModW = isRMWLoad(N10, Chain, N2, Load);
break;
}
}
if (RModW) {
MoveBelowTokenFactor(DAG, Load, SDOperand(I, 0), Chain);
MoveBelowTokenFactor(DAG, Load, SDValue(I, 0), Chain);
++NumLoadMoved;
}
}
@ -533,12 +533,12 @@ void X86DAGToDAGISel::PreprocessForFPConvert(SelectionDAG &DAG) {
else
MemVT = SrcIsSSE ? SrcVT : DstVT;
SDOperand MemTmp = DAG.CreateStackTemporary(MemVT);
SDValue MemTmp = DAG.CreateStackTemporary(MemVT);
// FIXME: optimize the case where the src/dest is a load or store?
SDOperand Store = DAG.getTruncStore(DAG.getEntryNode(), N->getOperand(0),
SDValue Store = DAG.getTruncStore(DAG.getEntryNode(), N->getOperand(0),
MemTmp, NULL, 0, MemVT);
SDOperand Result = DAG.getExtLoad(ISD::EXTLOAD, DstVT, Store, MemTmp,
SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, DstVT, Store, MemTmp,
NULL, 0, MemVT);
// We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
@ -546,7 +546,7 @@ void X86DAGToDAGISel::PreprocessForFPConvert(SelectionDAG &DAG) {
// anything below the conversion could be folded into other existing nodes.
// To avoid invalidating 'I', back it up to the convert node.
--I;
DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result);
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
// Now that we did that, the node is dead. Increment the iterator to the
// next node to process, then delete N.
@ -674,7 +674,7 @@ void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
/// MatchAddress - Add the specified node to the specified addressing mode,
/// returning true if it cannot be done. This just pattern matches for the
/// addressing mode.
bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM,
bool isRoot, unsigned Depth) {
// Limit recursion.
if (Depth > 5)
@ -719,7 +719,7 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
// been picked, we can't fit the result available in the register in the
// addressing mode. Duplicate GlobalAddress or ConstantPool as displacement.
if (!AlreadySelected || (AM.Base.Reg.Val && AM.IndexReg.Val)) {
SDOperand N0 = N.getOperand(0);
SDValue N0 = N.getOperand(0);
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
GlobalValue *GV = G->getGlobal();
AM.GV = GV;
@ -765,7 +765,7 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
unsigned Val = CN->getValue();
if (Val == 1 || Val == 2 || Val == 3) {
AM.Scale = 1 << Val;
SDOperand ShVal = N.Val->getOperand(0);
SDValue ShVal = N.Val->getOperand(0);
// Okay, we know that we have a scale by now. However, if the scaled
// value is an add of something and a constant, we can fold the
@ -804,8 +804,8 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) {
AM.Scale = unsigned(CN->getValue())-1;
SDOperand MulVal = N.Val->getOperand(0);
SDOperand Reg;
SDValue MulVal = N.Val->getOperand(0);
SDValue Reg;
// Okay, we know that we have a scale by now. However, if the scaled
// value is an add of something and a constant, we can fold the
@ -869,7 +869,7 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
// Handle "(x << C1) & C2" as "(X & (C2>>C1)) << C1" if safe and if this
// allows us to fold the shift into this addressing mode.
if (AlreadySelected) break;
SDOperand Shift = N.getOperand(0);
SDValue Shift = N.getOperand(0);
if (Shift.getOpcode() != ISD::SHL) break;
// Scale must not be used already.
@ -894,9 +894,9 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
break;
// Get the new AND mask, this folds to a constant.
SDOperand NewANDMask = CurDAG->getNode(ISD::SRL, N.getValueType(),
SDOperand(C2, 0), SDOperand(C1, 0));
SDOperand NewAND = CurDAG->getNode(ISD::AND, N.getValueType(),
SDValue NewANDMask = CurDAG->getNode(ISD::SRL, N.getValueType(),
SDValue(C2, 0), SDValue(C1, 0));
SDValue NewAND = CurDAG->getNode(ISD::AND, N.getValueType(),
Shift.getOperand(0), NewANDMask);
NewANDMask.Val->setNodeId(Shift.Val->getNodeId());
NewAND.Val->setNodeId(N.Val->getNodeId());
@ -912,7 +912,7 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
/// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
/// specified addressing mode without any further recursion.
bool X86DAGToDAGISel::MatchAddressBase(SDOperand N, X86ISelAddressMode &AM,
bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM,
bool isRoot, unsigned Depth) {
// Is the base register already occupied?
if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.Val) {
@ -936,9 +936,9 @@ bool X86DAGToDAGISel::MatchAddressBase(SDOperand N, X86ISelAddressMode &AM,
/// SelectAddr - returns true if it is able pattern match an addressing mode.
/// It returns the operands which make up the maximal addressing mode it can
/// match by reference.
bool X86DAGToDAGISel::SelectAddr(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Scale, SDOperand &Index,
SDOperand &Disp) {
bool X86DAGToDAGISel::SelectAddr(SDValue Op, SDValue N, SDValue &Base,
SDValue &Scale, SDValue &Index,
SDValue &Disp) {
X86ISelAddressMode AM;
if (MatchAddress(N, AM))
return false;
@ -958,7 +958,7 @@ bool X86DAGToDAGISel::SelectAddr(SDOperand Op, SDOperand N, SDOperand &Base,
/// isZeroNode - Returns true if Elt is a constant zero or a floating point
/// constant +0.0.
static inline bool isZeroNode(SDOperand Elt) {
static inline bool isZeroNode(SDValue Elt) {
return ((isa<ConstantSDNode>(Elt) &&
cast<ConstantSDNode>(Elt)->getValue() == 0) ||
(isa<ConstantFPSDNode>(Elt) &&
@ -969,11 +969,11 @@ static inline bool isZeroNode(SDOperand Elt) {
/// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
/// match a load whose top elements are either undef or zeros. The load flavor
/// is derived from the type of N, which is either v4f32 or v2f64.
bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand Op, SDOperand Pred,
SDOperand N, SDOperand &Base,
SDOperand &Scale, SDOperand &Index,
SDOperand &Disp, SDOperand &InChain,
SDOperand &OutChain) {
bool X86DAGToDAGISel::SelectScalarSSELoad(SDValue Op, SDValue Pred,
SDValue N, SDValue &Base,
SDValue &Scale, SDValue &Index,
SDValue &Disp, SDValue &InChain,
SDValue &OutChain) {
if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
InChain = N.getOperand(0).getValue(1);
if (ISD::isNON_EXTLoad(InChain.Val) &&
@ -1001,7 +1001,7 @@ bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand Op, SDOperand Pred,
if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
return false;
OutChain = LD->getChain();
InChain = SDOperand(LD, 1);
InChain = SDValue(LD, 1);
return true;
}
return false;
@ -1010,9 +1010,9 @@ bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand Op, SDOperand Pred,
/// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
/// mode it matches can be cost effectively emitted as an LEA instruction.
bool X86DAGToDAGISel::SelectLEAAddr(SDOperand Op, SDOperand N,
SDOperand &Base, SDOperand &Scale,
SDOperand &Index, SDOperand &Disp) {
bool X86DAGToDAGISel::SelectLEAAddr(SDValue Op, SDValue N,
SDValue &Base, SDValue &Scale,
SDValue &Index, SDValue &Disp) {
X86ISelAddressMode AM;
if (MatchAddress(N, AM))
return false;
@ -1061,9 +1061,9 @@ bool X86DAGToDAGISel::SelectLEAAddr(SDOperand Op, SDOperand N,
return false;
}
bool X86DAGToDAGISel::TryFoldLoad(SDOperand P, SDOperand N,
SDOperand &Base, SDOperand &Scale,
SDOperand &Index, SDOperand &Disp) {
bool X86DAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
SDValue &Base, SDValue &Scale,
SDValue &Index, SDValue &Disp) {
if (ISD::isNON_EXTLoad(N.Val) &&
N.hasOneUse() &&
CanBeFoldedBy(N.Val, P.Val, P.Val))
@ -1111,8 +1111,8 @@ static SDNode *FindCallStartFromCall(SDNode *Node) {
return FindCallStartFromCall(Node->getOperand(0).Val);
}
SDNode *X86DAGToDAGISel::getTruncate(SDOperand N0, MVT VT) {
SDOperand SRIdx;
SDNode *X86DAGToDAGISel::getTruncate(SDValue N0, MVT VT) {
SDValue SRIdx;
switch (VT.getSimpleVT()) {
default: assert(0 && "Unknown truncate!");
case MVT::i8:
@ -1130,7 +1130,7 @@ SDNode *X86DAGToDAGISel::getTruncate(SDOperand N0, MVT VT) {
Opc = X86::MOV32to32_;
break;
}
N0 = SDOperand(CurDAG->getTargetNode(Opc, N0VT, MVT::Flag, N0), 0);
N0 = SDValue(CurDAG->getTargetNode(Opc, N0VT, MVT::Flag, N0), 0);
return CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
VT, N0, SRIdx, N0.getValue(1));
}
@ -1146,7 +1146,7 @@ SDNode *X86DAGToDAGISel::getTruncate(SDOperand N0, MVT VT) {
}
SDNode *X86DAGToDAGISel::Select(SDOperand N) {
SDNode *X86DAGToDAGISel::Select(SDValue N) {
SDNode *Node = N.Val;
MVT NVT = Node->getValueType(0);
unsigned Opc, MOpc;
@ -1183,13 +1183,13 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
if (TM.getCodeModel() != CodeModel::Small)
break;
MVT PtrVT = TLI.getPointerTy();
SDOperand N0 = N.getOperand(0);
SDOperand N1 = N.getOperand(1);
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N.Val->getValueType(0) == PtrVT &&
N0.getOpcode() == X86ISD::Wrapper &&
N1.getOpcode() == ISD::Constant) {
unsigned Offset = (unsigned)cast<ConstantSDNode>(N1)->getValue();
SDOperand C(0, 0);
SDValue C(0, 0);
// TODO: handle ExternalSymbolSDNode.
if (GlobalAddressSDNode *G =
dyn_cast<GlobalAddressSDNode>(N0.getOperand(0))) {
@ -1204,7 +1204,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
if (C.Val) {
if (Subtarget->is64Bit()) {
SDOperand Ops[] = { CurDAG->getRegister(0, PtrVT), getI8Imm(1),
SDValue Ops[] = { CurDAG->getRegister(0, PtrVT), getI8Imm(1),
CurDAG->getRegister(0, PtrVT), C };
return CurDAG->SelectNodeTo(N.Val, X86::LEA64r, MVT::i64, Ops, 4);
} else
@ -1218,8 +1218,8 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
case ISD::SMUL_LOHI:
case ISD::UMUL_LOHI: {
SDOperand N0 = Node->getOperand(0);
SDOperand N1 = Node->getOperand(1);
SDValue N0 = Node->getOperand(0);
SDValue N1 = Node->getOperand(1);
bool isSigned = Opcode == ISD::SMUL_LOHI;
if (!isSigned)
@ -1248,7 +1248,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
}
SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
SDValue Tmp0, Tmp1, Tmp2, Tmp3;
bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
// multiplty is commmutative
if (!foldedLoad) {
@ -1258,8 +1258,8 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
}
AddToISelQueue(N0);
SDOperand InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), LoReg,
N0, SDOperand()).getValue(1);
SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), LoReg,
N0, SDValue()).getValue(1);
if (foldedLoad) {
AddToISelQueue(N1.getOperand(0));
@ -1267,21 +1267,21 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
AddToISelQueue(Tmp1);
AddToISelQueue(Tmp2);
AddToISelQueue(Tmp3);
SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
SDNode *CNode =
CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
InFlag = SDOperand(CNode, 1);
InFlag = SDValue(CNode, 1);
// Update the chain.
ReplaceUses(N1.getValue(1), SDOperand(CNode, 0));
ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
} else {
AddToISelQueue(N1);
InFlag =
SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
SDValue(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
}
// Copy the low half of the result, if it is needed.
if (!N.getValue(0).use_empty()) {
SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
LoReg, NVT, InFlag);
InFlag = Result.getValue(2);
ReplaceUses(N.getValue(0), Result);
@ -1293,18 +1293,18 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
}
// Copy the high half of the result, if it is needed.
if (!N.getValue(1).use_empty()) {
SDOperand Result;
SDValue Result;
if (HiReg == X86::AH && Subtarget->is64Bit()) {
// Prevent use of AH in a REX instruction by referencing AX instead.
// Shift it down 8 bits.
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
X86::AX, MVT::i16, InFlag);
InFlag = Result.getValue(2);
Result = SDOperand(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
CurDAG->getTargetConstant(8, MVT::i8)), 0);
// Then truncate it down to i8.
SDOperand SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
Result = SDOperand(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
MVT::i8, Result, SRIdx), 0);
} else {
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
@ -1328,8 +1328,8 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
case ISD::SDIVREM:
case ISD::UDIVREM: {
SDOperand N0 = Node->getOperand(0);
SDOperand N1 = Node->getOperand(1);
SDValue N0 = Node->getOperand(0);
SDValue N1 = Node->getOperand(1);
bool isSigned = Opcode == ISD::SDIVREM;
if (!isSigned)
@ -1375,46 +1375,46 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
break;
}
SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
SDValue Tmp0, Tmp1, Tmp2, Tmp3;
bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
SDOperand InFlag;
SDValue InFlag;
if (NVT == MVT::i8 && !isSigned) {
// Special case for div8, just use a move with zero extension to AX to
// clear the upper 8 bits (AH).
SDOperand Tmp0, Tmp1, Tmp2, Tmp3, Move, Chain;
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Move, Chain;
if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3)) {
SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N0.getOperand(0) };
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N0.getOperand(0) };
AddToISelQueue(N0.getOperand(0));
AddToISelQueue(Tmp0);
AddToISelQueue(Tmp1);
AddToISelQueue(Tmp2);
AddToISelQueue(Tmp3);
Move =
SDOperand(CurDAG->getTargetNode(X86::MOVZX16rm8, MVT::i16, MVT::Other,
SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, MVT::i16, MVT::Other,
Ops, 5), 0);
Chain = Move.getValue(1);
ReplaceUses(N0.getValue(1), Chain);
} else {
AddToISelQueue(N0);
Move =
SDOperand(CurDAG->getTargetNode(X86::MOVZX16rr8, MVT::i16, N0), 0);
SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, MVT::i16, N0), 0);
Chain = CurDAG->getEntryNode();
}
Chain = CurDAG->getCopyToReg(Chain, X86::AX, Move, SDOperand());
Chain = CurDAG->getCopyToReg(Chain, X86::AX, Move, SDValue());
InFlag = Chain.getValue(1);
} else {
AddToISelQueue(N0);
InFlag =
CurDAG->getCopyToReg(CurDAG->getEntryNode(),
LoReg, N0, SDOperand()).getValue(1);
LoReg, N0, SDValue()).getValue(1);
if (isSigned) {
// Sign extend the low part into the high part.
InFlag =
SDOperand(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
SDValue(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
} else {
// Zero out the high part, effectively zero extending the input.
SDOperand ClrNode = SDOperand(CurDAG->getTargetNode(ClrOpcode, NVT), 0);
SDValue ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, NVT), 0);
InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), HiReg,
ClrNode, InFlag).getValue(1);
}
@ -1426,21 +1426,21 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
AddToISelQueue(Tmp1);
AddToISelQueue(Tmp2);
AddToISelQueue(Tmp3);
SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
SDNode *CNode =
CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
InFlag = SDOperand(CNode, 1);
InFlag = SDValue(CNode, 1);
// Update the chain.
ReplaceUses(N1.getValue(1), SDOperand(CNode, 0));
ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
} else {
AddToISelQueue(N1);
InFlag =
SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
SDValue(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
}
// Copy the division (low) result, if it is needed.
if (!N.getValue(0).use_empty()) {
SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
LoReg, NVT, InFlag);
InFlag = Result.getValue(2);
ReplaceUses(N.getValue(0), Result);
@ -1452,18 +1452,18 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
}
// Copy the remainder (high) result, if it is needed.
if (!N.getValue(1).use_empty()) {
SDOperand Result;
SDValue Result;
if (HiReg == X86::AH && Subtarget->is64Bit()) {
// Prevent use of AH in a REX instruction by referencing AX instead.
// Shift it down 8 bits.
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
X86::AX, MVT::i16, InFlag);
InFlag = Result.getValue(2);
Result = SDOperand(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
CurDAG->getTargetConstant(8, MVT::i8)), 0);
// Then truncate it down to i8.
SDOperand SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
Result = SDOperand(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
MVT::i8, Result, SRIdx), 0);
} else {
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
@ -1490,7 +1490,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
if (NVT == MVT::i8)
break;
SDOperand N0 = Node->getOperand(0);
SDValue N0 = Node->getOperand(0);
// Get the subregsiter index for the type to extend.
MVT N0VT = N0.getValueType();
unsigned Idx = (N0VT == MVT::i32) ? X86::SUBREG_32BIT :
@ -1503,9 +1503,9 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
// If we have an index, generate an insert_subreg into undef.
AddToISelQueue(N0);
SDOperand Undef =
SDOperand(CurDAG->getTargetNode(X86::IMPLICIT_DEF, NVT), 0);
SDOperand SRIdx = CurDAG->getTargetConstant(Idx, MVT::i32);
SDValue Undef =
SDValue(CurDAG->getTargetNode(X86::IMPLICIT_DEF, NVT), 0);
SDValue SRIdx = CurDAG->getTargetConstant(Idx, MVT::i32);
SDNode *ResNode = CurDAG->getTargetNode(X86::INSERT_SUBREG,
NVT, Undef, N0, SRIdx);
@ -1519,11 +1519,11 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
}
case ISD::SIGN_EXTEND_INREG: {
SDOperand N0 = Node->getOperand(0);
SDValue N0 = Node->getOperand(0);
AddToISelQueue(N0);
MVT SVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
SDOperand TruncOp = SDOperand(getTruncate(N0, SVT), 0);
SDValue TruncOp = SDValue(getTruncate(N0, SVT), 0);
unsigned Opc = 0;
switch (NVT.getSimpleVT()) {
default: assert(0 && "Unknown sign_extend_inreg!");
@ -1564,7 +1564,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
}
case ISD::TRUNCATE: {
SDOperand Input = Node->getOperand(0);
SDValue Input = Node->getOperand(0);
AddToISelQueue(Node->getOperand(0));
SDNode *ResNode = getTruncate(Input, NVT);
@ -1581,9 +1581,9 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
case ISD::DECLARE: {
// Handle DECLARE nodes here because the second operand may have been
// wrapped in X86ISD::Wrapper.
SDOperand Chain = Node->getOperand(0);
SDOperand N1 = Node->getOperand(1);
SDOperand N2 = Node->getOperand(2);
SDValue Chain = Node->getOperand(0);
SDValue N1 = Node->getOperand(1);
SDValue N2 = Node->getOperand(2);
if (!isa<FrameIndexSDNode>(N1))
break;
int FI = cast<FrameIndexSDNode>(N1)->getIndex();
@ -1594,10 +1594,10 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
isa<GlobalAddressSDNode>(N2.getOperand(0))) {
GlobalValue *GV =
cast<GlobalAddressSDNode>(N2.getOperand(0))->getGlobal();
SDOperand Tmp1 = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
SDOperand Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
SDValue Tmp1 = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
AddToISelQueue(Chain);
SDOperand Ops[] = { Tmp1, Tmp2, Chain };
SDValue Ops[] = { Tmp1, Tmp2, Chain };
return CurDAG->getTargetNode(TargetInstrInfo::DECLARE,
MVT::Other, Ops, 3);
}
@ -1621,9 +1621,9 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
}
bool X86DAGToDAGISel::
SelectInlineAsmMemoryOperand(const SDOperand &Op, char ConstraintCode,
std::vector<SDOperand> &OutOps, SelectionDAG &DAG){
SDOperand Op0, Op1, Op2, Op3;
SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
std::vector<SDValue> &OutOps, SelectionDAG &DAG){
SDValue Op0, Op1, Op2, Op3;
switch (ConstraintCode) {
case 'o': // offsetable ??
case 'v': // not offsetable ??

1130
lib/Target/X86/X86ISelLowering.cpp
View File

File diff suppressed because it is too large Load Diff

146
lib/Target/X86/X86ISelLowering.h
View File

@ -325,7 +325,7 @@ namespace llvm {
/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
/// jumptable.
SDOperand getPICJumpTableRelocBase(SDOperand Table,
SDValue getPICJumpTableRelocBase(SDValue Table,
SelectionDAG &DAG) const;
// Return the number of bytes that a function should pop when it returns (in
@ -357,7 +357,7 @@ namespace llvm {
/// LowerOperation - Provide custom lowering hooks for some operations.
///
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
/// ReplaceNodeResults - Replace a node with an illegal result type
/// with a new node built out of custom code.
@ -365,7 +365,7 @@ namespace llvm {
virtual SDNode *ReplaceNodeResults(SDNode *N, SelectionDAG &DAG);
virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB);
@ -376,12 +376,12 @@ namespace llvm {
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - Return the ISD::SETCC ValueType
virtual MVT getSetCCResultType(const SDOperand &) const;
virtual MVT getSetCCResultType(const SDValue &) const;
/// computeMaskedBitsForTargetNode - Determine which of the bits specified
/// in Mask are known to be either zero or one and return them in the
/// KnownZero/KnownOne bitsets.
virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
virtual void computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
APInt &KnownZero,
APInt &KnownOne,
@ -391,7 +391,7 @@ namespace llvm {
virtual bool
isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG);
ConstraintType getConstraintType(const std::string &Constraint) const;
@ -403,9 +403,9 @@ namespace llvm {
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops.
virtual void LowerAsmOperandForConstraint(SDOperand Op,
virtual void LowerAsmOperandForConstraint(SDValue Op,
char ConstraintLetter,
std::vector<SDOperand> &Ops,
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const;
/// getRegForInlineAsmConstraint - Given a physical register constraint
@ -430,13 +430,13 @@ namespace llvm {
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask
/// values are assumed to be legal.
virtual bool isShuffleMaskLegal(SDOperand Mask, MVT VT) const;
virtual bool isShuffleMaskLegal(SDValue Mask, MVT VT) const;
/// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
/// used by Targets can use this to indicate if there is a suitable
/// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
/// pool entry.
virtual bool isVectorClearMaskLegal(const std::vector<SDOperand> &BVOps,
virtual bool isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
MVT EVT, SelectionDAG &DAG) const;
/// ShouldShrinkFPConstant - If true, then instruction selection should
@ -452,8 +452,8 @@ namespace llvm {
/// IsEligibleForTailCallOptimization - Check whether the call is eligible
/// for tail call optimization. Target which want to do tail call
/// optimization should implement this function.
virtual bool IsEligibleForTailCallOptimization(SDOperand Call,
SDOperand Ret,
virtual bool IsEligibleForTailCallOptimization(SDValue Call,
SDValue Ret,
SelectionDAG &DAG) const;
virtual const X86Subtarget* getSubtarget() {
@ -483,87 +483,87 @@ namespace llvm {
bool X86ScalarSSEf32;
bool X86ScalarSSEf64;
SDNode *LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode*TheCall,
SDNode *LowerCallResult(SDValue Chain, SDValue InFlag, SDNode*TheCall,
unsigned CallingConv, SelectionDAG &DAG);
SDOperand LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
SDValue LowerMemArgument(SDValue Op, SelectionDAG &DAG,
const CCValAssign &VA, MachineFrameInfo *MFI,
unsigned CC, SDOperand Root, unsigned i);
unsigned CC, SDValue Root, unsigned i);
SDOperand LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
const SDOperand &StackPtr,
const CCValAssign &VA, SDOperand Chain,
SDOperand Arg);
SDValue LowerMemOpCallTo(SDValue Op, SelectionDAG &DAG,
const SDValue &StackPtr,
const CCValAssign &VA, SDValue Chain,
SDValue Arg);
// Call lowering helpers.
bool IsCalleePop(SDOperand Op);
bool IsCalleePop(SDValue Op);
bool CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall);
bool CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall);
SDOperand EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDOperand &OutRetAddr,
SDOperand Chain, bool IsTailCall, bool Is64Bit,
SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
SDValue Chain, bool IsTailCall, bool Is64Bit,
int FPDiff);
CCAssignFn *CCAssignFnForNode(SDOperand Op) const;
NameDecorationStyle NameDecorationForFORMAL_ARGUMENTS(SDOperand Op);
CCAssignFn *CCAssignFnForNode(SDValue Op) const;
NameDecorationStyle NameDecorationForFORMAL_ARGUMENTS(SDValue Op);
unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG);
std::pair<SDOperand,SDOperand> FP_TO_SINTHelper(SDOperand Op,
std::pair<SDValue,SDValue> FP_TO_SINTHelper(SDValue Op,
SelectionDAG &DAG);
SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerEXTRACT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerINSERT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerShift(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerFABS(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerFNEG(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerVSETCC(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerSELECT(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerBRCOND(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerMEMSET(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerVACOPY(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerFRAME_TO_ARGS_OFFSET(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerTRAMPOLINE(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerCTLZ(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerCTTZ(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerCMP_SWAP(SDOperand Op, SelectionDAG &DAG);
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG);
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG);
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG);
SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG);
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG);
SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG);
SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG);
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG);
SDValue LowerShift(SDValue Op, SelectionDAG &DAG);
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG);
SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG);
SDValue LowerFABS(SDValue Op, SelectionDAG &DAG);
SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG);
SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG);
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG);
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG);
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG);
SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG);
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG);
SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG);
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG);
SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG);
SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG);
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG);
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG);
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG);
SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG);
SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG);
SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG);
SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG);
SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG);
SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG);
SDNode *ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG);
SDNode *ExpandATOMIC_CMP_SWAP(SDNode *N, SelectionDAG &DAG);
SDNode *ExpandATOMIC_LOAD_SUB(SDNode *N, SelectionDAG &DAG);
SDOperand EmitTargetCodeForMemset(SelectionDAG &DAG,
SDOperand Chain,
SDOperand Dst, SDOperand Src,
SDOperand Size, unsigned Align,
SDValue EmitTargetCodeForMemset(SelectionDAG &DAG,
SDValue Chain,
SDValue Dst, SDValue Src,
SDValue Size, unsigned Align,
const Value *DstSV, uint64_t DstSVOff);
SDOperand EmitTargetCodeForMemcpy(SelectionDAG &DAG,
SDOperand Chain,
SDOperand Dst, SDOperand Src,
SDOperand Size, unsigned Align,
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG,
SDValue Chain,
SDValue Dst, SDValue Src,
SDValue Size, unsigned Align,
bool AlwaysInline,
const Value *DstSV, uint64_t DstSVOff,
const Value *SrcSV, uint64_t SrcSVOff);

14
lib/Target/X86/X86InstrInfo.cpp
View File

@ -2262,12 +2262,12 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
const TargetOperandInfo &TOI = TID.OpInfo[Index];
const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
std::vector<SDOperand> AddrOps;
std::vector<SDOperand> BeforeOps;
std::vector<SDOperand> AfterOps;
std::vector<SDValue> AddrOps;
std::vector<SDValue> BeforeOps;
std::vector<SDValue> AfterOps;
unsigned NumOps = N->getNumOperands();
for (unsigned i = 0; i != NumOps-1; ++i) {
SDOperand Op = N->getOperand(i);
SDValue Op = N->getOperand(i);
if (i >= Index && i < Index+4)
AddrOps.push_back(Op);
else if (i < Index)
@ -2275,7 +2275,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
else if (i > Index)
AfterOps.push_back(Op);
}
SDOperand Chain = N->getOperand(NumOps-1);
SDValue Chain = N->getOperand(NumOps-1);
AddrOps.push_back(Chain);
// Emit the load instruction.
@ -2306,7 +2306,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
VTs.push_back(VT);
}
if (Load)
BeforeOps.push_back(SDOperand(Load, 0));
BeforeOps.push_back(SDValue(Load, 0));
std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
SDNode *NewNode= DAG.getTargetNode(Opc, VTs, &BeforeOps[0], BeforeOps.size());
NewNodes.push_back(NewNode);
@ -2314,7 +2314,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
// Emit the store instruction.
if (FoldedStore) {
AddrOps.pop_back();
AddrOps.push_back(SDOperand(NewNode, 0));
AddrOps.push_back(SDValue(NewNode, 0));
AddrOps.push_back(Chain);
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);

2
lib/Transforms/Scalar/CodeGenPrepare.cpp
View File

@ -963,7 +963,7 @@ bool CodeGenPrepare::OptimizeInlineAsmInst(Instruction *I, CallSite CS,
}
// Compute the constraint code and ConstraintType to use.
TLI->ComputeConstraintToUse(OpInfo, SDOperand());
TLI->ComputeConstraintToUse(OpInfo, SDValue());
if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
OpInfo.isIndirect) {

152
utils/TableGen/DAGISelEmitter.cpp
View File

@ -254,7 +254,7 @@ void DAGISelEmitter::EmitNodeTransforms(std::ostream &OS) {
std::string ClassName = CGP.getSDNodeInfo(SDNode).getSDClassName();
const char *C2 = ClassName == "SDNode" ? "N" : "inN";
OS << "inline SDOperand Transform_" << I->first << "(SDNode *" << C2
OS << "inline SDValue Transform_" << I->first << "(SDNode *" << C2
<< ") {\n";
if (ClassName != "SDNode")
OS << " " << ClassName << " *N = cast<" << ClassName << ">(inN);\n";
@ -347,7 +347,7 @@ private:
/// tested, and if true, the match fails) [when 1], or normal code to emit
/// [when 0], or initialization code to emit [when 2].
std::vector<std::pair<unsigned, std::string> > &GeneratedCode;
/// GeneratedDecl - This is the set of all SDOperand declarations needed for
/// GeneratedDecl - This is the set of all SDValue declarations needed for
/// the set of patterns for each top-level opcode.
std::set<std::string> &GeneratedDecl;
/// TargetOpcodes - The target specific opcodes used by the resulting
@ -536,7 +536,7 @@ public:
} else
FoundChain = true;
ChainName = "Chain" + ChainSuffix;
emitInit("SDOperand " + ChainName + " = " + RootName +
emitInit("SDValue " + ChainName + " = " + RootName +
".getOperand(0);");
}
}
@ -578,9 +578,9 @@ public:
N->getChild(1)->getPredicateFn().empty()) {
if (IntInit *II = dynamic_cast<IntInit*>(N->getChild(1)->getLeafValue())) {
if (!isPowerOf2_32(II->getValue())) { // Don't bother with single bits.
emitInit("SDOperand " + RootName + "0" + " = " +
emitInit("SDValue " + RootName + "0" + " = " +
RootName + ".getOperand(" + utostr(0) + ");");
emitInit("SDOperand " + RootName + "1" + " = " +
emitInit("SDValue " + RootName + "1" + " = " +
RootName + ".getOperand(" + utostr(1) + ");");
emitCheck("isa<ConstantSDNode>(" + RootName + "1)");
@ -597,7 +597,7 @@ public:
}
for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, ++OpNo) {
emitInit("SDOperand " + RootName + utostr(OpNo) + " = " +
emitInit("SDValue " + RootName + utostr(OpNo) + " = " +
RootName + ".getOperand(" +utostr(OpNo) + ");");
EmitChildMatchCode(N->getChild(i), N, RootName + utostr(OpNo), RootName,
@ -611,13 +611,13 @@ public:
unsigned NumOps = CP->getNumOperands();
for (unsigned i = 0; i < NumOps; ++i) {
emitDecl("CPTmp" + utostr(i));
emitCode("SDOperand CPTmp" + utostr(i) + ";");
emitCode("SDValue CPTmp" + utostr(i) + ";");
}
if (CP->hasProperty(SDNPHasChain)) {
emitDecl("CPInChain");
emitDecl("Chain" + ChainSuffix);
emitCode("SDOperand CPInChain;");
emitCode("SDOperand Chain" + ChainSuffix + ";");
emitCode("SDValue CPInChain;");
emitCode("SDValue Chain" + ChainSuffix + ";");
}
std::string Code = Fn + "(" + RootName + ", " + RootName;
@ -685,7 +685,7 @@ public:
unsigned NumOps = CP->getNumOperands();
for (unsigned i = 0; i < NumOps; ++i) {
emitDecl("CPTmp" + utostr(i));
emitCode("SDOperand CPTmp" + utostr(i) + ";");
emitCode("SDValue CPTmp" + utostr(i) + ";");
}
if (CP->hasProperty(SDNPHasChain)) {
const SDNodeInfo &PInfo = CGP.getSDNodeInfo(Parent->getOperator());
@ -694,8 +694,8 @@ public:
ChainName = "Chain" + ChainSuffix;
emitDecl("CPInChain");
emitDecl(ChainName);
emitCode("SDOperand CPInChain;");
emitCode("SDOperand " + ChainName + ";");
emitCode("SDValue CPInChain;");
emitCode("SDValue " + ChainName + ";");
}
std::string Code = Fn + "(";
@ -794,7 +794,7 @@ public:
case MVT::i32: CastType = "unsigned"; break;
case MVT::i64: CastType = "uint64_t"; break;
}
emitCode("SDOperand " + TmpVar +
emitCode("SDValue " + TmpVar +
" = CurDAG->getTargetConstant(((" + CastType +
") cast<ConstantSDNode>(" + Val + ")->getValue()), " +
getEnumName(N->getTypeNum(0)) + ");");
@ -806,7 +806,7 @@ public:
} else if (!N->isLeaf() && N->getOperator()->getName() == "fpimm") {
assert(N->getExtTypes().size() == 1 && "Multiple types not handled!");
std::string TmpVar = "Tmp" + utostr(ResNo);
emitCode("SDOperand " + TmpVar +
emitCode("SDValue " + TmpVar +
" = CurDAG->getTargetConstantFP(cast<ConstantFPSDNode>(" +
Val + ")->getValueAPF(), cast<ConstantFPSDNode>(" + Val +
")->getValueType(0));");
@ -820,7 +820,7 @@ public:
// Transform ExternalSymbol to TargetExternalSymbol
if (Op && Op->getName() == "externalsym") {
std::string TmpVar = "Tmp"+utostr(ResNo);
emitCode("SDOperand " + TmpVar + " = CurDAG->getTarget"
emitCode("SDValue " + TmpVar + " = CurDAG->getTarget"
"ExternalSymbol(cast<ExternalSymbolSDNode>(" +
Val + ")->getSymbol(), " +
getEnumName(N->getTypeNum(0)) + ");");
@ -837,7 +837,7 @@ public:
if (Op && (Op->getName() == "globaladdr" ||
Op->getName() == "globaltlsaddr")) {
std::string TmpVar = "Tmp" + utostr(ResNo);
emitCode("SDOperand " + TmpVar + " = CurDAG->getTarget"
emitCode("SDValue " + TmpVar + " = CurDAG->getTarget"
"GlobalAddress(cast<GlobalAddressSDNode>(" + Val +
")->getGlobal(), " + getEnumName(N->getTypeNum(0)) +
");");
@ -881,13 +881,13 @@ public:
if (DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue())) {
unsigned ResNo = TmpNo++;
if (DI->getDef()->isSubClassOf("Register")) {
emitCode("SDOperand Tmp" + utostr(ResNo) + " = CurDAG->getRegister(" +
emitCode("SDValue Tmp" + utostr(ResNo) + " = CurDAG->getRegister(" +
getQualifiedName(DI->getDef()) + ", " +
getEnumName(N->getTypeNum(0)) + ");");
NodeOps.push_back("Tmp" + utostr(ResNo));
return NodeOps;
} else if (DI->getDef()->getName() == "zero_reg") {
emitCode("SDOperand Tmp" + utostr(ResNo) +
emitCode("SDValue Tmp" + utostr(ResNo) +
" = CurDAG->getRegister(0, " +
getEnumName(N->getTypeNum(0)) + ");");
NodeOps.push_back("Tmp" + utostr(ResNo));
@ -896,7 +896,7 @@ public:
} else if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) {
unsigned ResNo = TmpNo++;
assert(N->getExtTypes().size() == 1 && "Multiple types not handled!");
emitCode("SDOperand Tmp" + utostr(ResNo) +
emitCode("SDValue Tmp" + utostr(ResNo) +
" = CurDAG->getTargetConstant(0x" + itohexstr(II->getValue()) +
"ULL, " + getEnumName(N->getTypeNum(0)) + ");");
NodeOps.push_back("Tmp" + utostr(ResNo));
@ -948,7 +948,7 @@ public:
"(N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);");
}
if (IsVariadic)
emitCode("SmallVector<SDOperand, 8> Ops" + utostr(OpcNo) + ";");
emitCode("SmallVector<SDValue, 8> Ops" + utostr(OpcNo) + ";");
// How many results is this pattern expected to produce?
unsigned NumPatResults = 0;
@ -964,7 +964,7 @@ public:
// TokenFactor with it and the chain of the folded op as the new chain.
// We could potentially be doing multiple levels of folding, in that
// case, the TokenFactor can have more operands.
emitCode("SmallVector<SDOperand, 8> InChains;");
emitCode("SmallVector<SDValue, 8> InChains;");
for (unsigned i = 0, e = OrigChains.size(); i < e; ++i) {
emitCode("if (" + OrigChains[i].first + ".Val != " +
OrigChains[i].second + ".Val) {");
@ -1022,7 +1022,7 @@ public:
InFlagDecled, ResNodeDecled, true);
if (NodeHasOptInFlag || NodeHasInFlag || HasImpInputs) {
if (!InFlagDecled) {
emitCode("SDOperand InFlag(0, 0);");
emitCode("SDValue InFlag(0, 0);");
InFlagDecled = true;
}
if (NodeHasOptInFlag) {
@ -1042,7 +1042,7 @@ public:
std::string NodeName;
if (!isRoot) {
NodeName = "Tmp" + utostr(ResNo);
CodePrefix = "SDOperand " + NodeName + "(";
CodePrefix = "SDValue " + NodeName + "(";
} else {
NodeName = "ResNode";
if (!ResNodeDecled) {
@ -1103,7 +1103,7 @@ public:
if (II.isSimpleLoad | II.mayLoad | II.mayStore) {
std::vector<std::string>::const_iterator mi, mie;
for (mi = LSI.begin(), mie = LSI.end(); mi != mie; ++mi) {
emitCode("SDOperand LSI_" + *mi + " = "
emitCode("SDValue LSI_" + *mi + " = "
"CurDAG->getMemOperand(cast<MemSDNode>(" +
*mi + ")->getMemOperand());");
if (IsVariadic)
@ -1138,7 +1138,7 @@ public:
for (unsigned i = 0; i != NumOps; ++i)
Code += ", " + AllOps[i];
} else {
std::string OpsCode = "SDOperand Ops" + utostr(OpsNo) + "[] = { ";
std::string OpsCode = "SDValue Ops" + utostr(OpsNo) + "[] = { ";
for (unsigned i = 0; i != NumOps; ++i) {
OpsCode += AllOps[i];
if (i != NumOps-1)
@ -1165,12 +1165,12 @@ public:
if (NodeHasOutFlag) {
if (!InFlagDecled) {
After.push_back("SDOperand InFlag(ResNode, " +
After.push_back("SDValue InFlag(ResNode, " +
utostr(NumResults+NumDstRegs+(unsigned)NodeHasChain) +
");");
InFlagDecled = true;
} else
After.push_back("InFlag = SDOperand(ResNode, " +
After.push_back("InFlag = SDValue(ResNode, " +
utostr(NumResults+NumDstRegs+(unsigned)NodeHasChain) +
");");
}
@ -1178,23 +1178,23 @@ public:
if (FoldedChains.size() > 0) {
std::string Code;
for (unsigned j = 0, e = FoldedChains.size(); j < e; j++) {
ReplaceFroms.push_back("SDOperand(" +
ReplaceFroms.push_back("SDValue(" +
FoldedChains[j].first + ".Val, " +
utostr(FoldedChains[j].second) +
")");
ReplaceTos.push_back("SDOperand(ResNode, " +
ReplaceTos.push_back("SDValue(ResNode, " +
utostr(NumResults+NumDstRegs) + ")");
}
}
if (NodeHasOutFlag) {
if (FoldedFlag.first != "") {
ReplaceFroms.push_back("SDOperand(" + FoldedFlag.first + ".Val, " +
ReplaceFroms.push_back("SDValue(" + FoldedFlag.first + ".Val, " +
utostr(FoldedFlag.second) + ")");
ReplaceTos.push_back("InFlag");
} else {
assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP));
ReplaceFroms.push_back("SDOperand(N.Val, " +
ReplaceFroms.push_back("SDValue(N.Val, " +
utostr(NumPatResults + (unsigned)InputHasChain)
+ ")");
ReplaceTos.push_back("InFlag");
@ -1202,9 +1202,9 @@ public:
}
if (!ReplaceFroms.empty() && InputHasChain) {
ReplaceFroms.push_back("SDOperand(N.Val, " +
ReplaceFroms.push_back("SDValue(N.Val, " +
utostr(NumPatResults) + ")");
ReplaceTos.push_back("SDOperand(" + ChainName + ".Val, " +
ReplaceTos.push_back("SDValue(" + ChainName + ".Val, " +
ChainName + ".ResNo" + ")");
ChainAssignmentNeeded |= NodeHasChain;
}
@ -1215,12 +1215,12 @@ public:
} else if (InputHasChain && !NodeHasChain) {
// One of the inner node produces a chain.
if (NodeHasOutFlag) {
ReplaceFroms.push_back("SDOperand(N.Val, " +
ReplaceFroms.push_back("SDValue(N.Val, " +
utostr(NumPatResults+1) +
")");
ReplaceTos.push_back("SDOperand(ResNode, N.ResNo-1)");
ReplaceTos.push_back("SDValue(ResNode, N.ResNo-1)");
}
ReplaceFroms.push_back("SDOperand(N.Val, " +
ReplaceFroms.push_back("SDValue(N.Val, " +
utostr(NumPatResults) + ")");
ReplaceTos.push_back(ChainName);
}
@ -1230,10 +1230,10 @@ public:
// Remember which op produces the chain.
std::string ChainAssign;
if (!isRoot)
ChainAssign = ChainName + " = SDOperand(" + NodeName +
ChainAssign = ChainName + " = SDValue(" + NodeName +
".Val, " + utostr(NumResults+NumDstRegs) + ");";
else
ChainAssign = ChainName + " = SDOperand(" + NodeName +
ChainAssign = ChainName + " = SDValue(" + NodeName +
", " + utostr(NumResults+NumDstRegs) + ");";
After.push_front(ChainAssign);
@ -1243,11 +1243,11 @@ public:
After.push_back("ReplaceUses(" + ReplaceFroms[0] + ", " +
ReplaceTos[0] + ");");
} else if (!ReplaceFroms.empty()) {
After.push_back("const SDOperand Froms[] = {");
After.push_back("const SDValue Froms[] = {");
for (unsigned i = 0, e = ReplaceFroms.size(); i != e; ++i)
After.push_back(" " + ReplaceFroms[i] + (i + 1 != e ? "," : ""));
After.push_back("};");
After.push_back("const SDOperand Tos[] = {");
After.push_back("const SDValue Tos[] = {");
for (unsigned i = 0, e = ReplaceFroms.size(); i != e; ++i)
After.push_back(" " + ReplaceTos[i] + (i + 1 != e ? "," : ""));
After.push_back("};");
@ -1288,7 +1288,7 @@ public:
EmitResultCode(N->getChild(0), DstRegs, InFlagDecled,
ResNodeDecled, true);
unsigned ResNo = TmpNo++;
emitCode("SDOperand Tmp" + utostr(ResNo) + " = Transform_" + Op->getName()
emitCode("SDValue Tmp" + utostr(ResNo) + " = Transform_" + Op->getName()
+ "(" + Ops.back() + ".Val);");
NodeOps.push_back("Tmp" + utostr(ResNo));
if (isRoot)
@ -1356,20 +1356,20 @@ private:
MVT::SimpleValueType RVT = getRegisterValueType(RR, T);
if (RVT == MVT::Flag) {
if (!InFlagDecled) {
emitCode("SDOperand InFlag = " + RootName + utostr(OpNo) + ";");
emitCode("SDValue InFlag = " + RootName + utostr(OpNo) + ";");
InFlagDecled = true;
} else
emitCode("InFlag = " + RootName + utostr(OpNo) + ";");
emitCode("AddToISelQueue(InFlag);");
} else {
if (!ChainEmitted) {
emitCode("SDOperand Chain = CurDAG->getEntryNode();");
emitCode("SDValue Chain = CurDAG->getEntryNode();");
ChainName = "Chain";
ChainEmitted = true;
}
emitCode("AddToISelQueue(" + RootName + utostr(OpNo) + ");");
if (!InFlagDecled) {
emitCode("SDOperand InFlag(0, 0);");
emitCode("SDValue InFlag(0, 0);");
InFlagDecled = true;
}
std::string Decl = (!ResNodeDecled) ? "SDNode *" : "";
@ -1377,8 +1377,8 @@ private:
", " + getQualifiedName(RR) +
", " + RootName + utostr(OpNo) + ", InFlag).Val;");
ResNodeDecled = true;
emitCode(ChainName + " = SDOperand(ResNode, 0);");
emitCode("InFlag = SDOperand(ResNode, 1);");
emitCode(ChainName + " = SDValue(ResNode, 0);");
emitCode("InFlag = SDValue(ResNode, 1);");
}
}
}
@ -1387,7 +1387,7 @@ private:
if (HasInFlag) {
if (!InFlagDecled) {
emitCode("SDOperand InFlag = " + RootName +
emitCode("SDValue InFlag = " + RootName +
".getOperand(" + utostr(OpNo) + ");");
InFlagDecled = true;
} else
@ -1767,7 +1767,7 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
AddedInits.push_back(GeneratedCode[j].second);
}
std::string CalleeCode = "(const SDOperand &N";
std::string CalleeCode = "(const SDValue &N";
std::string CallerCode = "(N";
for (unsigned j = 0, e = TargetOpcodes.size(); j != e; ++j) {
CalleeCode += ", unsigned Opc" + utostr(j);
@ -1780,7 +1780,7 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
for (std::set<std::string>::iterator
I = Decls.begin(), E = Decls.end(); I != E; ++I) {
std::string Name = *I;
CalleeCode += ", SDOperand &" + Name;
CalleeCode += ", SDValue &" + Name;
CallerCode += ", " + Name;
}
@ -1845,7 +1845,7 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
OpVTI->second.push_back(OpVTStr);
OS << "SDNode *Select_" << getLegalCName(OpName)
<< OpVTStr << "(const SDOperand &N) {\n";
<< OpVTStr << "(const SDValue &N) {\n";
// Loop through and reverse all of the CodeList vectors, as we will be
// accessing them from their logical front, but accessing the end of a
@ -1884,8 +1884,8 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
}
// Emit boilerplate.
OS << "SDNode *Select_INLINEASM(SDOperand N) {\n"
<< " std::vector<SDOperand> Ops(N.Val->op_begin(), N.Val->op_end());\n"
OS << "SDNode *Select_INLINEASM(SDValue N) {\n"
<< " std::vector<SDValue> Ops(N.Val->op_begin(), N.Val->op_end());\n"
<< " SelectInlineAsmMemoryOperands(Ops, *CurDAG);\n\n"
<< " // Ensure that the asm operands are themselves selected.\n"
@ -1895,38 +1895,38 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
<< " std::vector<MVT> VTs;\n"
<< " VTs.push_back(MVT::Other);\n"
<< " VTs.push_back(MVT::Flag);\n"
<< " SDOperand New = CurDAG->getNode(ISD::INLINEASM, VTs, &Ops[0], "
<< " SDValue New = CurDAG->getNode(ISD::INLINEASM, VTs, &Ops[0], "
"Ops.size());\n"
<< " return New.Val;\n"
<< "}\n\n";
OS << "SDNode *Select_UNDEF(const SDOperand &N) {\n"
OS << "SDNode *Select_UNDEF(const SDValue &N) {\n"
<< " return CurDAG->SelectNodeTo(N.Val, TargetInstrInfo::IMPLICIT_DEF,\n"
<< " N.getValueType());\n"
<< "}\n\n";
OS << "SDNode *Select_DBG_LABEL(const SDOperand &N) {\n"
<< " SDOperand Chain = N.getOperand(0);\n"
OS << "SDNode *Select_DBG_LABEL(const SDValue &N) {\n"
<< " SDValue Chain = N.getOperand(0);\n"
<< " unsigned C = cast<LabelSDNode>(N)->getLabelID();\n"
<< " SDOperand Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
<< " SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
<< " AddToISelQueue(Chain);\n"
<< " return CurDAG->SelectNodeTo(N.Val, TargetInstrInfo::DBG_LABEL,\n"
<< " MVT::Other, Tmp, Chain);\n"
<< "}\n\n";
OS << "SDNode *Select_EH_LABEL(const SDOperand &N) {\n"
<< " SDOperand Chain = N.getOperand(0);\n"
OS << "SDNode *Select_EH_LABEL(const SDValue &N) {\n"
<< " SDValue Chain = N.getOperand(0);\n"
<< " unsigned C = cast<LabelSDNode>(N)->getLabelID();\n"
<< " SDOperand Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
<< " SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
<< " AddToISelQueue(Chain);\n"
<< " return CurDAG->SelectNodeTo(N.Val, TargetInstrInfo::EH_LABEL,\n"
<< " MVT::Other, Tmp, Chain);\n"
<< "}\n\n";
OS << "SDNode *Select_DECLARE(const SDOperand &N) {\n"
<< " SDOperand Chain = N.getOperand(0);\n"
<< " SDOperand N1 = N.getOperand(1);\n"
<< " SDOperand N2 = N.getOperand(2);\n"
OS << "SDNode *Select_DECLARE(const SDValue &N) {\n"
<< " SDValue Chain = N.getOperand(0);\n"
<< " SDValue N1 = N.getOperand(1);\n"
<< " SDValue N2 = N.getOperand(2);\n"
<< " if (!isa<FrameIndexSDNode>(N1) || !isa<GlobalAddressSDNode>(N2)) {\n"
<< " cerr << \"Cannot yet select llvm.dbg.declare: \";\n"
<< " N.Val->dump(CurDAG);\n"
@ -1934,31 +1934,31 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
<< " }\n"
<< " int FI = cast<FrameIndexSDNode>(N1)->getIndex();\n"
<< " GlobalValue *GV = cast<GlobalAddressSDNode>(N2)->getGlobal();\n"
<< " SDOperand Tmp1 = "
<< " SDValue Tmp1 = "
<< "CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());\n"
<< " SDOperand Tmp2 = "
<< " SDValue Tmp2 = "
<< "CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());\n"
<< " AddToISelQueue(Chain);\n"
<< " return CurDAG->SelectNodeTo(N.Val, TargetInstrInfo::DECLARE,\n"
<< " MVT::Other, Tmp1, Tmp2, Chain);\n"
<< "}\n\n";
OS << "SDNode *Select_EXTRACT_SUBREG(const SDOperand &N) {\n"
<< " SDOperand N0 = N.getOperand(0);\n"
<< " SDOperand N1 = N.getOperand(1);\n"
OS << "SDNode *Select_EXTRACT_SUBREG(const SDValue &N) {\n"
<< " SDValue N0 = N.getOperand(0);\n"
<< " SDValue N1 = N.getOperand(1);\n"
<< " unsigned C = cast<ConstantSDNode>(N1)->getValue();\n"
<< " SDOperand Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
<< " SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
<< " AddToISelQueue(N0);\n"
<< " return CurDAG->SelectNodeTo(N.Val, TargetInstrInfo::EXTRACT_SUBREG,\n"
<< " N.getValueType(), N0, Tmp);\n"
<< "}\n\n";
OS << "SDNode *Select_INSERT_SUBREG(const SDOperand &N) {\n"
<< " SDOperand N0 = N.getOperand(0);\n"
<< " SDOperand N1 = N.getOperand(1);\n"
<< " SDOperand N2 = N.getOperand(2);\n"
OS << "SDNode *Select_INSERT_SUBREG(const SDValue &N) {\n"
<< " SDValue N0 = N.getOperand(0);\n"
<< " SDValue N1 = N.getOperand(1);\n"
<< " SDValue N2 = N.getOperand(2);\n"
<< " unsigned C = cast<ConstantSDNode>(N2)->getValue();\n"
<< " SDOperand Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
<< " SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
<< " AddToISelQueue(N1);\n"
<< " AddToISelQueue(N0);\n"
<< " return CurDAG->SelectNodeTo(N.Val, TargetInstrInfo::INSERT_SUBREG,\n"
@ -1966,7 +1966,7 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
<< "}\n\n";
OS << "// The main instruction selector code.\n"
<< "SDNode *SelectCode(SDOperand N) {\n"
<< "SDNode *SelectCode(SDValue N) {\n"
<< " if (N.isMachineOpcode()) {\n"
<< " return NULL; // Already selected.\n"
<< " }\n\n"