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[Target] Remove the AvailableRegClasses vector from TargetLoweringBase. It was a private member with no code reading from it.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280647 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2016-09-05 06:43:00 +00:00
parent ac396ea37f
commit 481ecf26d0
1 changed files with 0 additions and 4 deletions
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4
include/llvm/Target/TargetLowering.h
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@ -1409,15 +1409,12 @@ protected:
/// that class natively.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
AvailableRegClasses.push_back(std::make_pair(VT, RC));
RegClassForVT[VT.SimpleTy] = RC;
}
/// Remove all register classes.
void clearRegisterClasses() {
std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
AvailableRegClasses.clear();
}
/// \brief Remove all operation actions.
@ -2064,7 +2061,6 @@ private:
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
private:
std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
/// Targets can specify ISD nodes that they would like PerformDAGCombine
/// callbacks for by calling setTargetDAGCombine(), which sets a bit in this