RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2025-02-13 06:34:24 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[AMDGPU][mc] Add support for ds_add_[rtn_]f32.

Browse Source 
Lit tests added.
Resolves https://github.com/RadeonOpenCompute/hcc/issues/122.

Differential Revision: https://reviews.llvm.org/D24765

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282086 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Artem Tamazov 2016-09-21 16:35:44 +00:00
parent aa30d2cf71
commit 4836a1b361
2 changed files with 20 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/Target/AMDGPU/DSInstructions.td
View File

@ -245,6 +245,7 @@ def DS_MAX_U32 : DS_1A1D_NORET<"ds_max_u32">;
def DS_AND_B32 : DS_1A1D_NORET<"ds_and_b32">;
def DS_OR_B32 : DS_1A1D_NORET<"ds_or_b32">;
def DS_XOR_B32 : DS_1A1D_NORET<"ds_xor_b32">;
def DS_ADD_F32 : DS_1A1D_NORET<"ds_add_f32">;
let mayLoad = 0 in {
def DS_WRITE_B8 : DS_1A1D_NORET<"ds_write_b8">;
@ -285,6 +286,8 @@ def DS_MAX_F64 : DS_1A1D_NORET<"ds_max_f64", VReg_64>;
def DS_ADD_RTN_U32 : DS_1A1D_RET<"ds_add_rtn_u32">,
AtomicNoRet<"ds_add_u32", 1>;
def DS_ADD_RTN_F32 : DS_1A1D_RET<"ds_add_rtn_f32">,
AtomicNoRet<"ds_add_f32", 1>;
def DS_SUB_RTN_U32 : DS_1A1D_RET<"ds_sub_rtn_u32">,
AtomicNoRet<"ds_sub_u32", 1>;
def DS_RSUB_RTN_U32 : DS_1A1D_RET<"ds_rsub_rtn_u32">,
@ -777,6 +780,7 @@ def DS_CMPST_B32_vi : DS_Real_vi<0x10, DS_CMPST_B32>;
def DS_CMPST_F32_vi : DS_Real_vi<0x11, DS_CMPST_F32>;
def DS_MIN_F32_vi : DS_Real_vi<0x12, DS_MIN_F32>;
def DS_MAX_F32_vi : DS_Real_vi<0x13, DS_MAX_F32>;
def DS_ADD_F32_vi : DS_Real_vi<0x15, DS_ADD_F32>;
def DS_GWS_INIT_vi : DS_Real_vi<0x19, DS_GWS_INIT>;
def DS_GWS_SEMA_V_vi : DS_Real_vi<0x1a, DS_GWS_SEMA_V>;
def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x1b, DS_GWS_SEMA_BR>;
@ -805,6 +809,7 @@ def DS_CMPST_RTN_F32_vi : DS_Real_vi<0x31, DS_CMPST_RTN_F32>;
def DS_MIN_RTN_F32_vi : DS_Real_vi<0x32, DS_MIN_RTN_F32>;
def DS_MAX_RTN_F32_vi : DS_Real_vi<0x33, DS_MAX_RTN_F32>;
def DS_WRAP_RTN_F32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_F32>;
def DS_ADD_RTN_F32_vi : DS_Real_vi<0x35, DS_ADD_RTN_F32>;
def DS_READ_B32_vi : DS_Real_vi<0x36, DS_READ_B32>;
def DS_READ2_B32_vi : DS_Real_vi<0x37, DS_READ2_B32>;
def DS_READ2ST64_B32_vi : DS_Real_vi<0x38, DS_READ2ST64_B32>;

17
test/MC/AMDGPU/ds.s
View File

@ -1,7 +1,12 @@
// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s --check-prefix=SICI
// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SI --check-prefix=SICI
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=SI --check-prefix=SICI
// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=CI --check-prefix=SICI
// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=VI
// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI
// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOCI --check-prefix=NOSICI
//===----------------------------------------------------------------------===//
// Checks for 16-bit Offsets
//===----------------------------------------------------------------------===//
@ -54,6 +59,10 @@ ds_add_u32 v2, v4
// SICI: ds_add_u32 v2, v4 ; encoding: [0x00,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
// VI: ds_add_u32 v2, v4 ; encoding: [0x00,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
ds_add_f32 v2, v4
// NOSICI: error: instruction not supported on this GPU
// VI: ds_add_f32 v2, v4 ; encoding: [0x00,0x00,0x2a,0xd8,0x02,0x04,0x00,0x00]
ds_sub_u32 v2, v4
// SICI: ds_sub_u32 v2, v4 ; encoding: [0x00,0x00,0x04,0xd8,0x02,0x04,0x00,0x00]
// VI: ds_sub_u32 v2, v4 ; encoding: [0x00,0x00,0x02,0xd8,0x02,0x04,0x00,0x00]
@ -162,6 +171,10 @@ ds_add_rtn_u32 v8, v2, v4
// SICI: ds_add_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x80,0xd8,0x02,0x04,0x00,0x08]
// VI: ds_add_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x40,0xd8,0x02,0x04,0x00,0x08]
ds_add_rtn_f32 v8, v2, v4
// NOSICI: error: instruction not supported on this GPU
// VI: ds_add_rtn_f32 v8, v2, v4 ; encoding: [0x00,0x00,0x6a,0xd8,0x02,0x04,0x00,0x08]
ds_sub_rtn_u32 v8, v2, v4
// SICI: ds_sub_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x84,0xd8,0x02,0x04,0x00,0x08]
// VI: ds_sub_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x42,0xd8,0x02,0x04,0x00,0x08]