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Indexing off by one resulted in errant encoding of source register for

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reg->reg moves.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57011 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2008-10-03 15:53:56 +00:00
parent 016d34cc4c
commit 48b828fdb4
1 changed files with 1 additions and 1 deletions
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2
lib/Target/ARM/ARMCodeEmitter.cpp
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@ -416,7 +416,7 @@ unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
const MachineOperand &MO = MI.getOperand(OpIdx);
if (MO.isReg())
// Encode register Rm.
return Binary | getMachineOpValue(MI, NumDefs + 1);
return Binary | getMachineOpValue(MI, NumDefs);
// Encode so_imm.
// Set bit I(25) to identify this is the immediate form of <shifter_op>