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[X86] Avoid generating inc/dec when slow for x.atomic_store(1 + x.atomic_load())
Summary: I had forgotten to check for NotSlowIncDec in the patterns that can generate inc/dec for the above pattern (added in D4796). This currently applies to Atom Silvermont, KNL and SKX. Test Plan: New checks on atomic_mi.ll Reviewers: jfb, nadav Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5677 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219336 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -800,12 +800,12 @@ defm RELEASE_INC : RELEASE_UNOP<
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(add (atomic_load_8 addr:$dst), (i8 1)),
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(add (atomic_load_16 addr:$dst), (i16 1)),
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(add (atomic_load_32 addr:$dst), (i32 1)),
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(add (atomic_load_64 addr:$dst), (i64 1))>;
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(add (atomic_load_64 addr:$dst), (i64 1))>, Requires<[NotSlowIncDec]>;
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defm RELEASE_DEC : RELEASE_UNOP<
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(add (atomic_load_8 addr:$dst), (i8 -1)),
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(add (atomic_load_16 addr:$dst), (i16 -1)),
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(add (atomic_load_32 addr:$dst), (i32 -1)),
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(add (atomic_load_64 addr:$dst), (i64 -1))>;
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(add (atomic_load_64 addr:$dst), (i64 -1))>, Requires<[NotSlowIncDec]>;
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/*
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TODO: These don't work because the type inference of TableGen fails.
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TODO: find a way to fix it.
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@ -1,5 +1,6 @@
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; RUN: llc < %s -march=x86-64 -verify-machineinstrs | FileCheck %s --check-prefix X64
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; RUN: llc < %s -march=x86 -verify-machineinstrs | FileCheck %s --check-prefix X32
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; RUN: llc < %s -march=x86-64 -mattr=slow-incdec -verify-machineinstrs | FileCheck %s --check-prefix SLOW_INC
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; This file checks that atomic (non-seq_cst) stores of immediate values are
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; done in one mov instruction and not 2. More precisely, it makes sure that the
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@ -374,6 +375,9 @@ define void @inc_8(i8* %p) {
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; X32-NOT: lock
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; X32: incb
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; X32-NOT: movb
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; SLOW_INC-LABEL: inc_8
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; SLOW_INC-NOT: incb
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; SLOW_INC-NOT: movb
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%1 = load atomic i8* %p seq_cst, align 1
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%2 = add i8 %1, 1
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store atomic i8 %2, i8* %p release, align 1
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@ -387,6 +391,8 @@ define void @inc_16(i16* %p) {
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; X64-NOT: incw
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; X32-LABEL: inc_16
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; X32-NOT: incw
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; SLOW_INC-LABEL: inc_16
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; SLOW_INC-NOT: incw
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%1 = load atomic i16* %p acquire, align 2
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%2 = add i16 %1, 1
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store atomic i16 %2, i16* %p release, align 2
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@ -402,6 +408,9 @@ define void @inc_32(i32* %p) {
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; X32-NOT: lock
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; X32: incl
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; X32-NOT: movl
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; SLOW_INC-LABEL: inc_32
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; SLOW_INC-NOT: incl
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; SLOW_INC-NOT: movl
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%1 = load atomic i32* %p acquire, align 4
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%2 = add i32 %1, 1
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store atomic i32 %2, i32* %p monotonic, align 4
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@ -415,6 +424,9 @@ define void @inc_64(i64* %p) {
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; X64-NOT: movq
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; We do not check X86-32 as it cannot do 'incq'.
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; X32-LABEL: inc_64
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; SLOW_INC-LABEL: inc_64
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; SLOW_INC-NOT: incq
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; SLOW_INC-NOT: movq
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%1 = load atomic i64* %p acquire, align 8
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%2 = add i64 %1, 1
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store atomic i64 %2, i64* %p release, align 8
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@ -443,6 +455,9 @@ define void @dec_8(i8* %p) {
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; X32-NOT: lock
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; X32: decb
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; X32-NOT: movb
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; SLOW_INC-LABEL: dec_8
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; SLOW_INC-NOT: decb
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; SLOW_INC-NOT: movb
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%1 = load atomic i8* %p seq_cst, align 1
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%2 = sub i8 %1, 1
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store atomic i8 %2, i8* %p release, align 1
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@ -456,6 +471,8 @@ define void @dec_16(i16* %p) {
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; X64-NOT: decw
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; X32-LABEL: dec_16
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; X32-NOT: decw
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; SLOW_INC-LABEL: dec_16
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; SLOW_INC-NOT: decw
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%1 = load atomic i16* %p acquire, align 2
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%2 = sub i16 %1, 1
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store atomic i16 %2, i16* %p release, align 2
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@ -471,6 +488,9 @@ define void @dec_32(i32* %p) {
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; X32-NOT: lock
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; X32: decl
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; X32-NOT: movl
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; SLOW_INC-LABEL: dec_32
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; SLOW_INC-NOT: decl
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; SLOW_INC-NOT: movl
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%1 = load atomic i32* %p acquire, align 4
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%2 = sub i32 %1, 1
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store atomic i32 %2, i32* %p monotonic, align 4
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@ -484,6 +504,9 @@ define void @dec_64(i64* %p) {
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; X64-NOT: movq
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; We do not check X86-32 as it cannot do 'decq'.
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; X32-LABEL: dec_64
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; SLOW_INC-LABEL: dec_64
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; SLOW_INC-NOT: decq
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; SLOW_INC-NOT: movq
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%1 = load atomic i64* %p acquire, align 8
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%2 = sub i64 %1, 1
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store atomic i64 %2, i64* %p release, align 8
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