diff --git a/lib/Target/Alpha/Alpha.h b/lib/Target/Alpha/Alpha.h index 1b369066212..8884af224d4 100644 --- a/lib/Target/Alpha/Alpha.h +++ b/lib/Target/Alpha/Alpha.h @@ -24,6 +24,7 @@ namespace llvm { class MachineCodeEmitter; FunctionPass *createAlphaSimpleInstructionSelector(TargetMachine &TM); + FunctionPass *createAlphaISelDag(TargetMachine &TM); FunctionPass *createAlphaCodePrinterPass(std::ostream &OS, TargetMachine &TM); FunctionPass *createAlphaPatternInstructionSelector(TargetMachine &TM); diff --git a/lib/Target/Alpha/AlphaISelLowering.h b/lib/Target/Alpha/AlphaISelLowering.h index 6041c5d4544..2edad0f58a7 100644 --- a/lib/Target/Alpha/AlphaISelLowering.h +++ b/lib/Target/Alpha/AlphaISelLowering.h @@ -21,6 +21,13 @@ namespace llvm { + namespace AlphaISD { + enum NodeType { + // Start the numbering where the builting ops and target ops leave off. + FIRST_NUMBER = ISD::BUILTIN_OP_END+Alpha::INSTRUCTION_LIST_END, + }; + } + class AlphaTargetLowering : public TargetLowering { int VarArgsOffset; // What is the offset to the first vaarg int VarArgsBase; // What is the base FrameIndex diff --git a/lib/Target/Alpha/AlphaInstrFormats.td b/lib/Target/Alpha/AlphaInstrFormats.td index f01e9072602..7e8e58a80c2 100644 --- a/lib/Target/Alpha/AlphaInstrFormats.td +++ b/lib/Target/Alpha/AlphaInstrFormats.td @@ -17,10 +17,10 @@ //Floating-point //PALcode -def u8imm : Operand; -def s14imm : Operand; -def s16imm : Operand; -def s21imm : Operand; +def u8imm : Operand; +def s14imm : Operand; +def s16imm : Operand; +def s21imm : Operand; def s64imm : Operand; //===----------------------------------------------------------------------===// @@ -93,8 +93,10 @@ class FBForm opcode, string asmstr> } //3.3.3 -class OForm opcode, bits<7> fun, string asmstr> +class OForm opcode, bits<7> fun, string asmstr, list pattern> : InstAlpha { + let Pattern = pattern; + bits<5> Rc; bits<5> Ra; bits<5> Rb; @@ -124,8 +126,10 @@ class OcmForm opcode, bits<7> fun, dag OL, string asmstr> } -class OFormL opcode, bits<7> fun, string asmstr> +class OFormL opcode, bits<7> fun, string asmstr, list pattern> : InstAlpha { + let Pattern = pattern; + bits<5> Rc; bits<5> Ra; bits<8> LIT; diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td index f355a12f235..1e6b7b041dc 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.td +++ b/lib/Target/Alpha/AlphaInstrInfo.td @@ -12,6 +12,24 @@ include "AlphaInstrFormats.td" +//******************** +//Paterns for matching +//******************** +def immUExt8 : PatLeaf<(imm), [{ + // immUExt8 predicate - True if the immediate fits in a 8-bit zero extended + // field. Used by instructions like 'addi'. + return (unsigned long)N->getValue() == (unsigned char)N->getValue(); +}]>; +def imm2 : PatLeaf<(imm), [{ + // imm2 predicate - True if the immediate is a 2 + return N->getValue() == 2; +}]>; +def imm3 : PatLeaf<(imm), [{ + // imm3 predicate - True if the immediate is a 3 + return N->getValue() == 3; +}]>; + + // //#define FP $15 // //#define RA $26 // //#define PV $27 @@ -112,124 +130,172 @@ let isTwoAddress = 1 in { "fcmovne $RCOND,$RSRC,$RDEST">; //FCMOVE if != zero } -def ADDL : OForm< 0x10, 0x00, "addl $RA,$RB,$RC">; //Add longword -def ADDLi : OFormL<0x10, 0x00, "addl $RA,$L,$RC">; //Add longword -def ADDQ : OForm< 0x10, 0x20, "addq $RA,$RB,$RC">; //Add quadword -def ADDQi : OFormL<0x10, 0x20, "addq $RA,$L,$RC">; //Add quadword -def AMASK : OForm< 0x11, 0x61, "AMASK $RA,$RB,$RC">; //Architecture mask -def AMASKi : OFormL<0x11, 0x61, "AMASK $RA,$L,$RC">; //Architecture mask -def AND : OForm< 0x11, 0x00, "and $RA,$RB,$RC">; //Logical product -def ANDi : OFormL<0x11, 0x00, "and $RA,$L,$RC">; //Logical product -def BIC : OForm< 0x11, 0x08, "bic $RA,$RB,$RC">; //Bit clear -def BICi : OFormL<0x11, 0x08, "bic $RA,$L,$RC">; //Bit clear -def BIS : OForm< 0x11, 0x20, "bis $RA,$RB,$RC">; //Logical sum -def BISi : OFormL<0x11, 0x20, "bis $RA,$L,$RC">; //Logical sum -def CTLZ : OForm< 0x1C, 0x32, "CTLZ $RB,$RC">; //Count leading zero -def CTPOP : OForm< 0x1C, 0x30, "CTPOP $RB,$RC">; //Count population -def CTTZ : OForm< 0x1C, 0x33, "CTTZ $RB,$RC">; //Count trailing zero -def EQV : OForm< 0x11, 0x48, "eqv $RA,$RB,$RC">; //Logical equivalence -def EQVi : OFormL<0x11, 0x48, "eqv $RA,$L,$RC">; //Logical equivalence -def EXTBL : OForm< 0x12, 0x06, "EXTBL $RA,$RB,$RC">; //Extract byte low -def EXTBLi : OFormL<0x12, 0x06, "EXTBL $RA,$L,$RC">; //Extract byte low -def EXTLH : OForm< 0x12, 0x6A, "EXTLH $RA,$RB,$RC">; //Extract longword high -def EXTLHi : OFormL<0x12, 0x6A, "EXTLH $RA,$L,$RC">; //Extract longword high -def EXTLL : OForm< 0x12, 0x26, "EXTLL $RA,$RB,$RC">; //Extract longword low -def EXTLLi : OFormL<0x12, 0x26, "EXTLL $RA,$L,$RC">; //Extract longword low -def EXTQH : OForm< 0x12, 0x7A, "EXTQH $RA,$RB,$RC">; //Extract quadword high -def EXTQHi : OFormL<0x12, 0x7A, "EXTQH $RA,$L,$RC">; //Extract quadword high -def EXTQ : OForm< 0x12, 0x36, "EXTQ $RA,$RB,$RC">; //Extract quadword low -def EXTQi : OFormL<0x12, 0x36, "EXTQ $RA,$L,$RC">; //Extract quadword low -def EXTWH : OForm< 0x12, 0x5A, "EXTWH $RA,$RB,$RC">; //Extract word high -def EXTWHi : OFormL<0x12, 0x5A, "EXTWH $RA,$L,$RC">; //Extract word high -def EXTWL : OForm< 0x12, 0x16, "EXTWL $RA,$RB,$RC">; //Extract word low -def EXTWLi : OFormL<0x12, 0x16, "EXTWL $RA,$L,$RC">; //Extract word low -def IMPLVER : OForm< 0x11, 0x6C, "IMPLVER $RA,$RB,$RC">; //Implementation version -def IMPLVERi : OFormL<0x11, 0x6C, "IMPLVER $RA,$L,$RC">; //Implementation version -def INSBL : OForm< 0x12, 0x0B, "INSBL $RA,$RB,$RC">; //Insert byte low -def INSBLi : OFormL<0x12, 0x0B, "INSBL $RA,$L,$RC">; //Insert byte low -def INSLH : OForm< 0x12, 0x67, "INSLH $RA,$RB,$RC">; //Insert longword high -def INSLHi : OFormL<0x12, 0x67, "INSLH $RA,$L,$RC">; //Insert longword high -def INSLL : OForm< 0x12, 0x2B, "INSLL $RA,$RB,$RC">; //Insert longword low -def INSLLi : OFormL<0x12, 0x2B, "INSLL $RA,$L,$RC">; //Insert longword low -def INSQH : OForm< 0x12, 0x77, "INSQH $RA,$RB,$RC">; //Insert quadword high -def INSQHi : OFormL<0x12, 0x77, "INSQH $RA,$L,$RC">; //Insert quadword high -def INSQL : OForm< 0x12, 0x3B, "INSQL $RA,$RB,$RC">; //Insert quadword low -def INSQLi : OFormL<0x12, 0x3B, "INSQL $RA,$L,$RC">; //Insert quadword low -def INSWH : OForm< 0x12, 0x57, "INSWH $RA,$RB,$RC">; //Insert word high -def INSWHi : OFormL<0x12, 0x57, "INSWH $RA,$L,$RC">; //Insert word high -def INSWL : OForm< 0x12, 0x1B, "INSWL $RA,$RB,$RC">; //Insert word low -def INSWLi : OFormL<0x12, 0x1B, "INSWL $RA,$L,$RC">; //Insert word low -def MSKBL : OForm< 0x12, 0x02, "MSKBL $RA,$RB,$RC">; //Mask byte low -def MSKBLi : OFormL<0x12, 0x02, "MSKBL $RA,$L,$RC">; //Mask byte low -def MSKLH : OForm< 0x12, 0x62, "MSKLH $RA,$RB,$RC">; //Mask longword high -def MSKLHi : OFormL<0x12, 0x62, "MSKLH $RA,$L,$RC">; //Mask longword high -def MSKLL : OForm< 0x12, 0x22, "MSKLL $RA,$RB,$RC">; //Mask longword low -def MSKLLi : OFormL<0x12, 0x22, "MSKLL $RA,$L,$RC">; //Mask longword low -def MSKQH : OForm< 0x12, 0x72, "MSKQH $RA,$RB,$RC">; //Mask quadword high -def MSKQHi : OFormL<0x12, 0x72, "MSKQH $RA,$L,$RC">; //Mask quadword high -def MSKQL : OForm< 0x12, 0x32, "MSKQL $RA,$RB,$RC">; //Mask quadword low -def MSKQLi : OFormL<0x12, 0x32, "MSKQL $RA,$L,$RC">; //Mask quadword low -def MSKWH : OForm< 0x12, 0x52, "MSKWH $RA,$RB,$RC">; //Mask word high -def MSKWHi : OFormL<0x12, 0x52, "MSKWH $RA,$L,$RC">; //Mask word high -def MSKWL : OForm< 0x12, 0x12, "MSKWL $RA,$RB,$RC">; //Mask word low -def MSKWLi : OFormL<0x12, 0x12, "MSKWL $RA,$L,$RC">; //Mask word low -def MULL : OForm< 0x13, 0x00, "mull $RA,$RB,$RC">; //Multiply longword -def MULLi : OFormL<0x13, 0x00, "mull $RA,$L,$RC">; //Multiply longword -def MULQ : OForm< 0x13, 0x20, "mulq $RA,$RB,$RC">; //Multiply quadword -def MULQi : OFormL<0x13, 0x20, "mulq $RA,$L,$RC">; //Multiply quadword -def ORNOT : OForm< 0x11, 0x28, "ornot $RA,$RB,$RC">; //Logical sum with complement -def ORNOTi : OFormL<0x11, 0x28, "ornot $RA,$L,$RC">; //Logical sum with complement -def S4ADDL : OForm< 0x10, 0x02, "s4addl $RA,$RB,$RC">; //Scaled add longword by 4 -def S4ADDLi : OFormL<0x10, 0x02, "s4addl $RA,$L,$RC">; //Scaled add longword by 4 -def S4ADDQ : OForm< 0x10, 0x22, "s4addq $RA,$RB,$RC">; //Scaled add quadword by 4 -def S4ADDQi : OFormL<0x10, 0x22, "s4addq $RA,$L,$RC">; //Scaled add quadword by 4 -def S4SUBL : OForm< 0x10, 0x0B, "s4subl $RA,$RB,$RC">; //Scaled subtract longword by 4 -def S4SUBLi : OFormL<0x10, 0x0B, "s4subl $RA,$L,$RC">; //Scaled subtract longword by 4 -def S4SUBQ : OForm< 0x10, 0x2B, "s4subq $RA,$RB,$RC">; //Scaled subtract quadword by 4 -def S4SUBQi : OFormL<0x10, 0x2B, "s4subq $RA,$L,$RC">; //Scaled subtract quadword by 4 -def S8ADDL : OForm< 0x10, 0x12, "s8addl $RA,$RB,$RC">; //Scaled add longword by 8 -def S8ADDLi : OFormL<0x10, 0x12, "s8addl $RA,$L,$RC">; //Scaled add longword by 8 -def S8ADDQ : OForm< 0x10, 0x32, "s8addq $RA,$RB,$RC">; //Scaled add quadword by 8 -def S8ADDQi : OFormL<0x10, 0x32, "s8addq $RA,$L,$RC">; //Scaled add quadword by 8 -def S8SUBL : OForm< 0x10, 0x1B, "s8subl $RA,$RB,$RC">; //Scaled subtract longword by 8 -def S8SUBLi : OFormL<0x10, 0x1B, "s8subl $RA,$L,$RC">; //Scaled subtract longword by 8 -def S8SUBQ : OForm< 0x10, 0x3B, "s8subq $RA,$RB,$RC">; //Scaled subtract quadword by 8 -def S8SUBQi : OFormL<0x10, 0x3B, "s8subq $RA,$L,$RC">; //Scaled subtract quadword by 8 -def SEXTB : OForm< 0x1C, 0x00, "sextb $RB,$RC">; //Sign extend byte -def SEXTW : OForm< 0x1C, 0x01, "sextw $RB,$RC">; //Sign extend word -def SL : OForm< 0x12, 0x39, "sll $RA,$RB,$RC">; //Shift left logical -def SLi : OFormL<0x12, 0x39, "sll $RA,$L,$RC">; //Shift left logical -def SRA : OForm< 0x12, 0x3C, "sra $RA,$RB,$RC">; //Shift right arithmetic -def SRAi : OFormL<0x12, 0x3C, "sra $RA,$L,$RC">; //Shift right arithmetic -def SRL : OForm< 0x12, 0x34, "srl $RA,$RB,$RC">; //Shift right logical +def ADDL : OForm< 0x10, 0x00, "addl $RA,$RB,$RC", + [(set GPRC:$RC, (sext_inreg (add GPRC:$RA, GPRC:$RB), i32))]>; +def ADDLi : OFormL<0x10, 0x00, "addl $RA,$L,$RC", + [(set GPRC:$RC, (sext_inreg (add GPRC:$RA, immUExt8:$L), i32))]>; +def ADDQ : OForm< 0x10, 0x20, "addq $RA,$RB,$RC", + [(set GPRC:$RC, (add GPRC:$RA, GPRC:$RB))]>; +def ADDQi : OFormL<0x10, 0x20, "addq $RA,$L,$RC", + [(set GPRC:$RC, (add GPRC:$RA, immUExt8:$L))]>; +//def AMASK : OForm< 0x11, 0x61, "AMASK $RA,$RB,$RC", []>; //Architecture mask +//def AMASKi : OFormL<0x11, 0x61, "AMASK $RA,$L,$RC", []>; //Architecture mask +def AND : OForm< 0x11, 0x00, "and $RA,$RB,$RC", + [(set GPRC:$RC, (and GPRC:$RA, GPRC:$RB))]>; +def ANDi : OFormL<0x11, 0x00, "and $RA,$L,$RC", + [(set GPRC:$RC, (and GPRC:$RA, immUExt8:$L))]>; +def BIC : OForm< 0x11, 0x08, "bic $RA,$RB,$RC", + [(set GPRC:$RC, (and GPRC:$RA, (not GPRC:$RB)))]>; +def BICi : OFormL<0x11, 0x08, "bic $RA,$L,$RC", []>; +// [(set GPRC:$RC, (and GPRC:$RA, (not immUExt8:$L)))]>; //FIXME? +def BIS : OForm< 0x11, 0x20, "bis $RA,$RB,$RC", + [(set GPRC:$RC, (or GPRC:$RA, GPRC:$RB))]>; +def BISi : OFormL<0x11, 0x20, "bis $RA,$L,$RC", + [(set GPRC:$RC, (or GPRC:$RA, immUExt8:$L))]>; +def CTLZ : OForm< 0x1C, 0x32, "CTLZ $RB,$RC", []>; +// [(set GPRC:$RC, (ctlz GPRC:$RB))]>; +def CTPOP : OForm< 0x1C, 0x30, "CTPOP $RB,$RC", []>; //Count population +def CTTZ : OForm< 0x1C, 0x33, "CTTZ $RB,$RC", []>; //Count trailing zero +def EQV : OForm< 0x11, 0x48, "eqv $RA,$RB,$RC", + [(set GPRC:$RC, (xor GPRC:$RA, (not GPRC:$RB)))]>; +def EQVi : OFormL<0x11, 0x48, "eqv $RA,$L,$RC", []>; +// [(set GPRC:$RC, (xor GPRC:$RA, (not immUExt8:$L)))]>; +//def EXTBL : OForm< 0x12, 0x06, "EXTBL $RA,$RB,$RC", []>; //Extract byte low +//def EXTBLi : OFormL<0x12, 0x06, "EXTBL $RA,$L,$RC", []>; //Extract byte low +//def EXTLH : OForm< 0x12, 0x6A, "EXTLH $RA,$RB,$RC", []>; //Extract longword high +//def EXTLHi : OFormL<0x12, 0x6A, "EXTLH $RA,$L,$RC", []>; //Extract longword high +//def EXTLL : OForm< 0x12, 0x26, "EXTLL $RA,$RB,$RC", []>; //Extract longword low +//def EXTLLi : OFormL<0x12, 0x26, "EXTLL $RA,$L,$RC", []>; //Extract longword low +//def EXTQH : OForm< 0x12, 0x7A, "EXTQH $RA,$RB,$RC", []>; //Extract quadword high +//def EXTQHi : OFormL<0x12, 0x7A, "EXTQH $RA,$L,$RC", []>; //Extract quadword high +//def EXTQ : OForm< 0x12, 0x36, "EXTQ $RA,$RB,$RC", []>; //Extract quadword low +//def EXTQi : OFormL<0x12, 0x36, "EXTQ $RA,$L,$RC", []>; //Extract quadword low +//def EXTWH : OForm< 0x12, 0x5A, "EXTWH $RA,$RB,$RC", []>; //Extract word high +//def EXTWHi : OFormL<0x12, 0x5A, "EXTWH $RA,$L,$RC", []>; //Extract word high +//def EXTWL : OForm< 0x12, 0x16, "EXTWL $RA,$RB,$RC", []>; //Extract word low +//def EXTWLi : OFormL<0x12, 0x16, "EXTWL $RA,$L,$RC", []>; //Extract word low +//def IMPLVER : OForm< 0x11, 0x6C, "IMPLVER $RA,$RB,$RC", []>; //Implementation version +//def IMPLVERi : OFormL<0x11, 0x6C, "IMPLVER $RA,$L,$RC", []>; //Implementation version +//def INSBL : OForm< 0x12, 0x0B, "INSBL $RA,$RB,$RC", []>; //Insert byte low +//def INSBLi : OFormL<0x12, 0x0B, "INSBL $RA,$L,$RC", []>; //Insert byte low +//def INSLH : OForm< 0x12, 0x67, "INSLH $RA,$RB,$RC", []>; //Insert longword high +//def INSLHi : OFormL<0x12, 0x67, "INSLH $RA,$L,$RC", []>; //Insert longword high +//def INSLL : OForm< 0x12, 0x2B, "INSLL $RA,$RB,$RC", []>; //Insert longword low +//def INSLLi : OFormL<0x12, 0x2B, "INSLL $RA,$L,$RC", []>; //Insert longword low +//def INSQH : OForm< 0x12, 0x77, "INSQH $RA,$RB,$RC", []>; //Insert quadword high +//def INSQHi : OFormL<0x12, 0x77, "INSQH $RA,$L,$RC", []>; //Insert quadword high +//def INSQL : OForm< 0x12, 0x3B, "INSQL $RA,$RB,$RC", []>; //Insert quadword low +//def INSQLi : OFormL<0x12, 0x3B, "INSQL $RA,$L,$RC", []>; //Insert quadword low +//def INSWH : OForm< 0x12, 0x57, "INSWH $RA,$RB,$RC", []>; //Insert word high +//def INSWHi : OFormL<0x12, 0x57, "INSWH $RA,$L,$RC", []>; //Insert word high +//def INSWL : OForm< 0x12, 0x1B, "INSWL $RA,$RB,$RC", []>; //Insert word low +//def INSWLi : OFormL<0x12, 0x1B, "INSWL $RA,$L,$RC", []>; //Insert word low +//def MSKBL : OForm< 0x12, 0x02, "MSKBL $RA,$RB,$RC", []>; //Mask byte low +//def MSKBLi : OFormL<0x12, 0x02, "MSKBL $RA,$L,$RC", []>; //Mask byte low +//def MSKLH : OForm< 0x12, 0x62, "MSKLH $RA,$RB,$RC", []>; //Mask longword high +//def MSKLHi : OFormL<0x12, 0x62, "MSKLH $RA,$L,$RC", []>; //Mask longword high +//def MSKLL : OForm< 0x12, 0x22, "MSKLL $RA,$RB,$RC", []>; //Mask longword low +//def MSKLLi : OFormL<0x12, 0x22, "MSKLL $RA,$L,$RC", []>; //Mask longword low +//def MSKQH : OForm< 0x12, 0x72, "MSKQH $RA,$RB,$RC", []>; //Mask quadword high +//def MSKQHi : OFormL<0x12, 0x72, "MSKQH $RA,$L,$RC", []>; //Mask quadword high +//def MSKQL : OForm< 0x12, 0x32, "MSKQL $RA,$RB,$RC", []>; //Mask quadword low +//def MSKQLi : OFormL<0x12, 0x32, "MSKQL $RA,$L,$RC", []>; //Mask quadword low +//def MSKWH : OForm< 0x12, 0x52, "MSKWH $RA,$RB,$RC", []>; //Mask word high +//def MSKWHi : OFormL<0x12, 0x52, "MSKWH $RA,$L,$RC", []>; //Mask word high +//def MSKWL : OForm< 0x12, 0x12, "MSKWL $RA,$RB,$RC", []>; //Mask word low +//def MSKWLi : OFormL<0x12, 0x12, "MSKWL $RA,$L,$RC", []>; //Mask word low +def MULL : OForm< 0x13, 0x00, "mull $RA,$RB,$RC", + [(set GPRC:$RC, (sext_inreg (mul GPRC:$RA, GPRC:$RB), i32))]>; +def MULLi : OFormL<0x13, 0x00, "mull $RA,$L,$RC", + [(set GPRC:$RC, (sext_inreg (mul GPRC:$RA, immUExt8:$L), i32))]>; +def MULQ : OForm< 0x13, 0x20, "mulq $RA,$RB,$RC", + [(set GPRC:$RC, (mul GPRC:$RA, GPRC:$RB))]>; +def MULQi : OFormL<0x13, 0x20, "mulq $RA,$L,$RC", + [(set GPRC:$RC, (mul GPRC:$RA, immUExt8:$L))]>; +def ORNOT : OForm< 0x11, 0x28, "ornot $RA,$RB,$RC", + [(set GPRC:$RC, (or GPRC:$RA, (not GPRC:$RB)))]>; +def ORNOTi : OFormL<0x11, 0x28, "ornot $RA,$L,$RC", []>; +// [(set GPRC:$RC, (or GPRC:$RA, (not immUExt8:$L)))]>; +def S4ADDL : OForm< 0x10, 0x02, "s4addl $RA,$RB,$RC", + [(set GPRC:$RC, (sext_inreg (add (shl GPRC:$RA, imm2), GPRC:$RB), i32))]>; +def S4ADDLi : OFormL<0x10, 0x02, "s4addl $RA,$L,$RC", + [(set GPRC:$RC, (sext_inreg (add (shl GPRC:$RA, imm2), immUExt8:$L), i32))]>; +def S4ADDQ : OForm< 0x10, 0x22, "s4addq $RA,$RB,$RC", + [(set GPRC:$RC, (add (shl GPRC:$RA, imm2), GPRC:$RB))]>; +def S4ADDQi : OFormL<0x10, 0x22, "s4addq $RA,$L,$RC", + [(set GPRC:$RC, (add (shl GPRC:$RA, imm2), immUExt8:$L))]>; +def S4SUBL : OForm< 0x10, 0x0B, "s4subl $RA,$RB,$RC", + [(set GPRC:$RC, (sext_inreg (sub (shl GPRC:$RA, imm2), GPRC:$RB), i32))]>; +def S4SUBLi : OFormL<0x10, 0x0B, "s4subl $RA,$L,$RC", + [(set GPRC:$RC, (sext_inreg (sub (shl GPRC:$RA, imm2), immUExt8:$L), i32))]>; +def S4SUBQ : OForm< 0x10, 0x2B, "s4subq $RA,$RB,$RC", + [(set GPRC:$RC, (sub (shl GPRC:$RA, imm2), GPRC:$RB))]>; +def S4SUBQi : OFormL<0x10, 0x2B, "s4subq $RA,$L,$RC", + [(set GPRC:$RC, (sub (shl GPRC:$RA, imm2), immUExt8:$L))]>; +def S8ADDL : OForm< 0x10, 0x12, "s8addl $RA,$RB,$RC", + [(set GPRC:$RC, (sext_inreg (add (shl GPRC:$RA, imm3), GPRC:$RB), i32))]>; +def S8ADDLi : OFormL<0x10, 0x12, "s8addl $RA,$L,$RC", + [(set GPRC:$RC, (sext_inreg (add (shl GPRC:$RA, imm3), immUExt8:$L), i32))]>; +def S8ADDQ : OForm< 0x10, 0x32, "s8addq $RA,$RB,$RC", + [(set GPRC:$RC, (add (shl GPRC:$RA, imm3), GPRC:$RB))]>; +def S8ADDQi : OFormL<0x10, 0x32, "s8addq $RA,$L,$RC", + [(set GPRC:$RC, (add (shl GPRC:$RA, imm3), immUExt8:$L))]>; +def S8SUBL : OForm< 0x10, 0x1B, "s8subl $RA,$RB,$RC", + [(set GPRC:$RC, (sext_inreg (sub (shl GPRC:$RA, imm3), GPRC:$RB), i32))]>; +def S8SUBLi : OFormL<0x10, 0x1B, "s8subl $RA,$L,$RC", + [(set GPRC:$RC, (sext_inreg (sub (shl GPRC:$RA, imm3), immUExt8:$L), i32))]>; +def S8SUBQ : OForm< 0x10, 0x3B, "s8subq $RA,$RB,$RC", + [(set GPRC:$RC, (sub (shl GPRC:$RA, imm3), GPRC:$RB))]>; +def S8SUBQi : OFormL<0x10, 0x3B, "s8subq $RA,$L,$RC", + [(set GPRC:$RC, (sub (shl GPRC:$RA, imm3), immUExt8:$L))]>; -def SRLi : OFormL<0x12, 0x34, "srl $RA,$L,$RC">; //Shift right logical -def SUBL : OForm< 0x10, 0x09, "subl $RA,$RB,$RC">; //Subtract longword -def SUBLi : OFormL<0x10, 0x09, "subl $RA,$L,$RC">; //Subtract longword -def SUBQ : OForm< 0x10, 0x29, "subq $RA,$RB,$RC">; //Subtract quadword -def SUBQi : OFormL<0x10, 0x29, "subq $RA,$L,$RC">; //Subtract quadword -def UMULH : OForm< 0x13, 0x30, "umulh $RA,$RB,$RC">; //Unsigned multiply quadword high -def UMULHi : OFormL<0x13, 0x30, "umulh $RA,$L,$RC">; //Unsigned multiply quadword high -def XOR : OForm< 0x11, 0x40, "xor $RA,$RB,$RC">; //Logical difference -def XORi : OFormL<0x11, 0x40, "xor $RA,$L,$RC">; //Logical difference -def ZAP : OForm< 0x12, 0x30, "zap $RA,$RB,$RC">; //Zero bytes -def ZAPi : OFormL<0x12, 0x30, "zap $RA,$L,$RC">; //Zero bytes -def ZAPNOT : OForm< 0x12, 0x31, "zapnot $RA,$RB,$RC">; //Zero bytes not -def ZAPNOTi : OFormL<0x12, 0x31, "zapnot $RA,$L,$RC">; //Zero bytes not +def SEXTB : OForm< 0x1C, 0x00, "sextb $RB,$RC", []>; //Sign extend byte +def SEXTW : OForm< 0x1C, 0x01, "sextw $RB,$RC", []>; //Sign extend word + +def SL : OForm< 0x12, 0x39, "sll $RA,$RB,$RC", + [(set GPRC:$RC, (shl GPRC:$RA, GPRC:$RB))]>; +def SLi : OFormL<0x12, 0x39, "sll $RA,$L,$RC", + [(set GPRC:$RC, (shl GPRC:$RA, immUExt8:$L))]>; +def SRA : OForm< 0x12, 0x3C, "sra $RA,$RB,$RC", + [(set GPRC:$RC, (sra GPRC:$RA, GPRC:$RB))]>; +def SRAi : OFormL<0x12, 0x3C, "sra $RA,$L,$RC", + [(set GPRC:$RC, (sra GPRC:$RA, immUExt8:$L))]>; +def SRL : OForm< 0x12, 0x34, "srl $RA,$RB,$RC", + [(set GPRC:$RC, (srl GPRC:$RA, GPRC:$RB))]>; +def SRLi : OFormL<0x12, 0x34, "srl $RA,$L,$RC", + [(set GPRC:$RC, (srl GPRC:$RA, immUExt8:$L))]>; +def SUBL : OForm< 0x10, 0x09, "subl $RA,$RB,$RC", + [(set GPRC:$RC, (sext_inreg (sub GPRC:$RA, GPRC:$RB), i32))]>; +def SUBLi : OFormL<0x10, 0x09, "subl $RA,$L,$RC", + [(set GPRC:$RC, (sext_inreg (sub GPRC:$RA, immUExt8:$L), i32))]>; +def SUBQ : OForm< 0x10, 0x29, "subq $RA,$RB,$RC", + [(set GPRC:$RC, (sub GPRC:$RA, GPRC:$RB))]>; +def SUBQi : OFormL<0x10, 0x29, "subq $RA,$L,$RC", + [(set GPRC:$RC, (sub GPRC:$RA, immUExt8:$L))]>; +def UMULH : OForm< 0x13, 0x30, "umulh $RA,$RB,$RC", []>; //Unsigned multiply quadword high +def UMULHi : OFormL<0x13, 0x30, "umulh $RA,$L,$RC", []>; //Unsigned multiply quadword high +def XOR : OForm< 0x11, 0x40, "xor $RA,$RB,$RC", + [(set GPRC:$RC, (xor GPRC:$RA, GPRC:$RB))]>; +def XORi : OFormL<0x11, 0x40, "xor $RA,$L,$RC", + [(set GPRC:$RC, (xor GPRC:$RA, immUExt8:$L))]>; +def ZAP : OForm< 0x12, 0x30, "zap $RA,$RB,$RC", []>; //Zero bytes +def ZAPi : OFormL<0x12, 0x30, "zap $RA,$L,$RC", []>; //Zero bytes +def ZAPNOT : OForm< 0x12, 0x31, "zapnot $RA,$RB,$RC", []>; //Zero bytes not +def ZAPNOTi : OFormL<0x12, 0x31, "zapnot $RA,$L,$RC", []>; //Zero bytes not //Comparison, int -def CMPBGE : OForm< 0x10, 0x0F, "cmpbge $RA,$RB,$RC">; //Compare byte -def CMPBGEi : OFormL<0x10, 0x0F, "cmpbge $RA,$L,$RC">; //Compare byte -def CMPEQ : OForm< 0x10, 0x2D, "cmpeq $RA,$RB,$RC">; //Compare signed quadword equal -def CMPEQi : OFormL<0x10, 0x2D, "cmpeq $RA,$L,$RC">; //Compare signed quadword equal -def CMPLE : OForm< 0x10, 0x6D, "cmple $RA,$RB,$RC">; //Compare signed quadword less than or equal -def CMPLEi : OFormL<0x10, 0x6D, "cmple $RA,$L,$RC">; //Compare signed quadword less than or equal -def CMPLT : OForm< 0x10, 0x4D, "cmplt $RA,$RB,$RC">; //Compare signed quadword less than -def CMPLTi : OFormL<0x10, 0x4D, "cmplt $RA,$L,$RC">; //Compare signed quadword less than -def CMPULE : OForm< 0x10, 0x3D, "cmpule $RA,$RB,$RC">; //Compare unsigned quadword less than or equal -def CMPULEi : OFormL<0x10, 0x3D, "cmpule $RA,$L,$RC">; //Compare unsigned quadword less than or equal -def CMPULT : OForm< 0x10, 0x1D, "cmpult $RA,$RB,$RC">; //Compare unsigned quadword less than -def CMPULTi : OFormL<0x10, 0x1D, "cmpult $RA,$L,$RC">; //Compare unsigned quadword less than +def CMPBGE : OForm< 0x10, 0x0F, "cmpbge $RA,$RB,$RC", []>; //Compare byte +def CMPBGEi : OFormL<0x10, 0x0F, "cmpbge $RA,$L,$RC", []>; //Compare byte +def CMPEQ : OForm< 0x10, 0x2D, "cmpeq $RA,$RB,$RC", []>; //Compare signed quadword equal +def CMPEQi : OFormL<0x10, 0x2D, "cmpeq $RA,$L,$RC", []>; //Compare signed quadword equal +def CMPLE : OForm< 0x10, 0x6D, "cmple $RA,$RB,$RC", []>; //Compare signed quadword less than or equal +def CMPLEi : OFormL<0x10, 0x6D, "cmple $RA,$L,$RC", []>; //Compare signed quadword less than or equal +def CMPLT : OForm< 0x10, 0x4D, "cmplt $RA,$RB,$RC", []>; //Compare signed quadword less than +def CMPLTi : OFormL<0x10, 0x4D, "cmplt $RA,$L,$RC", []>; //Compare signed quadword less than +def CMPULE : OForm< 0x10, 0x3D, "cmpule $RA,$RB,$RC", []>; //Compare unsigned quadword less than or equal +def CMPULEi : OFormL<0x10, 0x3D, "cmpule $RA,$L,$RC", []>; //Compare unsigned quadword less than or equal +def CMPULT : OForm< 0x10, 0x1D, "cmpult $RA,$RB,$RC", []>; //Compare unsigned quadword less than +def CMPULTi : OFormL<0x10, 0x1D, "cmpult $RA,$L,$RC", []>; //Compare unsigned quadword less than //Comparison, FP def CMPTEQ : FPForm<0x16, 0x0A5, "cmpteq/su $RA,$RB,$RC">; //Compare T_floating equal @@ -238,24 +304,27 @@ def CMPTLT : FPForm<0x16, 0x0A6, "cmptlt/su $RA,$RB,$RC">; //Compare T_floating def CMPTUN : FPForm<0x16, 0x0A4, "cmptun/su $RA,$RB,$RC">; //Compare T_floating unordered //There are in the Multimedia extentions, so let's not use them yet -def MAXSB8 : OForm<0x1C, 0x3E, "MAXSB8 $RA,$RB,$RC">; //Vector signed byte maximum -def MAXSW4 : OForm< 0x1C, 0x3F, "MAXSW4 $RA,$RB,$RC">; //Vector signed word maximum -def MAXUB8 : OForm<0x1C, 0x3C, "MAXUB8 $RA,$RB,$RC">; //Vector unsigned byte maximum -def MAXUW4 : OForm< 0x1C, 0x3D, "MAXUW4 $RA,$RB,$RC">; //Vector unsigned word maximum -def MINSB8 : OForm< 0x1C, 0x38, "MINSB8 $RA,$RB,$RC">; //Vector signed byte minimum -def MINSW4 : OForm< 0x1C, 0x39, "MINSW4 $RA,$RB,$RC">; //Vector signed word minimum -def MINUB8 : OForm< 0x1C, 0x3A, "MINUB8 $RA,$RB,$RC">; //Vector unsigned byte minimum -def MINUW4 : OForm< 0x1C, 0x3B, "MINUW4 $RA,$RB,$RC">; //Vector unsigned word minimum -def PERR : OForm< 0x1C, 0x31, "PERR $RA,$RB,$RC">; //Pixel error -def PKLB : OForm< 0x1C, 0x37, "PKLB $RA,$RB,$RC">; //Pack longwords to bytes -def PKWB : OForm<0x1C, 0x36, "PKWB $RA,$RB,$RC">; //Pack words to bytes -def UNPKBL : OForm< 0x1C, 0x35, "UNPKBL $RA,$RB,$RC">; //Unpack bytes to longwords -def UNPKBW : OForm< 0x1C, 0x34, "UNPKBW $RA,$RB,$RC">; //Unpack bytes to words +//def MAXSB8 : OForm<0x1C, 0x3E, "MAXSB8 $RA,$RB,$RC">; //Vector signed byte maximum +//def MAXSW4 : OForm< 0x1C, 0x3F, "MAXSW4 $RA,$RB,$RC">; //Vector signed word maximum +//def MAXUB8 : OForm<0x1C, 0x3C, "MAXUB8 $RA,$RB,$RC">; //Vector unsigned byte maximum +//def MAXUW4 : OForm< 0x1C, 0x3D, "MAXUW4 $RA,$RB,$RC">; //Vector unsigned word maximum +//def MINSB8 : OForm< 0x1C, 0x38, "MINSB8 $RA,$RB,$RC">; //Vector signed byte minimum +//def MINSW4 : OForm< 0x1C, 0x39, "MINSW4 $RA,$RB,$RC">; //Vector signed word minimum +//def MINUB8 : OForm< 0x1C, 0x3A, "MINUB8 $RA,$RB,$RC">; //Vector unsigned byte minimum +//def MINUW4 : OForm< 0x1C, 0x3B, "MINUW4 $RA,$RB,$RC">; //Vector unsigned word minimum +//def PERR : OForm< 0x1C, 0x31, "PERR $RA,$RB,$RC">; //Pixel error +//def PKLB : OForm< 0x1C, 0x37, "PKLB $RA,$RB,$RC">; //Pack longwords to bytes +//def PKWB : OForm<0x1C, 0x36, "PKWB $RA,$RB,$RC">; //Pack words to bytes +//def UNPKBL : OForm< 0x1C, 0x35, "UNPKBL $RA,$RB,$RC">; //Unpack bytes to longwords +//def UNPKBW : OForm< 0x1C, 0x34, "UNPKBW $RA,$RB,$RC">; //Unpack bytes to words //End operate -let isReturn = 1, isTerminator = 1 in +let isReturn = 1, isTerminator = 1 in def RET : MbrForm< 0x1A, 0x02, (ops GPRC:$RD, GPRC:$RS, s64imm:$DISP), "ret $RD,($RS),$DISP">; //Return from subroutine +//DAG Version: +let isReturn = 1, isTerminator = 1, Ra = 31, Rb = 26, disp = 1, Uses = [R26] in + def RETDAG : MbrForm< 0x1A, 0x02, (ops), "ret $$31,($$26),1">; //Return from subroutine def JMP : MbrForm< 0x1A, 0x00, (ops GPRC:$RD, GPRC:$RS, GPRC:$DISP), "jmp $RD,($RS),$DISP">; //Jump let isCall = 1, diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index c348fa9ce46..baf6bca8ee8 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -314,7 +314,7 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); MachineBasicBlock::iterator MBBI = prior(MBB.end()); - assert((MBBI->getOpcode() == Alpha::RET) + assert(((MBBI->getOpcode() == Alpha::RET) || (MBBI->getOpcode() == Alpha::RETDAG)) && "Can only insert epilog into returning blocks"); bool FP = hasFP(MF); diff --git a/lib/Target/Alpha/AlphaTargetMachine.cpp b/lib/Target/Alpha/AlphaTargetMachine.cpp index 8f263294052..37f71b25af9 100644 --- a/lib/Target/Alpha/AlphaTargetMachine.cpp +++ b/lib/Target/Alpha/AlphaTargetMachine.cpp @@ -32,6 +32,9 @@ namespace llvm { cl::opt EnableAlphaLSR("enable-lsr-for-alpha", cl::desc("Enable LSR for Alpha (beta option!)"), cl::Hidden); + cl::opt EnableAlphaDAG("enable-dag-isel-for-alpha", + cl::desc("Enable DAG ISEL for Alpha (beta option!)"), + cl::Hidden); } unsigned AlphaTargetMachine::getModuleMatchQuality(const Module &M) { @@ -94,7 +97,10 @@ bool AlphaTargetMachine::addPassesToEmitFile(PassManager &PM, // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); - PM.add(createAlphaPatternInstructionSelector(*this)); + if (EnableAlphaDAG) + PM.add(createAlphaISelDag(*this)); + else + PM.add(createAlphaPatternInstructionSelector(*this)); if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(&std::cerr)); diff --git a/lib/Target/Alpha/Makefile b/lib/Target/Alpha/Makefile index 7d3f3547632..836268b551d 100644 --- a/lib/Target/Alpha/Makefile +++ b/lib/Target/Alpha/Makefile @@ -14,6 +14,6 @@ TARGET = Alpha BUILT_SOURCES = AlphaGenRegisterInfo.h.inc AlphaGenRegisterNames.inc \ AlphaGenRegisterInfo.inc AlphaGenInstrNames.inc \ AlphaGenInstrInfo.inc AlphaGenCodeEmitter.inc \ - AlphaGenAsmWriter.inc + AlphaGenAsmWriter.inc AlphaGenDAGISel.inc include $(LEVEL)/Makefile.common