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Enable generation of AssertSext and AssertZext in the PPC backend.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23168 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2005-08-31 01:58:39 +00:00
parent 7a49fdcd11
commit 49296f1f48
1 changed files with 7 additions and 2 deletions
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9
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -214,8 +214,13 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
MF.addLiveIn(GPR[GPR_idx]);
argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
GPR[GPR_idx], MVT::i32);
if (ObjectVT != MVT::i32)
argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
if (ObjectVT != MVT::i32) {
unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
: ISD::AssertZext;
argt = DAG.getNode(AssertOp, MVT::i32, argt,
DAG.getValueType(ObjectVT));
argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt);
}
} else {
needsLoad = true;
}