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[mips] Set isAsCheapAsAMove flag on ADDiu and DADDiu, which enables

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re-materialization of immediate loads.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167153 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-10-31 18:37:55 +00:00
parent b586aae15e
commit 497204a94b
3 changed files with 33 additions and 2 deletions
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2
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -86,7 +86,7 @@ let DecoderNamespace = "Mips64" in {
def DADDi : ArithOverflowI<0x18, "daddi", add, simm16_64, immSExt16,
CPU64Regs>;
def DADDiu : ArithLogicI<0x19, "daddiu", add, simm16_64, immSExt16,
CPU64Regs>;
CPU64Regs>, IsAsCheapAsAMove;
def DANDi : ArithLogicI<0x0c, "andi", and, uimm16_64, immZExt16, CPU64Regs>;
def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>;
def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>;

7
lib/Target/Mips/MipsInstrInfo.td
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@ -200,6 +200,10 @@ class IsTailCall {
bit isCodeGenOnly = 1;
}
class IsAsCheapAsAMove {
bit isAsCheapAsAMove = 1;
}
//===----------------------------------------------------------------------===//
// Instruction format superclass
//===----------------------------------------------------------------------===//
@ -925,7 +929,8 @@ def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>;
//===----------------------------------------------------------------------===//
/// Arithmetic Instructions (ALU Immediate)
def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>;
def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>,
IsAsCheapAsAMove;
def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>;
def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;

26
test/CodeGen/Mips/remat-immed-load.ll Normal file
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@ -0,0 +1,26 @@
; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 < %s | FileCheck %s -check-prefix=64
define void @f0() nounwind {
entry:
; 32: addiu $4, $zero, 1
; 32: addiu $4, $zero, 1
tail call void @foo1(i32 1) nounwind
tail call void @foo1(i32 1) nounwind
ret void
}
declare void @foo1(i32)
define void @f3() nounwind {
entry:
; 64: daddiu $4, $zero, 1
; 64: daddiu $4, $zero, 1
tail call void @foo2(i64 1) nounwind
tail call void @foo2(i64 1) nounwind
ret void
}
declare void @foo2(i64)