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[SPARC] Use AtomicExpandPass to expand AtomicRMW instructions.
They were previously expanded to CAS loops in a custom isel expansion, but AtomicExpandPass knows how to do that generically. Testing is covered by the existing sparc atomics.ll testcases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264771 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
James Y Knight
parent
1df673217b
commit
499797f6dc
@ -1394,6 +1394,14 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
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// TargetLowering Implementation
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//===----------------------------------------------------------------------===//
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TargetLowering::AtomicExpansionKind SparcTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
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if (AI->getOperation() == AtomicRMWInst::Xchg &&
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AI->getType()->getPrimitiveSizeInBits() == 32)
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return AtomicExpansionKind::None; // Uses xchg instruction
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return AtomicExpansionKind::CmpXChg;
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}
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/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
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/// condition.
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static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
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@ -3005,51 +3013,6 @@ SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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case SP::SELECT_CC_DFP_FCC:
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case SP::SELECT_CC_QFP_FCC:
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return expandSelectCC(MI, BB, SP::FBCOND);
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case SP::ATOMIC_LOAD_ADD_32:
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return expandAtomicRMW(MI, BB, SP::ADDrr);
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case SP::ATOMIC_LOAD_ADD_64:
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return expandAtomicRMW(MI, BB, SP::ADDXrr);
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case SP::ATOMIC_LOAD_SUB_32:
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return expandAtomicRMW(MI, BB, SP::SUBrr);
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case SP::ATOMIC_LOAD_SUB_64:
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return expandAtomicRMW(MI, BB, SP::SUBXrr);
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case SP::ATOMIC_LOAD_AND_32:
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return expandAtomicRMW(MI, BB, SP::ANDrr);
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case SP::ATOMIC_LOAD_AND_64:
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return expandAtomicRMW(MI, BB, SP::ANDXrr);
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case SP::ATOMIC_LOAD_OR_32:
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return expandAtomicRMW(MI, BB, SP::ORrr);
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case SP::ATOMIC_LOAD_OR_64:
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return expandAtomicRMW(MI, BB, SP::ORXrr);
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case SP::ATOMIC_LOAD_XOR_32:
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return expandAtomicRMW(MI, BB, SP::XORrr);
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case SP::ATOMIC_LOAD_XOR_64:
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return expandAtomicRMW(MI, BB, SP::XORXrr);
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case SP::ATOMIC_LOAD_NAND_32:
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return expandAtomicRMW(MI, BB, SP::ANDrr);
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case SP::ATOMIC_LOAD_NAND_64:
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return expandAtomicRMW(MI, BB, SP::ANDXrr);
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case SP::ATOMIC_SWAP_64:
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return expandAtomicRMW(MI, BB, 0);
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case SP::ATOMIC_LOAD_MAX_32:
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return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_G);
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case SP::ATOMIC_LOAD_MAX_64:
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return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_G);
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case SP::ATOMIC_LOAD_MIN_32:
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return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LE);
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case SP::ATOMIC_LOAD_MIN_64:
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return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LE);
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case SP::ATOMIC_LOAD_UMAX_32:
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return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_GU);
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case SP::ATOMIC_LOAD_UMAX_64:
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return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_GU);
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case SP::ATOMIC_LOAD_UMIN_32:
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return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LEU);
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case SP::ATOMIC_LOAD_UMIN_64:
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return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LEU);
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}
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}
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@ -3112,101 +3075,6 @@ SparcTargetLowering::expandSelectCC(MachineInstr *MI,
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return BB;
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}
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MachineBasicBlock*
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SparcTargetLowering::expandAtomicRMW(MachineInstr *MI,
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MachineBasicBlock *MBB,
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unsigned Opcode,
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unsigned CondCode) const {
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const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
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MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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DebugLoc DL = MI->getDebugLoc();
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// MI is an atomic read-modify-write instruction of the form:
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//
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// rd = atomicrmw<op> addr, rs2
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//
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// All three operands are registers.
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unsigned DestReg = MI->getOperand(0).getReg();
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unsigned AddrReg = MI->getOperand(1).getReg();
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unsigned Rs2Reg = MI->getOperand(2).getReg();
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// SelectionDAG has already inserted memory barriers before and after MI, so
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// we simply have to implement the operatiuon in terms of compare-and-swap.
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//
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// %val0 = load %addr
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// loop:
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// %val = phi %val0, %dest
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// %upd = op %val, %rs2
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// %dest = cas %addr, %val, %upd
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// cmp %val, %dest
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// bne loop
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// done:
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//
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bool is64Bit = SP::I64RegsRegClass.hasSubClassEq(MRI.getRegClass(DestReg));
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const TargetRegisterClass *ValueRC =
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is64Bit ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
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unsigned Val0Reg = MRI.createVirtualRegister(ValueRC);
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BuildMI(*MBB, MI, DL, TII.get(is64Bit ? SP::LDXri : SP::LDri), Val0Reg)
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.addReg(AddrReg).addImm(0);
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// Split the basic block MBB before MI and insert the loop block in the hole.
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MachineFunction::iterator MFI = MBB->getIterator();
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const BasicBlock *LLVM_BB = MBB->getBasicBlock();
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MachineFunction *MF = MBB->getParent();
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MachineBasicBlock *LoopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *DoneMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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++MFI;
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MF->insert(MFI, LoopMBB);
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MF->insert(MFI, DoneMBB);
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// Move MI and following instructions to DoneMBB.
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DoneMBB->splice(DoneMBB->begin(), MBB, MI, MBB->end());
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DoneMBB->transferSuccessorsAndUpdatePHIs(MBB);
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// Connect the CFG again.
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MBB->addSuccessor(LoopMBB);
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LoopMBB->addSuccessor(LoopMBB);
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LoopMBB->addSuccessor(DoneMBB);
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// Build the loop block.
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unsigned ValReg = MRI.createVirtualRegister(ValueRC);
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// Opcode == 0 means try to write Rs2Reg directly (ATOMIC_SWAP).
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unsigned UpdReg = (Opcode ? MRI.createVirtualRegister(ValueRC) : Rs2Reg);
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BuildMI(LoopMBB, DL, TII.get(SP::PHI), ValReg)
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.addReg(Val0Reg).addMBB(MBB)
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.addReg(DestReg).addMBB(LoopMBB);
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if (CondCode) {
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// This is one of the min/max operations. We need a CMPrr followed by a
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// MOVXCC/MOVICC.
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BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(Rs2Reg);
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BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg)
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.addReg(ValReg).addReg(Rs2Reg).addImm(CondCode);
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} else if (Opcode) {
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BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg)
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.addReg(ValReg).addReg(Rs2Reg);
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}
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if (MI->getOpcode() == SP::ATOMIC_LOAD_NAND_32 ||
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MI->getOpcode() == SP::ATOMIC_LOAD_NAND_64) {
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unsigned TmpReg = UpdReg;
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UpdReg = MRI.createVirtualRegister(ValueRC);
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BuildMI(LoopMBB, DL, TII.get(SP::XORri), UpdReg).addReg(TmpReg).addImm(-1);
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}
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BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::CASXrr : SP::CASrr), DestReg)
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.addReg(AddrReg).addReg(ValReg).addReg(UpdReg)
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.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
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BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(DestReg);
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BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::BPXCC : SP::BCOND))
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.addMBB(LoopMBB).addImm(SPCC::ICC_NE);
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MI->eraseFromParent();
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return DoneMBB;
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}
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//===----------------------------------------------------------------------===//
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// Sparc Inline Assembly Support
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//===----------------------------------------------------------------------===//
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@ -187,6 +187,8 @@ namespace llvm {
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return true;
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}
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AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
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void ReplaceNodeResults(SDNode *N,
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SmallVectorImpl<SDValue>& Results,
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SelectionDAG &DAG) const override;
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@ -510,39 +510,6 @@ def : Pat<(atomic_store ADDRri:$dst, i64:$val), (STXri ADDRri:$dst, $val)>;
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} // Predicates = [Is64Bit]
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let usesCustomInserter = 1, hasCtrlDep = 1, mayLoad = 1, mayStore = 1,
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Defs = [ICC] in
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multiclass AtomicRMW<SDPatternOperator op32, SDPatternOperator op64> {
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def _32 : Pseudo<(outs IntRegs:$rd),
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(ins ptr_rc:$addr, IntRegs:$rs2), "",
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[(set i32:$rd, (op32 iPTR:$addr, i32:$rs2))]>;
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let Predicates = [Is64Bit] in
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def _64 : Pseudo<(outs I64Regs:$rd),
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(ins ptr_rc:$addr, I64Regs:$rs2), "",
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[(set i64:$rd, (op64 iPTR:$addr, i64:$rs2))]>;
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}
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defm ATOMIC_LOAD_ADD : AtomicRMW<atomic_load_add_32, atomic_load_add_64>;
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defm ATOMIC_LOAD_SUB : AtomicRMW<atomic_load_sub_32, atomic_load_sub_64>;
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defm ATOMIC_LOAD_AND : AtomicRMW<atomic_load_and_32, atomic_load_and_64>;
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defm ATOMIC_LOAD_OR : AtomicRMW<atomic_load_or_32, atomic_load_or_64>;
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defm ATOMIC_LOAD_XOR : AtomicRMW<atomic_load_xor_32, atomic_load_xor_64>;
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defm ATOMIC_LOAD_NAND : AtomicRMW<atomic_load_nand_32, atomic_load_nand_64>;
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defm ATOMIC_LOAD_MIN : AtomicRMW<atomic_load_min_32, atomic_load_min_64>;
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defm ATOMIC_LOAD_MAX : AtomicRMW<atomic_load_max_32, atomic_load_max_64>;
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defm ATOMIC_LOAD_UMIN : AtomicRMW<atomic_load_umin_32, atomic_load_umin_64>;
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defm ATOMIC_LOAD_UMAX : AtomicRMW<atomic_load_umax_32, atomic_load_umax_64>;
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// There is no 64-bit variant of SWAP, so use a pseudo.
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let usesCustomInserter = 1, hasCtrlDep = 1, mayLoad = 1, mayStore = 1,
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Defs = [ICC], Predicates = [Is64Bit] in
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def ATOMIC_SWAP_64 : Pseudo<(outs I64Regs:$rd),
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(ins ptr_rc:$addr, I64Regs:$rs2), "",
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[(set i64:$rd,
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(atomic_swap_64 iPTR:$addr, i64:$rs2))]>;
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let Predicates = [Is64Bit], hasSideEffects = 1, Uses = [ICC], cc = 0b10 in
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defm TXCC : TRAP<"%xcc">;
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