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Add a utility function for conservatively clearing kill flags, and make
use of it in MachineCSE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103726 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -163,6 +163,12 @@ public:
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/// form, so there should only be one definition.
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MachineInstr *getVRegDef(unsigned Reg) const;
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/// clearKillFlags - Iterate over all the uses of the given register and
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/// clear the kill flag from the MachineOperand. This function is used by
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/// optimization passes which extend register lifetimes and need only
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/// preserve conservative kill flag information.
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void clearKillFlags(unsigned Reg) const;
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#ifndef NDEBUG
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void dumpUses(unsigned RegNo) const;
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#endif
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@ -112,6 +112,7 @@ bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
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DEBUG(dbgs() << "Coalescing: " << *DefMI);
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DEBUG(dbgs() << "*** to: " << *MI);
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MO.setReg(SrcReg);
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MRI->clearKillFlags(SrcReg);
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if (NewRC != SRC)
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MRI->setRegClass(SrcReg, NewRC);
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DefMI->eraseFromParent();
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@ -365,8 +366,10 @@ bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
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// Actually perform the elimination.
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if (DoCSE) {
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for (unsigned i = 0, e = CSEPairs.size(); i != e; ++i)
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for (unsigned i = 0, e = CSEPairs.size(); i != e; ++i) {
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MRI->replaceRegWith(CSEPairs[i].first, CSEPairs[i].second);
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MRI->clearKillFlags(CSEPairs[i].second);
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}
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MI->eraseFromParent();
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++NumCSEs;
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} else {
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@ -133,6 +133,15 @@ bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
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return ++UI == use_nodbg_end();
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}
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/// clearKillFlags - Iterate over all the uses of the given register and
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/// clear the kill flag from the MachineOperand. This function is used by
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/// optimization passes which extend register lifetimes and need only
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/// preserve conservative kill flag information.
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void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
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for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI)
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UI.getOperand().setIsKill(false);
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}
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bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
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for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
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if (I->first == Reg || I->second == Reg)
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