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Fix newly-introduced 4.3 warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47375 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -80,7 +80,7 @@ public:
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// ParserOptions in effect. If positional information is not applicable,
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// these will return a value of -1.
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//
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inline const void getErrorLocation(int &Line, int &Column) const {
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inline void getErrorLocation(int &Line, int &Column) const {
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Line = LineNo; Column = ColumnNo;
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}
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@ -578,12 +578,13 @@ static BasicBlock *getBBVal(const ValID &ID) {
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} if (ID.Type == ValID::LocalName) {
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std::string Name = ID.getName();
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Value *N = CurFun.CurrentFunction->getValueSymbolTable().lookup(Name);
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if (N)
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if (N) {
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if (N->getType()->getTypeID() == Type::LabelTyID)
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BB = cast<BasicBlock>(N);
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else
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GenerateError("Reference to label '" + Name + "' is actually of type '"+
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N->getType()->getDescription() + "'");
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}
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} else if (ID.Type == ValID::LocalID) {
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if (ID.Num < CurFun.NextValNum && ID.Num < CurFun.Values.size()) {
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if (CurFun.Values[ID.Num]->getType()->getTypeID() == Type::LabelTyID)
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@ -578,12 +578,13 @@ static BasicBlock *getBBVal(const ValID &ID) {
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} if (ID.Type == ValID::LocalName) {
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std::string Name = ID.getName();
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Value *N = CurFun.CurrentFunction->getValueSymbolTable().lookup(Name);
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if (N)
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if (N) {
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if (N->getType()->getTypeID() == Type::LabelTyID)
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BB = cast<BasicBlock>(N);
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else
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GenerateError("Reference to label '" + Name + "' is actually of type '"+
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N->getType()->getDescription() + "'");
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}
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} else if (ID.Type == ValID::LocalID) {
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if (ID.Num < CurFun.NextValNum && ID.Num < CurFun.Values.size()) {
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if (CurFun.Values[ID.Num]->getType()->getTypeID() == Type::LabelTyID)
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@ -224,11 +224,12 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
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unsigned SrcReg, DstReg;
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if (!CopyMI || !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg))
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return Reg;
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if (TargetRegisterInfo::isVirtualRegister(SrcReg))
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if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
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if (!vrm_->isAssignedReg(SrcReg))
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return Reg;
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else
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SrcReg = vrm_->getPhys(SrcReg);
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}
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if (Reg == SrcReg)
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return Reg;
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@ -864,7 +865,7 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
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// If copy coalescer has assigned a "preferred" register, check if it's
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// available first.
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if (cur->preference)
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if (cur->preference) {
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if (prt_->isRegAvail(cur->preference)) {
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DOUT << "\t\tassigned the preferred register: "
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<< tri_->getName(cur->preference) << "\n";
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@ -872,6 +873,7 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
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} else
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DOUT << "\t\tunable to assign the preferred register: "
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<< tri_->getName(cur->preference) << "\n";
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}
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// Scan for the first available register.
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TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_);
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@ -775,11 +775,12 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
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// Spill all physical registers holding virtual registers now.
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for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
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if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
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if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) {
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if (unsigned VirtReg = PhysRegsUsed[i])
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spillVirtReg(MBB, MI, VirtReg, i);
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else
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removePhysReg(i);
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}
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#if 0
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// This checking code is very expensive.
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@ -34,7 +34,7 @@ namespace llvm {
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getCalleeSaveSpillSlots(unsigned &NumEntries) const;
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//! Stack slot size (16 bytes)
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static const int stackSlotSize() {
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static int stackSlotSize() {
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return 16;
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}
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//! Maximum frame offset representable by a signed 10-bit integer
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@ -42,19 +42,19 @@ namespace llvm {
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This is the maximum frame offset that can be expressed as a 10-bit
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integer, used in D-form addresses.
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*/
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static const int maxFrameOffset() {
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static int maxFrameOffset() {
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return ((1 << 9) - 1) * stackSlotSize();
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}
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//! Minimum frame offset representable by a signed 10-bit integer
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static const int minFrameOffset() {
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static int minFrameOffset() {
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return -(1 << 9) * stackSlotSize();
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}
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//! Minimum frame size (enough to spill LR + SP)
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static const int minStackSize() {
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static int minStackSize() {
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return (2 * stackSlotSize());
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}
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//! Frame size required to spill all registers plus frame info
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static const int fullSpillSize() {
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static int fullSpillSize() {
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return (SPURegisterInfo::getNumArgRegs() * stackSlotSize());
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}
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//! Number of instructions required to overcome hint-for-branch latency
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@ -65,7 +65,7 @@ namespace llvm {
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of instructions occurs between the HBR and the target. Currently, HBRs
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take 6 cycles, ergo, the magic number 6.
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*/
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static const int branchHintPenalty() {
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static int branchHintPenalty() {
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return 6;
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}
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};
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@ -221,7 +221,7 @@ SPURegisterInfo::getArgRegs()
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return SPU_ArgRegs;
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}
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const unsigned
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unsigned
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SPURegisterInfo::getNumArgRegs()
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{
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return sizeof(SPU_ArgRegs) / sizeof(SPU_ArgRegs[0]);
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@ -90,7 +90,7 @@ namespace llvm {
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static const unsigned *getArgRegs();
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//! Return the size of the argument passing register array
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static const unsigned getNumArgRegs();
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static unsigned getNumArgRegs();
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//! Get DWARF debugging register number
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int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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@ -145,11 +145,12 @@ unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) const {
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const TargetRegisterClass *
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X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
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if (RC == &X86::CCRRegClass)
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if (RC == &X86::CCRRegClass) {
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if (Is64Bit)
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return &X86::GR64RegClass;
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else
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return &X86::GR32RegClass;
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}
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return NULL;
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}
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@ -5481,8 +5481,8 @@ Instruction *InstCombiner::visitICmpInstWithInstAndIntCst(ICmpInst &ICI,
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// Extending a relational comparison when we're checking the sign
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// bit would not work.
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if (Cast->hasOneUse() &&
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(ICI.isEquality() || AndCST->getValue().isNonNegative() &&
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RHSV.isNonNegative())) {
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(ICI.isEquality() ||
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(AndCST->getValue().isNonNegative() && RHSV.isNonNegative()))) {
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uint32_t BitWidth =
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cast<IntegerType>(Cast->getOperand(0)->getType())->getBitWidth();
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APInt NewCST = AndCST->getValue();
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@ -90,7 +90,7 @@ namespace {
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std::map<DomTreeNode*, Value*> &Phis);
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/// inLoop - returns true if the given block is within the current loop
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const bool inLoop(BasicBlock* B) {
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bool inLoop(BasicBlock* B) {
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return std::binary_search(LoopBlocks.begin(), LoopBlocks.end(), B);
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}
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};
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@ -186,7 +186,7 @@ ParamAttrsList::includeAttrs(const ParamAttrsList *PAL,
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// For now, say we can't change a known alignment.
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ParameterAttributes OldAlign = OldAttrs & ParamAttr::Alignment;
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ParameterAttributes NewAlign = attrs & ParamAttr::Alignment;
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assert(!OldAlign || !NewAlign || OldAlign == NewAlign &&
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assert((!OldAlign || !NewAlign || OldAlign == NewAlign) &&
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"Attempt to change alignment!");
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#endif
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