RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-12-24 13:06:56 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

add R0 to liveout

Browse Source 
expand "ret null" (implements test/Regression/CodeGen/ARM/ret_void.ll)
note that a Flag link is missing between the copy and the branch


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28691 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2006-06-05 22:26:14 +00:00
parent 2403b855cd
commit 4b02367d54
1 changed files with 13 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -49,18 +49,28 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
SDOperand Copy;
SDOperand Chain = Op.getOperand(0);
switch(Op.getNumOperands()) {
default:
assert(0 && "Do not know how to return this many arguments!");
abort();
case 1:
return SDOperand(); // ret void is legal
case 1: {
SDOperand LR = DAG.getRegister(ARM::R14, MVT::i32);
return DAG.getNode(ISD::BRIND, MVT::Other, Chain, LR);
}
case 3:
Copy = DAG.getCopyToReg(Op.getOperand(0), ARM::R0, Op.getOperand(1), SDOperand());
Copy = DAG.getCopyToReg(Chain, ARM::R0, Op.getOperand(1), SDOperand());
if (DAG.getMachineFunction().liveout_empty())
DAG.getMachineFunction().addLiveOut(ARM::R0);
break;
}
SDOperand LR = DAG.getRegister(ARM::R14, MVT::i32);
//bug: the copy and branch should be linked with a flag so that the
//scheduller can't move an instruction that destroys R0 in between them
//return DAG.getNode(ISD::BRIND, MVT::Other, Copy, LR, Copy.getValue(1));
return DAG.getNode(ISD::BRIND, MVT::Other, Copy, LR);
}