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[FastISel][AArch64] Followup commit for 218031 to handle negative offsets too.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218032 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka 2014-09-18 07:04:49 +00:00
parent 22b557d942
commit 4b6f00ad18
2 changed files with 13 additions and 15 deletions
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10
lib/Target/AArch64/AArch64FastISel.cpp
View File

@ -917,11 +917,15 @@ bool AArch64FastISel::simplifyAddress(Address &Addr, MVT VT) {
// Since the offset is too large for the load/store instruction get the
// reg+offset into a register.
if (ImmediateOffsetNeedsLowering) {
unsigned ResultReg = 0;
unsigned ResultReg;
if (Addr.getReg()) {
// Try to fold the immediate into the add instruction.
ResultReg = emitAddSub_ri(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
/*IsKill=*/false, Offset);
if (Offset < 0)
ResultReg = emitAddSub_ri(/*UseAdd=*/false, MVT::i64, Addr.getReg(),
/*IsKill=*/false, -Offset);
else
ResultReg = emitAddSub_ri(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
/*IsKill=*/false, Offset);
if (!ResultReg) {
unsigned ImmReg = fastEmit_i(MVT::i64, MVT::i64, ISD::Constant, Offset);
ResultReg = emitAddSub_rr(/*UseAdd=*/true, MVT::i64, Addr.getReg(),

18
test/CodeGen/AArch64/fast-isel-addressing-modes.ll
View File

@ -130,12 +130,9 @@ define i32 @load_breg_immoff_1(i64 %a) {
; Min not-supported negative offset
define i32 @load_breg_immoff_2(i64 %a) {
; SDAG-LABEL: load_breg_immoff_2
; SDAG: sub [[REG:x[0-9]+]], x0, #257
; SDAG-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
; FAST-LABEL: load_breg_immoff_2
; FAST: add [[REG:x[0-9]+]], x0, {{x[0-9]+}}
; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
; CHECK-LABEL: load_breg_immoff_2
; CHECK: sub [[REG:x[0-9]+]], x0, #257
; CHECK-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
%1 = add i64 %a, -257
%2 = inttoptr i64 %1 to i32*
%3 = load i32* %2
@ -196,12 +193,9 @@ define void @store_breg_immoff_1(i64 %a) {
; Min not-supported negative offset
define void @store_breg_immoff_2(i64 %a) {
; SDAG-LABEL: store_breg_immoff_2
; SDAG: sub [[REG:x[0-9]+]], x0, #257
; SDAG-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
; FAST-LABEL: store_breg_immoff_2
; FAST: add [[REG:x[0-9]+]], x0, {{x[0-9]+}}
; FAST-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
; CHECK-LABEL: store_breg_immoff_2
; CHECK: sub [[REG:x[0-9]+]], x0, #257
; CHECK-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
%1 = add i64 %a, -257
%2 = inttoptr i64 %1 to i32*
store i32 0, i32* %2