From 4b76ffc1ffca2ed016467e916d5223515b485592 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Wed, 7 Jul 2010 00:32:25 +0000 Subject: [PATCH] Revert "Remove references to INSERT_SUBREG after de-SSA" r107725. Buildbot breakage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107744 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/LiveIntervalAnalysis.cpp | 6 ++ lib/CodeGen/LowerSubregs.cpp | 88 ++++++++++++++++++++++- lib/CodeGen/ProcessImplicitDefs.cpp | 15 ++++ lib/CodeGen/RegisterCoalescer.cpp | 2 +- lib/CodeGen/SimpleRegisterCoalescing.cpp | 7 +- lib/CodeGen/StackSlotColoring.cpp | 3 +- lib/CodeGen/TwoAddressInstructionPass.cpp | 24 +++++-- 7 files changed, 136 insertions(+), 9 deletions(-) diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index 7c07c045dc3..a626fc03937 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -324,6 +324,12 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, if (mi->isCopyLike() || tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg)) { CopyMI = mi; + + // Some of the REG_SEQUENCE lowering in TwoAddressInstrPass creates + // implicit defs without really knowing. It shows up as INSERT_SUBREG + // using an undefined register. + if (mi->isInsertSubreg()) + mi->getOperand(1).setIsUndef(); } VNInfo *ValNo = interval.getNextValue(defIndex, CopyMI, true, diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp index eccae52fbcd..172e4b57950 100644 --- a/lib/CodeGen/LowerSubregs.cpp +++ b/lib/CodeGen/LowerSubregs.cpp @@ -54,6 +54,7 @@ namespace { private: bool LowerExtract(MachineInstr *MI); + bool LowerInsert(MachineInstr *MI); bool LowerSubregToReg(MachineInstr *MI); bool LowerCopy(MachineInstr *MI); @@ -237,6 +238,90 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) { return true; } +bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { + MachineBasicBlock *MBB = MI->getParent(); + assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && + (MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) && + (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && + MI->getOperand(3).isImm() && "Invalid insert_subreg"); + + unsigned DstReg = MI->getOperand(0).getReg(); +#ifndef NDEBUG + unsigned SrcReg = MI->getOperand(1).getReg(); +#endif + unsigned InsReg = MI->getOperand(2).getReg(); + unsigned SubIdx = MI->getOperand(3).getImm(); + + assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?"); + assert(SubIdx != 0 && "Invalid index for insert_subreg"); + unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); + assert(DstSubReg && "invalid subregister index for register"); + assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) && + "Insert superreg source must be in a physical register"); + assert(TargetRegisterInfo::isPhysicalRegister(InsReg) && + "Inserted value must be in a physical register"); + + DEBUG(dbgs() << "subreg: CONVERTING: " << *MI); + + if (DstSubReg == InsReg) { + // No need to insert an identity copy instruction. If the SrcReg was + // , we need to make sure it is alive by inserting a KILL + if (MI->getOperand(1).isUndef() && !MI->getOperand(0).isDead()) { + MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), + TII->get(TargetOpcode::KILL), DstReg); + if (MI->getOperand(2).isUndef()) + MIB.addReg(InsReg, RegState::Undef); + else + MIB.addReg(InsReg, RegState::Kill); + } else { + DEBUG(dbgs() << "subreg: eliminated!\n"); + MBB->erase(MI); + return true; + } + } else { + // Insert sub-register copy + const TargetRegisterClass *TRC0= TRI->getPhysicalRegisterRegClass(DstSubReg); + const TargetRegisterClass *TRC1= TRI->getPhysicalRegisterRegClass(InsReg); + if (MI->getOperand(2).isUndef()) + // If the source register being inserted is undef, then this becomes a + // KILL. + BuildMI(*MBB, MI, MI->getDebugLoc(), + TII->get(TargetOpcode::KILL), DstSubReg); + else { + bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1, + MI->getDebugLoc()); + (void)Emitted; + assert(Emitted && "Subreg and Dst must be of compatible register class"); + } + MachineBasicBlock::iterator CopyMI = MI; + --CopyMI; + + // INSERT_SUBREG is a two-address instruction so it implicitly kills SrcReg. + if (!MI->getOperand(1).isUndef()) + CopyMI->addOperand(MachineOperand::CreateReg(DstReg, false, true, true)); + + // Transfer the kill/dead flags, if needed. + if (MI->getOperand(0).isDead()) { + TransferDeadFlag(MI, DstSubReg, TRI); + } else { + // Make sure the full DstReg is live after this replacement. + CopyMI->addOperand(MachineOperand::CreateReg(DstReg, true, true)); + } + + // Make sure the inserted register gets killed + if (MI->getOperand(2).isKill() && !MI->getOperand(2).isUndef()) + TransferKillFlag(MI, InsReg, TRI); + } + + DEBUG({ + MachineBasicBlock::iterator dMI = MI; + dbgs() << "subreg: " << *(--dMI) << "\n"; + }); + + MBB->erase(MI); + return true; +} + bool LowerSubregsInstructionPass::LowerCopy(MachineInstr *MI) { MachineOperand &DstMO = MI->getOperand(0); MachineOperand &SrcMO = MI->getOperand(1); @@ -302,9 +387,10 @@ bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) { mi != me;) { MachineBasicBlock::iterator nmi = llvm::next(mi); MachineInstr *MI = mi; - assert(!MI->isInsertSubreg() && "INSERT_SUBREG should no longer appear"); if (MI->isExtractSubreg()) { MadeChange |= LowerExtract(MI); + } else if (MI->isInsertSubreg()) { + MadeChange |= LowerInsert(MI); } else if (MI->isSubregToReg()) { MadeChange |= LowerSubregToReg(MI); } else if (MI->isCopy()) { diff --git a/lib/CodeGen/ProcessImplicitDefs.cpp b/lib/CodeGen/ProcessImplicitDefs.cpp index 2caef08b509..80121ca0f29 100644 --- a/lib/CodeGen/ProcessImplicitDefs.cpp +++ b/lib/CodeGen/ProcessImplicitDefs.cpp @@ -102,6 +102,21 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) { continue; } + if (MI->isInsertSubreg()) { + MachineOperand &MO = MI->getOperand(2); + if (ImpDefRegs.count(MO.getReg())) { + // %reg1032 = INSERT_SUBREG %reg1032, undef, 2 + // This is an identity copy, eliminate it now. + if (MO.isKill()) { + LiveVariables::VarInfo& vi = lv_->getVarInfo(MO.getReg()); + vi.removeKill(MI); + } + MI->eraseFromParent(); + Changed = true; + continue; + } + } + // Eliminate %reg1032:sub = COPY undef. if (MI->isCopy() && MI->getOperand(0).getSubReg()) { MachineOperand &MO = MI->getOperand(1); diff --git a/lib/CodeGen/RegisterCoalescer.cpp b/lib/CodeGen/RegisterCoalescer.cpp index 35b5b7eab1a..1aeedaaa852 100644 --- a/lib/CodeGen/RegisterCoalescer.cpp +++ b/lib/CodeGen/RegisterCoalescer.cpp @@ -54,7 +54,7 @@ bool CoalescerPair::isMoveInstr(const MachineInstr *MI, DstSub = MI->getOperand(0).getSubReg(); Src = MI->getOperand(1).getReg(); SrcSub = compose(MI->getOperand(1).getSubReg(), MI->getOperand(2).getImm()); - } else if (MI->isSubregToReg()) { + } else if (MI->isInsertSubreg() || MI->isSubregToReg()) { Dst = MI->getOperand(0).getReg(); DstSub = compose(MI->getOperand(0).getSubReg(), MI->getOperand(3).getImm()); Src = MI->getOperand(2).getReg(); diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp index 73db174117b..e0b9f0c10f6 100644 --- a/lib/CodeGen/SimpleRegisterCoalescing.cpp +++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp @@ -1523,7 +1523,12 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB, if (Inst->isCopy() || Inst->isExtractSubreg()) { DstReg = Inst->getOperand(0).getReg(); SrcReg = Inst->getOperand(1).getReg(); - } else if (Inst->isSubregToReg()) { + } else if (Inst->isInsertSubreg()) { + DstReg = Inst->getOperand(0).getReg(); + SrcReg = Inst->getOperand(2).getReg(); + if (Inst->getOperand(1).isUndef()) + isInsUndef = true; + } else if (Inst->isInsertSubreg() || Inst->isSubregToReg()) { DstReg = Inst->getOperand(0).getReg(); SrcReg = Inst->getOperand(2).getReg(); } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) diff --git a/lib/CodeGen/StackSlotColoring.cpp b/lib/CodeGen/StackSlotColoring.cpp index 5172f3a24bf..7f3b452f0a5 100644 --- a/lib/CodeGen/StackSlotColoring.cpp +++ b/lib/CodeGen/StackSlotColoring.cpp @@ -508,7 +508,8 @@ bool StackSlotColoring::PropagateBackward(MachineBasicBlock::iterator MII, // Abort the use is actually a sub-register def. We don't have enough // information to figure out if it is really legal. - if (MO.getSubReg() || MII->isExtractSubreg() || MII->isSubregToReg()) + if (MO.getSubReg() || MII->isExtractSubreg() || + MII->isInsertSubreg() || MII->isSubregToReg()) return false; const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI); diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp index 48ced83b3b2..efe14e6b28a 100644 --- a/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -1359,11 +1359,25 @@ TwoAddressInstructionPass::CoalesceExtSubRegs(SmallVector &Srcs, // Insert a copy or an extract to replace the original extracts. MachineBasicBlock::iterator InsertLoc = SomeMI; - MachineInstr *CopyMI = BuildMI(*SomeMI->getParent(), SomeMI, - SomeMI->getDebugLoc(), - TII->get(TargetOpcode::COPY)) - .addReg(DstReg, RegState::Define, NewDstSubIdx) - .addReg(SrcReg, 0, NewSrcSubIdx); + if (NewSrcSubIdx) { + // Insert an extract subreg. + BuildMI(*SomeMI->getParent(), InsertLoc, SomeMI->getDebugLoc(), + TII->get(TargetOpcode::EXTRACT_SUBREG), DstReg) + .addReg(SrcReg).addImm(NewSrcSubIdx); + } else if (NewDstSubIdx) { + // Do a subreg insertion. + BuildMI(*SomeMI->getParent(), InsertLoc, SomeMI->getDebugLoc(), + TII->get(TargetOpcode::INSERT_SUBREG), DstReg) + .addReg(DstReg).addReg(SrcReg).addImm(NewDstSubIdx); + } else { + // Insert a copy. + bool Emitted = + TII->copyRegToReg(*SomeMI->getParent(), InsertLoc, DstReg, SrcReg, + MRI->getRegClass(DstReg), MRI->getRegClass(SrcReg), + SomeMI->getDebugLoc()); + (void)Emitted; + } + MachineBasicBlock::iterator CopyMI = prior(InsertLoc); // Remove all the old extract instructions. for (MachineRegisterInfo::use_nodbg_iterator