mirror of
https://github.com/RPCS3/llvm.git
synced 2024-12-30 16:34:03 +00:00
Added Nate's div by constant stuff, also scaled operations!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21116 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
parent
ce91ec9ae6
commit
4b8ac1559a
@ -58,25 +58,29 @@ namespace {
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addRegisterClass(MVT::f64, Alpha::FPRCRegisterClass);
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addRegisterClass(MVT::f32, Alpha::FPRCRegisterClass);
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setOperationAction(ISD::EXTLOAD , MVT::i1 , Promote);
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setOperationAction(ISD::EXTLOAD , MVT::f32 , Promote);
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setOperationAction(ISD::EXTLOAD , MVT::i1 , Promote);
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setOperationAction(ISD::EXTLOAD , MVT::f32 , Promote);
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setOperationAction(ISD::ZEXTLOAD , MVT::i1 , Expand);
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setOperationAction(ISD::ZEXTLOAD , MVT::i32 , Expand);
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setOperationAction(ISD::ZEXTLOAD , MVT::i1 , Expand);
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setOperationAction(ISD::ZEXTLOAD , MVT::i32 , Expand);
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setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
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setOperationAction(ISD::SEXTLOAD , MVT::i8 , Expand);
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setOperationAction(ISD::SEXTLOAD , MVT::i16 , Expand);
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setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
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setOperationAction(ISD::SEXTLOAD , MVT::i8 , Expand);
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setOperationAction(ISD::SEXTLOAD , MVT::i16 , Expand);
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setOperationAction(ISD::SREM , MVT::f32 , Expand);
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setOperationAction(ISD::SREM , MVT::f64 , Expand);
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setOperationAction(ISD::SREM , MVT::f32 , Expand);
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setOperationAction(ISD::SREM , MVT::f64 , Expand);
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setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
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setOperationAction(ISD::MEMSET , MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
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//If this didn't legalize into a div....
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// setOperationAction(ISD::SREM , MVT::i64, Expand);
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// setOperationAction(ISD::UREM , MVT::i64, Expand);
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setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
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setOperationAction(ISD::MEMSET , MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
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//Doesn't work yet
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setOperationAction(ISD::SETCC , MVT::f32, Promote);
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setOperationAction(ISD::SETCC , MVT::f32, Promote);
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computeRegisterProperties();
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@ -335,7 +339,10 @@ class ISel : public SelectionDAGISel {
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/// Alpha-specific SelectionDAG.
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AlphaTargetLowering AlphaLowering;
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SelectionDAG *ISelDAG; // Hack to support us having a dag->dag transform
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// for sdiv and udiv until it is put into the future
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// dag combiner.
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/// ExprMap - As shared expressions are codegen'd, we keep track of which
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/// vreg the value is produced in, so we only emit one copy of each compiled
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/// tree.
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@ -354,6 +361,7 @@ public:
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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// Codegen the basic block.
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ISelDAG = &DAG;
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Select(DAG.getRoot());
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// Clear state used for selection.
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@ -371,9 +379,162 @@ public:
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void MoveInt2FP(unsigned src, unsigned dst, bool isDouble);
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//returns whether the sense of the comparison was inverted
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bool SelectFPSetCC(SDOperand N, unsigned dst);
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// dag -> dag expanders for integer divide by constant
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SDOperand BuildSDIVSequence(SDOperand N);
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SDOperand BuildUDIVSequence(SDOperand N);
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};
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}
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//Shamelessly adapted from PPC32
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// Structure used to return the necessary information to codegen an SDIV as
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// a multiply.
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struct ms {
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int64_t m; // magic number
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int64_t s; // shift amount
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};
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struct mu {
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uint64_t m; // magic number
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int64_t a; // add indicator
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int64_t s; // shift amount
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};
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/// magic - calculate the magic numbers required to codegen an integer sdiv as
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/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
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/// or -1.
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static struct ms magic(int64_t d) {
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int64_t p;
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uint64_t ad, anc, delta, q1, r1, q2, r2, t;
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const uint64_t two63 = 9223372036854775808ULL; // 2^63
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struct ms mag;
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ad = abs(d);
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t = two63 + ((uint64_t)d >> 63);
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anc = t - 1 - t%ad; // absolute value of nc
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p = 31; // initialize p
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q1 = two63/anc; // initialize q1 = 2p/abs(nc)
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r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
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q2 = two63/ad; // initialize q2 = 2p/abs(d)
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r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
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do {
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p = p + 1;
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q1 = 2*q1; // update q1 = 2p/abs(nc)
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r1 = 2*r1; // update r1 = rem(2p/abs(nc))
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if (r1 >= anc) { // must be unsigned comparison
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q1 = q1 + 1;
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r1 = r1 - anc;
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}
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q2 = 2*q2; // update q2 = 2p/abs(d)
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r2 = 2*r2; // update r2 = rem(2p/abs(d))
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if (r2 >= ad) { // must be unsigned comparison
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q2 = q2 + 1;
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r2 = r2 - ad;
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}
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delta = ad - r2;
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} while (q1 < delta || (q1 == delta && r1 == 0));
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mag.m = q2 + 1;
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if (d < 0) mag.m = -mag.m; // resulting magic number
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mag.s = p - 64; // resulting shift
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return mag;
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}
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/// magicu - calculate the magic numbers required to codegen an integer udiv as
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/// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
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static struct mu magicu(uint64_t d)
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{
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int64_t p;
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uint64_t nc, delta, q1, r1, q2, r2;
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struct mu magu;
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magu.a = 0; // initialize "add" indicator
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nc = - 1 - (-d)%d;
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p = 31; // initialize p
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q1 = 0x8000000000000000/nc; // initialize q1 = 2p/nc
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r1 = 0x8000000000000000 - q1*nc; // initialize r1 = rem(2p,nc)
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q2 = 0x7FFFFFFFFFFFFFFF/d; // initialize q2 = (2p-1)/d
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r2 = 0x7FFFFFFFFFFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
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do {
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p = p + 1;
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if (r1 >= nc - r1 ) {
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q1 = 2*q1 + 1; // update q1
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r1 = 2*r1 - nc; // update r1
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}
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else {
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q1 = 2*q1; // update q1
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r1 = 2*r1; // update r1
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}
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if (r2 + 1 >= d - r2) {
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if (q2 >= 0x7FFFFFFFFFFFFFFF) magu.a = 1;
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q2 = 2*q2 + 1; // update q2
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r2 = 2*r2 + 1 - d; // update r2
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}
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else {
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if (q2 >= 0x8000000000000000) magu.a = 1;
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q2 = 2*q2; // update q2
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r2 = 2*r2 + 1; // update r2
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}
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delta = d - 1 - r2;
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} while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
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magu.m = q2 + 1; // resulting magic number
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magu.s = p - 32; // resulting shift
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return magu;
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}
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/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
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/// return a DAG expression to select that will generate the same value by
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/// multiplying by a magic number. See:
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/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
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SDOperand ISel::BuildSDIVSequence(SDOperand N) {
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int d = (int)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
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ms magics = magic(d);
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// Multiply the numerator (operand 0) by the magic value
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SDOperand Q = ISelDAG->getNode(ISD::MULHS, MVT::i64, N.getOperand(0),
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ISelDAG->getConstant(magics.m, MVT::i64));
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// If d > 0 and m < 0, add the numerator
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if (d > 0 && magics.m < 0)
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Q = ISelDAG->getNode(ISD::ADD, MVT::i64, Q, N.getOperand(0));
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// If d < 0 and m > 0, subtract the numerator.
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if (d < 0 && magics.m > 0)
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Q = ISelDAG->getNode(ISD::SUB, MVT::i64, Q, N.getOperand(0));
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// Shift right algebraic if shift value is nonzero
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if (magics.s > 0)
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Q = ISelDAG->getNode(ISD::SRA, MVT::i64, Q,
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ISelDAG->getConstant(magics.s, MVT::i64));
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// Extract the sign bit and add it to the quotient
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SDOperand T =
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ISelDAG->getNode(ISD::SRL, MVT::i64, Q, ISelDAG->getConstant(63, MVT::i64));
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return ISelDAG->getNode(ISD::ADD, MVT::i64, Q, T);
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}
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/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
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/// return a DAG expression to select that will generate the same value by
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/// multiplying by a magic number. See:
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/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
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SDOperand ISel::BuildUDIVSequence(SDOperand N) {
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unsigned d =
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(unsigned)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
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mu magics = magicu(d);
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// Multiply the numerator (operand 0) by the magic value
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SDOperand Q = ISelDAG->getNode(ISD::MULHU, MVT::i64, N.getOperand(0),
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ISelDAG->getConstant(magics.m, MVT::i64));
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if (magics.a == 0) {
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Q = ISelDAG->getNode(ISD::SRL, MVT::i64, Q,
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ISelDAG->getConstant(magics.s, MVT::i64));
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} else {
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SDOperand NPQ = ISelDAG->getNode(ISD::SUB, MVT::i64, N.getOperand(0), Q);
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NPQ = ISelDAG->getNode(ISD::SRL, MVT::i64, NPQ,
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ISelDAG->getConstant(1, MVT::i64));
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NPQ = ISelDAG->getNode(ISD::ADD, MVT::i64, NPQ, Q);
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Q = ISelDAG->getNode(ISD::SRL, MVT::i64, NPQ,
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ISelDAG->getConstant(magics.s-1, MVT::i64));
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}
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return Q;
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}
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//These describe LDAx
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static const int IMM_LOW = -32768;
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static const int IMM_HIGH = 32767;
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@ -959,7 +1120,26 @@ unsigned ISel::SelectExpr(SDOperand N) {
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Node->dump();
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assert(0 && "Node not handled!\n");
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case ISD::MULHU:
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Alpha::UMULH, 2, Result).addReg(Tmp1).addReg(Tmp2);
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case ISD::MULHS:
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{
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//MULHU - Ra<63>*Rb - Rb<63>*Ra
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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Tmp3 = MakeReg(MVT::i64);
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BuildMI(BB, Alpha::UMULH, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
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unsigned V1 = MakeReg(MVT::i64);
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unsigned V2 = MakeReg(MVT::i64);
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BuildMI(BB, Alpha::CMOVGE, 3, V1).addReg(Tmp2).addReg(Alpha::R31).addReg(Tmp1);
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BuildMI(BB, Alpha::CMOVGE, 3, V2).addReg(Tmp1).addReg(Alpha::R31).addReg(Tmp2);
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unsigned IRes = MakeReg(MVT::i64);
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BuildMI(BB, Alpha::SUBQ, 2, IRes).addReg(Tmp3).addReg(V1);
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BuildMI(BB, Alpha::SUBQ, 2, Result).addReg(IRes).addReg(V2);
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return Result;
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}
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case ISD::UNDEF: {
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BuildMI(BB, Alpha::IDEF, 0, Result);
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return Result;
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@ -1517,8 +1697,43 @@ unsigned ISel::SelectExpr(SDOperand N) {
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{
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bool isAdd = opcode == ISD::ADD;
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//FIXME: first check for Scaled Adds and Subs!
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if(N.getOperand(1).getOpcode() == ISD::Constant &&
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//first check for Scaled Adds and Subs!
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//Valid for add and sub
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if(N.getOperand(0).getOpcode() == ISD::SHL &&
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N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue() == 2)
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{
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Tmp1 = SelectExpr(N.getOperand(1));
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Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
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BuildMI(BB, isAdd?Alpha::S4ADDQ:Alpha::S4SUBQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
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}
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else if(N.getOperand(0).getOpcode() == ISD::SHL &&
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N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue() == 3)
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{
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Tmp1 = SelectExpr(N.getOperand(1));
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Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
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BuildMI(BB, isAdd?Alpha::S4ADDQ:Alpha::S8SUBQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
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}
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//Position prevents subs
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else if(N.getOperand(1).getOpcode() == ISD::SHL && isAdd &
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N.getOperand(1).getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() == 2)
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{
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
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BuildMI(BB, Alpha::S8ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
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}
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else if(N.getOperand(0).getOpcode() == ISD::SHL && isAdd &&
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N.getOperand(1).getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() == 3)
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{
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
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BuildMI(BB, Alpha::S8ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
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}
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//small addi
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else if(N.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
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{ //Normal imm add/sub
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Opc = isAdd ? Alpha::ADDQi : Alpha::SUBQi;
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@ -1526,6 +1741,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
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}
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//larger addi
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else if(N.getOperand(1).getOpcode() == ISD::Constant &&
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(cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 32767 ||
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(long)cast<ConstantSDNode>(N.getOperand(1))->getValue() >= -32767))
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@ -1535,7 +1751,9 @@ unsigned ISel::SelectExpr(SDOperand N) {
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if (!isAdd)
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Tmp2 = -Tmp2;
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BuildMI(BB, Alpha::LDA, 2, Result).addImm(Tmp2).addReg(Tmp1);
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} else {
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}
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//give up and do the operation
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else {
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//Normal add/sub
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Opc = isAdd ? Alpha::ADDQ : Alpha::SUBQ;
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Tmp1 = SelectExpr(N.getOperand(0));
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@ -1546,9 +1764,22 @@ unsigned ISel::SelectExpr(SDOperand N) {
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}
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case ISD::SDIV:
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case ISD::UDIV:
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if (N.getOperand(1).getOpcode() == ISD::Constant &&
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((int64_t)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended() >= 2 ||
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(int64_t)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended() <= -2))
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{
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// If this is a divide by constant, we can emit code using some magic
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// constants to implement it as a multiply instead.
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ExprMap.erase(N);
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if (opcode == ISD::SDIV)
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return SelectExpr(BuildSDIVSequence(N));
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else
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return SelectExpr(BuildUDIVSequence(N));
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}
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//else fall though
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case ISD::UREM:
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case ISD::SREM:
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case ISD::UDIV:
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//FIXME: alpha really doesn't support any of these operations,
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// the ops are expanded into special library calls with
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// special calling conventions
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