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AMDGPU: sext_inreg (srl x, K), vt -> bfe x, K, vt.Size
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267244 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
0983344233
commit
4bfa27af78
@ -531,6 +531,7 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
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case ISD::AND:
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case ISD::SRL:
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case ISD::SRA:
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case ISD::SIGN_EXTEND_INREG:
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if (N->getValueType(0) != MVT::i32 ||
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Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
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break;
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@ -1478,6 +1479,21 @@ SDNode *AMDGPUDAGToDAGISel::SelectS_BFE(SDNode *N) {
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if (N->getOperand(0).getOpcode() == ISD::SHL)
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return SelectS_BFEFromShifts(N);
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break;
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case ISD::SIGN_EXTEND_INREG: {
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// sext_inreg (srl x, 16), i8 -> bfe_i32 x, 16, 8
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SDValue Src = N->getOperand(0);
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if (Src.getOpcode() != ISD::SRL)
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break;
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const ConstantSDNode *Amt = dyn_cast<ConstantSDNode>(Src.getOperand(1));
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if (!Amt)
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break;
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unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits();
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return getS_BFE(AMDGPU::S_BFE_I32, SDLoc(N), Src.getOperand(0),
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Amt->getZExtValue(), Width);
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}
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}
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return SelectCode(N);
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@ -1,9 +1,9 @@
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; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; SI-LABEL: {{^}}s_sext_i1_to_i32:
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; SI: v_cndmask_b32_e64
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; SI: s_endpgm
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; GCN-LABEL: {{^}}s_sext_i1_to_i32:
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; GCN: v_cndmask_b32_e64
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; GCN: s_endpgm
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define void @s_sext_i1_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%cmp = icmp eq i32 %a, %b
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%sext = sext i1 %cmp to i32
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@ -11,9 +11,9 @@ define void @s_sext_i1_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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ret void
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}
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; SI-LABEL: {{^}}test_s_sext_i32_to_i64:
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; SI: s_ashr_i32
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; SI: s_endpg
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; GCN-LABEL: {{^}}test_s_sext_i32_to_i64:
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; GCN: s_ashr_i32
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; GCN: s_endpg
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define void @test_s_sext_i32_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) nounwind {
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entry:
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%mul = mul i32 %a, %b
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@ -23,11 +23,11 @@ entry:
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ret void
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}
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; SI-LABEL: {{^}}s_sext_i1_to_i64:
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; SI: v_cndmask_b32_e64 v[[LOREG:[0-9]+]], 0, -1, vcc
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; SI: v_mov_b32_e32 v[[HIREG:[0-9]+]], v[[LOREG]]
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; SI: buffer_store_dwordx2 v{{\[}}[[LOREG]]:[[HIREG]]{{\]}}
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; SI: s_endpgm
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; GCN-LABEL: {{^}}s_sext_i1_to_i64:
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; GCN: v_cndmask_b32_e64 v[[LOREG:[0-9]+]], 0, -1, vcc
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; GCN: v_mov_b32_e32 v[[HIREG:[0-9]+]], v[[LOREG]]
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; GCN: buffer_store_dwordx2 v{{\[}}[[LOREG]]:[[HIREG]]{{\]}}
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; GCN: s_endpgm
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define void @s_sext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%cmp = icmp eq i32 %a, %b
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%sext = sext i1 %cmp to i64
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@ -35,18 +35,18 @@ define void @s_sext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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ret void
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}
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; SI-LABEL: {{^}}s_sext_i32_to_i64:
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; SI: s_ashr_i32
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; SI: s_endpgm
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; GCN-LABEL: {{^}}s_sext_i32_to_i64:
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; GCN: s_ashr_i32
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; GCN: s_endpgm
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define void @s_sext_i32_to_i64(i64 addrspace(1)* %out, i32 %a) nounwind {
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%sext = sext i32 %a to i64
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store i64 %sext, i64 addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL: {{^}}v_sext_i32_to_i64:
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; SI: v_ashr
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; SI: s_endpgm
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; GCN-LABEL: {{^}}v_sext_i32_to_i64:
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; GCN: v_ashr
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; GCN: s_endpgm
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define void @v_sext_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%val = load i32, i32 addrspace(1)* %in, align 4
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%sext = sext i32 %val to i64
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@ -54,10 +54,112 @@ define void @v_sext_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) no
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ret void
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}
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; SI-LABEL: {{^}}s_sext_i16_to_i64:
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; SI: s_endpgm
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; GCN-LABEL: {{^}}s_sext_i16_to_i64:
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; GCN: s_endpgm
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define void @s_sext_i16_to_i64(i64 addrspace(1)* %out, i16 %a) nounwind {
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%sext = sext i16 %a to i64
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store i64 %sext, i64 addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}s_sext_v4i8_to_v4i32:
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; GCN: s_load_dword [[VAL:s[0-9]+]]
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; GCN-DAG: s_sext_i32_i8 [[EXT0:s[0-9]+]], [[VAL]]
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; GCN-DAG: s_bfe_i32 [[EXT1:s[0-9]+]], [[VAL]], 0x80008
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; GCN-DAG: s_bfe_i32 [[EXT2:s[0-9]+]], [[VAL]], 0x80010
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; GCN-DAG: s_ashr_i32 [[EXT3:s[0-9]+]], [[VAL]], 24
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; GCN-DAG: v_mov_b32_e32 [[VEXT0:v[0-9]+]], [[EXT0]]
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; GCN-DAG: v_mov_b32_e32 [[VEXT1:v[0-9]+]], [[EXT1]]
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; GCN-DAG: v_mov_b32_e32 [[VEXT2:v[0-9]+]], [[EXT2]]
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; GCN-DAG: v_mov_b32_e32 [[VEXT3:v[0-9]+]], [[EXT3]]
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; GCN-DAG: buffer_store_dword [[VEXT0]]
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; GCN-DAG: buffer_store_dword [[VEXT1]]
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; GCN-DAG: buffer_store_dword [[VEXT2]]
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; GCN-DAG: buffer_store_dword [[VEXT3]]
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; GCN: s_endpgm
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define void @s_sext_v4i8_to_v4i32(i32 addrspace(1)* %out, i32 %a) nounwind {
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%cast = bitcast i32 %a to <4 x i8>
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%ext = sext <4 x i8> %cast to <4 x i32>
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%elt0 = extractelement <4 x i32> %ext, i32 0
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%elt1 = extractelement <4 x i32> %ext, i32 1
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%elt2 = extractelement <4 x i32> %ext, i32 2
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%elt3 = extractelement <4 x i32> %ext, i32 3
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store volatile i32 %elt0, i32 addrspace(1)* %out
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store volatile i32 %elt1, i32 addrspace(1)* %out
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store volatile i32 %elt2, i32 addrspace(1)* %out
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store volatile i32 %elt3, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_sext_v4i8_to_v4i32:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]]
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; GCN-DAG: v_bfe_i32 [[EXT0:v[0-9]+]], [[VAL]], 0, 8
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; GCN-DAG: v_bfe_i32 [[EXT1:v[0-9]+]], [[VAL]], 8, 8
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; GCN-DAG: v_bfe_i32 [[EXT2:v[0-9]+]], [[VAL]], 16, 8
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; GCN-DAG: v_ashrrev_i32_e32 [[EXT3:v[0-9]+]], 24, [[VAL]]
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; GCN: buffer_store_dword [[EXT0]]
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; GCN: buffer_store_dword [[EXT1]]
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; GCN: buffer_store_dword [[EXT2]]
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; GCN: buffer_store_dword [[EXT3]]
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define void @v_sext_v4i8_to_v4i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%a = load i32, i32 addrspace(1)* %in
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%cast = bitcast i32 %a to <4 x i8>
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%ext = sext <4 x i8> %cast to <4 x i32>
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%elt0 = extractelement <4 x i32> %ext, i32 0
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%elt1 = extractelement <4 x i32> %ext, i32 1
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%elt2 = extractelement <4 x i32> %ext, i32 2
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%elt3 = extractelement <4 x i32> %ext, i32 3
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store volatile i32 %elt0, i32 addrspace(1)* %out
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store volatile i32 %elt1, i32 addrspace(1)* %out
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store volatile i32 %elt2, i32 addrspace(1)* %out
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store volatile i32 %elt3, i32 addrspace(1)* %out
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ret void
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}
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; FIXME: s_bfe_i64
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; GCN-LABEL: {{^}}s_sext_v4i16_to_v4i32:
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; GCN-DAG: s_ashr_i64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 48
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; GCN-DAG: s_ashr_i32 s{{[0-9]+}}, s{{[0-9]+}}, 16
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; GCN-DAG: s_sext_i32_i16
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; GCN-DAG: s_sext_i32_i16
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; GCN: s_endpgm
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define void @s_sext_v4i16_to_v4i32(i32 addrspace(1)* %out, i64 %a) nounwind {
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%cast = bitcast i64 %a to <4 x i16>
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%ext = sext <4 x i16> %cast to <4 x i32>
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%elt0 = extractelement <4 x i32> %ext, i32 0
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%elt1 = extractelement <4 x i32> %ext, i32 1
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%elt2 = extractelement <4 x i32> %ext, i32 2
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%elt3 = extractelement <4 x i32> %ext, i32 3
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store volatile i32 %elt0, i32 addrspace(1)* %out
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store volatile i32 %elt1, i32 addrspace(1)* %out
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store volatile i32 %elt2, i32 addrspace(1)* %out
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store volatile i32 %elt3, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_sext_v4i16_to_v4i32:
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; SI-DAG: v_ashr_i64 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, 48
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; VI-DAG: v_ashrrev_i64 v{{\[[0-9]+:[0-9]+\]}}, 48, v{{\[[0-9]+:[0-9]+\]}}
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; GCN-DAG: v_ashrrev_i32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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; GCN-DAG: v_ashrrev_i32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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; GCN-DAG: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16
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; GCN-DAG: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16
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; GCN: s_endpgm
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define void @v_sext_v4i16_to_v4i32(i32 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind {
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%a = load i64, i64 addrspace(1)* %in
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%cast = bitcast i64 %a to <4 x i16>
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%ext = sext <4 x i16> %cast to <4 x i32>
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%elt0 = extractelement <4 x i32> %ext, i32 0
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%elt1 = extractelement <4 x i32> %ext, i32 1
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%elt2 = extractelement <4 x i32> %ext, i32 2
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%elt3 = extractelement <4 x i32> %ext, i32 3
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store volatile i32 %elt0, i32 addrspace(1)* %out
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store volatile i32 %elt1, i32 addrspace(1)* %out
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store volatile i32 %elt2, i32 addrspace(1)* %out
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store volatile i32 %elt3, i32 addrspace(1)* %out
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ret void
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}
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