RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-12-19 01:48:34 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

simplify some code and eliminate the symbolicAddressesAreRIPRel() predicate.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74377 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2009-06-27 05:24:12 +00:00
parent de53dc03f5
commit 4c1b606ecd
3 changed files with 4 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
lib/Target/X86/X86FastISel.cpp
View File

@ -396,8 +396,7 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
// Constant-offset addressing.
Disp += CI->getSExtValue() * S;
} else if (IndexReg == 0 &&
(!AM.GV ||
!getTargetMachine()->symbolicAddressesAreRIPRel()) &&
(!AM.GV || !Subtarget->isPICStyleRIPRel()) &&
(S == 1 || S == 2 || S == 4 || S == 8)) {
// Scaled-index addressing.
Scale = S;
@ -432,7 +431,7 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
return false;
// RIP-relative addresses can't have additional register operands.
if (getTargetMachine()->symbolicAddressesAreRIPRel() &&
if (Subtarget->isPICStyleRIPRel() &&
(AM.Base.Reg != 0 || AM.IndexReg != 0))
return false;
@ -482,7 +481,7 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
// Prevent loading GV stub multiple times in same MBB.
LocalValueMap[V] = AM.Base.Reg;
} else if (getTargetMachine()->symbolicAddressesAreRIPRel()) {
} else if (Subtarget->isPICStyleRIPRel()) {
// Use rip-relative addressing if we can.
AM.Base.Reg = X86::RIP;
}
@ -491,7 +490,7 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
}
// If all else fails, try to materialize the value in a register.
if (!AM.GV || !getTargetMachine()->symbolicAddressesAreRIPRel()) {
if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
if (AM.Base.Reg == 0) {
AM.Base.Reg = getRegForValue(V);
return AM.Base.Reg != 0;

8
lib/Target/X86/X86TargetMachine.cpp
View File

@ -318,11 +318,3 @@ bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
return false;
}
/// symbolicAddressesAreRIPRel - Return true if symbolic addresses are
/// RIP-relative on this machine, taking into consideration the relocation
/// model and subtarget. RIP-relative addresses cannot have a separate
/// base or index register.
bool X86TargetMachine::symbolicAddressesAreRIPRel() const {
return getRelocationModel() != Reloc::Static &&
Subtarget.isPICStyleRIPRel();
}

6
lib/Target/X86/X86TargetMachine.h
View File

@ -91,12 +91,6 @@ public:
virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
bool DumpAsm, JITCodeEmitter &JCE);
/// symbolicAddressesAreRIPRel - Return true if symbolic addresses are
/// RIP-relative on this machine, taking into consideration the relocation
/// model and subtarget. RIP-relative addresses cannot have a separate
/// base or index register.
bool symbolicAddressesAreRIPRel() const;
};
/// X86_32TargetMachine - X86 32-bit target machine.