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Add SelectionDAG::getNOT method to construct bitwise NOT operations,

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corresponding to the "not" and "vnot" PatFrags.  Use the new method
in some places where it seems appropriate.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62768 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2009-01-22 17:39:32 +00:00
parent 10dfea82d2
commit 4c24546238
6 changed files with 44 additions and 34 deletions
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3
include/llvm/CodeGen/SelectionDAG.h
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@ -366,6 +366,9 @@ public:
/// value assuming it was the smaller SrcTy value.
SDValue getZeroExtendInReg(SDValue Op, MVT SrcTy);
/// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
SDValue getNOT(SDValue Val, MVT VT);
/// getCALLSEQ_START - Return a new CALLSEQ_START node, which always must have
/// a flag result (to ensure it's not CSE'd).
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op) {

15
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -2759,15 +2759,15 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) {
}
// fold select C, 0, X -> ~C & X
if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
AddToWorkList(XORNode.getNode());
return DAG.getNode(ISD::AND, VT, XORNode, N2);
SDValue NOTNode = DAG.getNOT(N0, VT);
AddToWorkList(NOTNode.getNode());
return DAG.getNode(ISD::AND, VT, NOTNode, N2);
}
// fold select C, X, 1 -> ~C | X
if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
AddToWorkList(XORNode.getNode());
return DAG.getNode(ISD::OR, VT, XORNode, N1);
SDValue NOTNode = DAG.getNOT(N0, VT);
AddToWorkList(NOTNode.getNode());
return DAG.getNode(ISD::OR, VT, NOTNode, N1);
}
// fold select C, X, 0 -> C & X
// FIXME: this should check for C type == X type, not i1?
@ -5574,8 +5574,7 @@ SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
SDValue NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
N0);
SDValue NotN0 = DAG.getNode(ISD::XOR, XType, N0,
DAG.getConstant(~0ULL, XType));
SDValue NotN0 = DAG.getNOT(N0, XType);
return DAG.getNode(ISD::SRL, XType,
DAG.getNode(ISD::AND, XType, NegN0, NotN0),
DAG.getConstant(XType.getSizeInBits()-1,

6
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -6318,7 +6318,7 @@ SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
}
Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
Op = DAG.getNOT(Op, VT);
return DAG.getNode(ISD::CTPOP, VT, Op);
}
case ISD::CTTZ: {
@ -6327,9 +6327,7 @@ SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
// { return 32 - nlz(~x & (x-1)); }
// see also http://www.hackersdelight.org/HDcode/ntz.cc
MVT VT = Op.getValueType();
SDValue Tmp2 = DAG.getConstant(~0ULL, VT);
SDValue Tmp3 = DAG.getNode(ISD::AND, VT,
DAG.getNode(ISD::XOR, VT, Op, Tmp2),
SDValue Tmp3 = DAG.getNode(ISD::AND, VT, DAG.getNOT(Op, VT),
DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
// If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&

15
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -816,6 +816,21 @@ SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, MVT VT) {
getConstant(Imm, Op.getValueType()));
}
/// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
///
SDValue SelectionDAG::getNOT(SDValue Val, MVT VT) {
SDValue NegOne;
if (VT.isVector()) {
MVT EltVT = VT.getVectorElementType();
SDValue NegOneElt = getConstant(EltVT.getIntegerVTBitMask(), EltVT);
std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOneElt);
NegOne = getNode(ISD::BUILD_VECTOR, VT, &NegOnes[0], NegOnes.size());
} else
NegOne = getConstant(VT.getIntegerVTBitMask(), VT);
return getNode(ISD::XOR, VT, Val, NegOne);
}
SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) {
MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT);

28
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@ -1798,39 +1798,39 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
if (N0.getValueType() == MVT::i1 && foldBooleans) {
switch (Cond) {
default: assert(0 && "Unknown integer setcc!");
case ISD::SETEQ: // X == Y -> (X^Y)^1
case ISD::SETEQ: // X == Y -> ~(X^Y)
Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
N0 = DAG.getNOT(Temp, MVT::i1);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETNE: // X != Y --> (X^Y)
N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
break;
case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
Temp = DAG.getNOT(N0, MVT::i1);
N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
Temp = DAG.getNOT(N1, MVT::i1);
N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
Temp = DAG.getNOT(N0, MVT::i1);
N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
Temp = DAG.getNOT(N1, MVT::i1);
N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
break;
}

11
lib/Target/X86/X86ISelLowering.cpp
View File

@ -5253,14 +5253,9 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
SDValue Result = DAG.getNode(Opc, VT, Op0, Op1);
// If the logical-not of the result is required, perform that now.
if (Invert) {
MVT EltVT = VT.getVectorElementType();
SDValue NegOne = DAG.getConstant(EltVT.getIntegerVTBitMask(), EltVT);
std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOne);
SDValue NegOneV = DAG.getNode(ISD::BUILD_VECTOR, VT, &NegOnes[0],
NegOnes.size());
Result = DAG.getNode(ISD::XOR, VT, Result, NegOneV);
}
if (Invert)
Result = DAG.getNOT(Result, VT);
return Result;
}