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Now that we have operand info for machine instructions, use it to create

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temporary registers for things that define a register.  This allows dag->dag
isel to compile this:

int %test() { ret int 65535 }

into:

_test:
        lis r2, 0
        ori r2, r2, 65535
        blr

Next up, getting CopyFromReg to work, allowing arguments and cross-bb values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22932 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-08-19 20:45:43 +00:00
parent 8d30c23d26
commit 4ccd406317
1 changed files with 21 additions and 8 deletions
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29
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
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@ -13,8 +13,10 @@
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "sched"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/CommandLine.h"
@ -34,11 +36,13 @@ namespace {
MachineBasicBlock *BB;
const TargetMachine &TM;
const TargetInstrInfo &TII;
SSARegMap *RegMap;
std::map<SDNode *, unsigned> EmittedOps;
public:
SimpleSched(SelectionDAG &D, MachineBasicBlock *bb)
: DAG(D), BB(bb), TM(D.getTarget()), TII(*TM.getInstrInfo()) {
: DAG(D), BB(bb), TM(D.getTarget()), TII(*TM.getInstrInfo()),
RegMap(BB->getParent()->getSSARegMap()) {
assert(&TII && "Target doesn't provide instr info?");
}
@ -73,14 +77,14 @@ unsigned SimpleSched::Emit(SDOperand Op) {
// Target nodes have any register or immediate operands before any chain
// nodes. Check that the DAG matches the TD files's expectation of #
// operands.
unsigned NumResults = Op.Val->getNumValues();
if (NumResults && Op.getOperand(NumResults-1).getValueType() == MVT::Other)
--NumResults;
#ifndef _NDEBUG
unsigned Operands = Op.getNumOperands();
if (Operands && Op.getOperand(Operands-1).getValueType() == MVT::Other)
--Operands;
unsigned Results = Op.Val->getNumValues();
if (Results && Op.getOperand(Results-1).getValueType() == MVT::Other)
--Results;
assert(unsigned(II.numOperands) == Operands+Results &&
assert(unsigned(II.numOperands) == Operands+NumResults &&
"#operands for dag node doesn't match .td file!");
#endif
@ -89,9 +93,18 @@ unsigned SimpleSched::Emit(SDOperand Op) {
// Add result register values for things that are defined by this
// instruction.
assert(Op.Val->getNumValues() == 1 &&
Op.getValue(0).getValueType() == MVT::Other &&
"Return values not implemented yet");
if (NumResults) {
// Create the result registers for this node and add the result regs to
// the machine instruction.
const TargetOperandInfo *OpInfo = II.OpInfo;
ResultReg = RegMap->createVirtualRegister(OpInfo[0].RegClass);
MI->addRegOperand(ResultReg, MachineOperand::Def);
for (unsigned i = 1; i != NumResults; ++i) {
assert(OpInfo[i].RegClass && "Isn't a register operand!");
MI->addRegOperand(RegMap->createVirtualRegister(OpInfo[0].RegClass),
MachineOperand::Def);
}
}
// Emit all of the operands of this instruction, adding them to the
// instruction as appropriate.