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Reapplying this patch. With the newest commits, the error in Olden/bisort
has disappeared. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30633 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -34,12 +34,15 @@ namespace {
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struct VISIBILITY_HIDDEN PNE : public MachineFunctionPass {
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bool runOnMachineFunction(MachineFunction &Fn) {
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analyzePHINodes(Fn);
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bool Changed = false;
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// Eliminate PHI instructions by inserting copies into predecessor blocks.
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for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
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Changed |= EliminatePHINodes(Fn, *I);
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VRegPHIUseCount.clear();
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return Changed;
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}
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@ -54,15 +57,26 @@ namespace {
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///
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bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
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void LowerAtomicPHINode(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator AfterPHIsIt,
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DenseMap<unsigned, VirtReg2IndexFunctor> &VUC);
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MachineBasicBlock::iterator AfterPHIsIt);
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/// analyzePHINodes - Gather information about the PHI nodes in
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/// here. In particular, we want to map the number of uses of a virtual
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/// register which is used in a PHI node. We map that to the BB the
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/// vreg is coming from. This is used later to determine when the vreg
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/// is killed in the BB.
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///
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void analyzePHINodes(const MachineFunction& Fn);
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typedef std::pair<const MachineBasicBlock*, unsigned> BBVRegPair;
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typedef std::map<BBVRegPair, unsigned> VRegPHIUse;
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VRegPHIUse VRegPHIUseCount;
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};
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RegisterPass<PNE> X("phi-node-elimination",
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"Eliminate PHI nodes for register allocation");
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}
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const PassInfo *llvm::PHIEliminationID = X.getPassInfo();
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/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
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@ -72,20 +86,6 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
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if (MBB.empty() || MBB.front().getOpcode() != TargetInstrInfo::PHI)
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return false; // Quick exit for basic blocks without PHIs.
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// VRegPHIUseCount - Keep track of the number of times each virtual register
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// is used by PHI nodes in successors of this block.
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DenseMap<unsigned, VirtReg2IndexFunctor> VRegPHIUseCount;
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VRegPHIUseCount.grow(MF.getSSARegMap()->getLastVirtReg());
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for (MachineBasicBlock::pred_iterator PI = MBB.pred_begin(),
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E = MBB.pred_end(); PI != E; ++PI)
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for (MachineBasicBlock::succ_iterator SI = (*PI)->succ_begin(),
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E = (*PI)->succ_end(); SI != E; ++SI)
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for (MachineBasicBlock::iterator BBI = (*SI)->begin(), E = (*SI)->end();
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BBI != E && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
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for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
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VRegPHIUseCount[BBI->getOperand(i).getReg()]++;
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// Get an iterator to the first instruction after the last PHI node (this may
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// also be the end of the basic block).
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MachineBasicBlock::iterator AfterPHIsIt = MBB.begin();
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@ -93,9 +93,9 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
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AfterPHIsIt->getOpcode() == TargetInstrInfo::PHI)
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++AfterPHIsIt; // Skip over all of the PHI nodes...
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while (MBB.front().getOpcode() == TargetInstrInfo::PHI) {
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LowerAtomicPHINode(MBB, AfterPHIsIt, VRegPHIUseCount);
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}
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while (MBB.front().getOpcode() == TargetInstrInfo::PHI)
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LowerAtomicPHINode(MBB, AfterPHIsIt);
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return true;
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}
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@ -115,8 +115,7 @@ static bool InstructionUsesRegister(MachineInstr *MI, unsigned SrcReg) {
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/// atomic execution of PHIs. This lowering method is always correct all of the
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/// time.
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void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator AfterPHIsIt,
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DenseMap<unsigned, VirtReg2IndexFunctor> &VRegPHIUseCount) {
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MachineBasicBlock::iterator AfterPHIsIt) {
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// Unlink the PHI node from the basic block, but don't delete the PHI yet.
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MachineInstr *MPhi = MBB.remove(MBB.begin());
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@ -167,7 +166,9 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
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// node.
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unsigned NumPreds = (MPhi->getNumOperands()-1)/2;
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for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
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VRegPHIUseCount[MPhi->getOperand(i).getReg()] -= NumPreds;
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VRegPHIUseCount[BBVRegPair(
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MPhi->getOperand(i + 1).getMachineBasicBlock(),
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MPhi->getOperand(i).getReg())] -= NumPreds;
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// Now loop over all of the incoming arguments, changing them to copy into
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// the IncomingReg register in the corresponding predecessor basic block.
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@ -219,7 +220,10 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
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//
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// Is it used by any PHI instructions in this block?
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bool ValueIsLive = VRegPHIUseCount[SrcReg] != 0;
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bool ValueIsLive =
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VRegPHIUseCount[BBVRegPair(
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MPhi->getOperand(i).getMachineBasicBlock(),
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SrcReg)] != 0;
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std::vector<MachineBasicBlock*> OpSuccBlocks;
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@ -317,3 +321,19 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
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delete MPhi;
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++NumAtomic;
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}
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/// analyzePHINodes - Gather information about the PHI nodes in here. In
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/// particular, we want to map the number of uses of a virtual register which is
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/// used in a PHI node. We map that to the BB the vreg is coming from. This is
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/// used later to determine when the vreg is killed in the BB.
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///
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void PNE::analyzePHINodes(const MachineFunction& Fn) {
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for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
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I != E; ++I)
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for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
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BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
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for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
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VRegPHIUseCount[BBVRegPair(
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BBI->getOperand(i + 1).getMachineBasicBlock(),
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BBI->getOperand(i).getReg())]++;
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}
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