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Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140370 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2011-09-23 06:57:25 +00:00
parent aaa9fc2e37
commit 4da632e6e0
5 changed files with 23 additions and 13 deletions
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11
test/MC/Disassembler/X86/intel-syntax.txt
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@ -12,14 +12,11 @@
# CHECK: movsq # CHECK: movsq
0x48 0xa5 0x48 0xa5
# CHECK: pop DS # CHECK: pop FS
0x1f 0x0f 0xa1
# CHECK: pop ES # CHECK: pop GS
0x07 0x0f 0xa9
# CHECK: pop SS
0x17
# CHECK: in AL, DX # CHECK: in AL, DX
0xec 0xec

6
utils/TableGen/X86DisassemblerTables.cpp
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@ -642,12 +642,16 @@ void DisassemblerTables::setTableFields(OpcodeType type,
InstructionContext insnContext, InstructionContext insnContext,
uint8_t opcode, uint8_t opcode,
const ModRMFilter &filter, const ModRMFilter &filter,
InstrUID uid) { InstrUID uid,
bool is32bit) {
unsigned index; unsigned index;
ContextDecision &decision = *Tables[type]; ContextDecision &decision = *Tables[type];
for (index = 0; index < IC_max; ++index) { for (index = 0; index < IC_max; ++index) {
if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
continue;
if (inheritsFrom((InstructionContext)index, if (inheritsFrom((InstructionContext)index,
InstructionSpecifiers[uid].insnContext)) InstructionSpecifiers[uid].insnContext))
setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode], setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],

4
utils/TableGen/X86DisassemblerTables.h
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@ -260,11 +260,13 @@ public:
/// @param filter - The ModRMFilter that decides which ModR/M byte values /// @param filter - The ModRMFilter that decides which ModR/M byte values
/// correspond to the desired instruction. /// correspond to the desired instruction.
/// @param uid - The unique ID of the instruction. /// @param uid - The unique ID of the instruction.
/// @param is32bit - Instructon is only 32-bit
void setTableFields(OpcodeType type, void setTableFields(OpcodeType type,
InstructionContext insnContext, InstructionContext insnContext,
uint8_t opcode, uint8_t opcode,
const ModRMFilter &filter, const ModRMFilter &filter,
InstrUID uid); InstrUID uid,
bool is32bit);
/// specForUID - Returns the instruction specifier for a given unique /// specForUID - Returns the instruction specifier for a given unique
/// instruction ID. Used when resolving collisions. /// instruction ID. Used when resolving collisions.

11
utils/TableGen/X86RecognizableInstr.cpp
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@ -231,10 +231,15 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L"); HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
// Check for 64-bit inst which does not require REX // Check for 64-bit inst which does not require REX
Is32Bit = false;
Is64Bit = false; Is64Bit = false;
// FIXME: Is there some better way to check for In64BitMode? // FIXME: Is there some better way to check for In64BitMode?
std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates"); std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
if (Predicates[i]->getName().find("32Bit") != Name.npos) {
Is32Bit = true;
break;
}
if (Predicates[i]->getName().find("64Bit") != Name.npos) { if (Predicates[i]->getName().find("64Bit") != Name.npos) {
Is64Bit = true; Is64Bit = true;
break; break;
@ -947,7 +952,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
insnContext(), insnContext(),
currentOpcode, currentOpcode,
*filter, *filter,
UID); UID, Is32Bit);
Spec->modifierType = MODIFIER_OPCODE; Spec->modifierType = MODIFIER_OPCODE;
Spec->modifierBase = opcodeToSet; Spec->modifierBase = opcodeToSet;
@ -957,14 +962,14 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
insnContext(), insnContext(),
opcodeToSet, opcodeToSet,
*filter, *filter,
UID); UID, Is32Bit);
} }
} else { } else {
tables.setTableFields(opcodeType, tables.setTableFields(opcodeType,
insnContext(), insnContext(),
opcodeToSet, opcodeToSet,
*filter, *filter,
UID); UID, Is32Bit);
Spec->modifierType = MODIFIER_NONE; Spec->modifierType = MODIFIER_NONE;
Spec->modifierBase = opcodeToSet; Spec->modifierBase = opcodeToSet;

4
utils/TableGen/X86RecognizableInstr.h
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@ -64,8 +64,10 @@ private:
bool HasLockPrefix; bool HasLockPrefix;
/// The isCodeGenOnly filed from the record /// The isCodeGenOnly filed from the record
bool IsCodeGenOnly; bool IsCodeGenOnly;
// Whether the instruction has the predicate "Mode64Bit" // Whether the instruction has the predicate "In64BitMode"
bool Is64Bit; bool Is64Bit;
// Whether the instruction has the predicate "In32BitMode"
bool Is32Bit;
/// The instruction name as listed in the tables /// The instruction name as listed in the tables
std::string Name; std::string Name;