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[PowerPC] Eliminate compares - add i32 sext/zext handling for SETLE/SETGE

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Adds handling for SETLE/SETGE comparisons on i32 values. Furthermore, it adds
the handling for the special case where RHS == 0.

Differential Revision: https://reviews.llvm.org/D34048


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310346 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nemanja Ivanovic 2017-08-08 11:20:44 +00:00
parent c6a1f940fd
commit 4db6f31bda
13 changed files with 945 additions and 0 deletions
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126
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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@ -282,6 +282,11 @@ private:
// SExtInvert - invert the condition code, sign-extend value
enum SetccInGPROpts { ZExtOrig, ZExtInvert, SExtOrig, SExtInvert };
// Comparisons against zero to emit GPR code sequences for. Each of these
// sequences may need to be emitted for two or more equivalent patterns.
// For example (a >= 0) == (a > -1).
enum ZeroCompare { GEZExt, GESExt, LEZExt, LESExt };
bool trySETCC(SDNode *N);
bool tryEXTEND(SDNode *N);
bool tryLogicOpOfCompares(SDNode *N);
@ -289,6 +294,8 @@ private:
SDValue signExtendInputIfNeeded(SDValue Input);
SDValue zeroExtendInputIfNeeded(SDValue Input);
SDValue addExtOrTrunc(SDValue NatWidthRes, ExtOrTruncConversion Conv);
SDValue getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl,
ZeroCompare CmpTy);
SDValue get32BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
int64_t RHSValue, SDLoc dl);
SDValue get32BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
@ -2797,6 +2804,71 @@ SDValue PPCDAGToDAGISel::addExtOrTrunc(SDValue NatWidthRes,
NatWidthRes, SubRegIdx), 0);
}
// Produce a GPR sequence for compound comparisons (<=, >=) against zero.
// Handle both zero-extensions and sign-extensions.
SDValue PPCDAGToDAGISel::getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl,
ZeroCompare CmpTy) {
EVT InVT = LHS.getValueType();
bool Is32Bit = InVT == MVT::i32;
SDValue ToExtend;
// Produce the value that needs to be either zero or sign extended.
switch (CmpTy) {
default: llvm_unreachable("Unknown Zero-comparison type.");
case ZeroCompare::GEZExt:
case ZeroCompare::GESExt:
ToExtend = SDValue(CurDAG->getMachineNode(Is32Bit ? PPC::NOR : PPC::NOR8,
dl, InVT, LHS, LHS), 0);
case ZeroCompare::LEZExt:
case ZeroCompare::LESExt: {
if (Is32Bit) {
SDValue Neg =
SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, LHS), 0);
ToExtend =
SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
Neg, getI64Imm(1, dl),
getI64Imm(63, dl)), 0);
} else {
SDValue Addi =
SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS,
getI64Imm(~0ULL, dl)), 0);
ToExtend = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
Addi, LHS), 0);
}
}
}
// For 64-bit sequences, the extensions are the same for the GE/LE cases.
if (!Is32Bit && (CmpTy == ZeroCompare::GEZExt || ZeroCompare::LEZExt))
return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
ToExtend, getI64Imm(1, dl),
getI64Imm(63, dl)), 0);
if (!Is32Bit && (CmpTy == ZeroCompare::GESExt || ZeroCompare::LESExt))
return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, ToExtend,
getI64Imm(63, dl)), 0);
assert(Is32Bit && "Should have handled the 32-bit sequences above.");
// For 32-bit sequences, the extensions differ between GE/LE cases.
switch (CmpTy) {
default: llvm_unreachable("Unknown Zero-comparison type.");
case ZeroCompare::GEZExt: {
SDValue ShiftOps[] =
{ ToExtend, getI32Imm(1, dl), getI32Imm(31, dl), getI32Imm(31, dl) };
return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
ShiftOps), 0);
}
case ZeroCompare::GESExt:
return SDValue(CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, ToExtend,
getI32Imm(31, dl)), 0);
case ZeroCompare::LEZExt:
return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, ToExtend,
getI32Imm(1, dl)), 0);
case ZeroCompare::LESExt:
return SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, ToExtend,
getI32Imm(-1, dl)), 0);
}
}
/// Produces a zero-extended result of comparing two 32-bit values according to
/// the passed condition code.
SDValue PPCDAGToDAGISel::get32BitZExtCompare(SDValue LHS, SDValue RHS,
@ -2831,6 +2903,32 @@ SDValue PPCDAGToDAGISel::get32BitZExtCompare(SDValue LHS, SDValue RHS,
return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
getI32Imm(1, dl)), 0);
}
case ISD::SETGE: {
// (zext (setcc %a, %b, setge)) -> (xor (lshr (sub %a, %b), 63), 1)
// (zext (setcc %a, 0, setge)) -> (lshr (~ %a), 31)
if(IsRHSZero)
return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
// Not a special case (i.e. RHS == 0). Handle (%a >= %b) as (%b <= %a)
// by swapping inputs and falling through.
std::swap(LHS, RHS);
ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
IsRHSZero = RHSConst && RHSConst->isNullValue();
LLVM_FALLTHROUGH;
}
case ISD::SETLE: {
// (zext (setcc %a, %b, setle)) -> (xor (lshr (sub %b, %a), 63), 1)
// (zext (setcc %a, 0, setle)) -> (xor (lshr (- %a), 63), 1)
if(IsRHSZero)
return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
SDValue Sub =
SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, LHS, RHS), 0);
SDValue Shift =
SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32, Sub,
getI64Imm(1, dl), getI64Imm(63, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::XORI, dl,
MVT::i32, Shift, getI32Imm(1, dl)), 0);
}
}
}
@ -2878,6 +2976,34 @@ SDValue PPCDAGToDAGISel::get32BitSExtCompare(SDValue LHS, SDValue RHS,
getI32Imm(1, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Xori), 0);
}
case ISD::SETGE: {
// (sext (setcc %a, %b, setge)) -> (add (lshr (sub %a, %b), 63), -1)
// (sext (setcc %a, 0, setge)) -> (ashr (~ %a), 31)
if (IsRHSZero)
return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
// Not a special case (i.e. RHS == 0). Handle (%a >= %b) as (%b <= %a)
// by swapping inputs and falling through.
std::swap(LHS, RHS);
ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
IsRHSZero = RHSConst && RHSConst->isNullValue();
LLVM_FALLTHROUGH;
}
case ISD::SETLE: {
// (sext (setcc %a, %b, setge)) -> (add (lshr (sub %b, %a), 63), -1)
// (sext (setcc %a, 0, setle)) -> (add (lshr (- %a), 63), -1)
if (IsRHSZero)
return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
SDValue SUBFNode =
SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, MVT::Glue,
LHS, RHS), 0);
SDValue Srdi =
SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
SUBFNode, getI64Imm(1, dl),
getI64Imm(63, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Srdi,
getI32Imm(-1, dl)), 0);
}
}
}

68
test/CodeGen/PowerPC/testComparesigesc.ll Normal file
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@ -0,0 +1,68 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
define signext i32 @test_igesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
define signext i32 @test_igesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_igesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}

68
test/CodeGen/PowerPC/testComparesigesi.ll Normal file
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@ -0,0 +1,68 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define signext i32 @test_igesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_igesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

68
test/CodeGen/PowerPC/testComparesigess.ll Normal file
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@ -0,0 +1,68 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
define signext i32 @test_igess(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
define signext i32 @test_igess_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_igess_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_igess_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}

68
test/CodeGen/PowerPC/testComparesilesc.ll Normal file
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@ -0,0 +1,68 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
define signext i32 @test_ilesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
define signext i32 @test_ilesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_ilesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}

68
test/CodeGen/PowerPC/testComparesilesi.ll Normal file
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@ -0,0 +1,68 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_ilesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

68
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
define signext i32 @test_iless(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
define signext i32 @test_iless_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_iless_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_iless_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}

68
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
define i64 @test_llgesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgesc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_llgesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgesc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
define void @test_llgesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgesc_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgesc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}

68
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define i64 @test_llgesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgesi:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llgesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgesi_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define void @test_llgesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgesi_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgesi_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

68
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
define i64 @test_llgess(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgess:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_llgess_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgess_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
define void @test_llgess_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgess_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgess_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}

69
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
define i64 @test_lllesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lllesc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_lllesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lllesc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
define void @test_lllesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lllesc_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lllesc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}

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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define i64 @test_lllesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lllesi:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_lllesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lllesi_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define void @test_lllesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lllesi_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lllesi_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
define i64 @test_llless(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llless:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_llless_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llless_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
define void @test_llless_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llless_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_llless_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llless_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}