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[PowerPC] Add a DAGToDAG peephole to remove unnecessary zero-exts
On PPC64, we end up with lots of i32 -> i64 zero extensions, not only from all of the usual places, but also from the ABI, which specifies that values passed are zero extended. Almost all 32-bit PPC instructions in PPC64 mode are defined to do *something* to the higher-order bits, and for some instructions, that action clears those bits (thus providing a zero-extended result). This is especially common after rotate-and-mask instructions. Adding an additional instruction to zero-extend the results of these instructions is unnecessary. This PPCISelDAGToDAG peephole optimization examines these zero-extensions, and looks back through their operands to see if all instructions will implicitly zero extend their results. If so, we convert these instructions to their 64-bit variants (which is an internal change only, the actual encoding of these instructions is the same as the original 32-bit ones) and remove the unnecessary zero-extension (changing where the INSERT_SUBREG instructions are to make everything internally consistent). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224169 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
parent
3b7e6d27d2
commit
4e703f82f2
@ -205,6 +205,7 @@ private:
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SDNode *SelectSETCC(SDNode *N);
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void PeepholePPC64();
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void PeepholePPC64ZExt();
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void PeepholeCROps();
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bool AllUsersSelectZero(SDNode *N);
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@ -1628,6 +1629,7 @@ void PPCDAGToDAGISel::PostprocessISelDAG() {
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PeepholePPC64();
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PeepholeCROps();
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PeepholePPC64ZExt();
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}
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// Check if all users of this node will become isel where the second operand
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@ -2101,6 +2103,299 @@ void PPCDAGToDAGISel::PeepholeCROps() {
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} while (IsModified);
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}
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// Gather the set of 32-bit operations that are known to have their
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// higher-order 32 bits zero, where ToPromote contains all such operations.
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static bool PeepholePPC64ZExtGather(SDValue Op32,
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SmallPtrSetImpl<SDNode *> &ToPromote) {
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if (!Op32.isMachineOpcode())
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return false;
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// First, check for the "frontier" instructions (those that will clear the
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// higher-order 32 bits.
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// For RLWINM and RLWNM, we need to make sure that the mask does not wrap
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// around. If it does not, then these instructions will clear the
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// higher-order bits.
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if ((Op32.getMachineOpcode() == PPC::RLWINM ||
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Op32.getMachineOpcode() == PPC::RLWNM) &&
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Op32.getConstantOperandVal(2) <= Op32.getConstantOperandVal(3)) {
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ToPromote.insert(Op32.getNode());
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return true;
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}
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// SLW and SRW always clear the higher-order bits.
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if (Op32.getMachineOpcode() == PPC::SLW ||
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Op32.getMachineOpcode() == PPC::SRW) {
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ToPromote.insert(Op32.getNode());
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return true;
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}
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// For LI and LIS, we need the immediate to be positive (so that it is not
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// sign extended).
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if (Op32.getMachineOpcode() == PPC::LI ||
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Op32.getMachineOpcode() == PPC::LIS) {
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if (!isUInt<15>(Op32.getConstantOperandVal(0)))
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return false;
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ToPromote.insert(Op32.getNode());
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return true;
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}
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// Next, check for those instructions we can look through.
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// Assuming the mask does not wrap around, then the higher-order bits are
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// taken directly from the first operand.
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if (Op32.getMachineOpcode() == PPC::RLWIMI &&
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Op32.getConstantOperandVal(3) <= Op32.getConstantOperandVal(4)) {
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SmallPtrSet<SDNode *, 16> ToPromote1;
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if (!PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1))
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return false;
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ToPromote.insert(Op32.getNode());
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ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
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return true;
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}
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// For OR, the higher-order bits are zero if that is true for both operands.
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// For SELECT_I4, the same is true (but the relevant operand numbers are
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// shifted by 1).
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if (Op32.getMachineOpcode() == PPC::OR ||
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Op32.getMachineOpcode() == PPC::SELECT_I4) {
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unsigned B = Op32.getMachineOpcode() == PPC::SELECT_I4 ? 1 : 0;
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SmallPtrSet<SDNode *, 16> ToPromote1;
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if (!PeepholePPC64ZExtGather(Op32.getOperand(B+0), ToPromote1))
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return false;
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if (!PeepholePPC64ZExtGather(Op32.getOperand(B+1), ToPromote1))
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return false;
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ToPromote.insert(Op32.getNode());
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ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
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return true;
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}
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// For ORI and ORIS, we need the higher-order bits of the first operand to be
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// zero, and also for the constant to be positive (so that it is not sign
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// extended).
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if (Op32.getMachineOpcode() == PPC::ORI ||
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Op32.getMachineOpcode() == PPC::ORIS) {
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SmallPtrSet<SDNode *, 16> ToPromote1;
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if (!PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1))
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return false;
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if (!isUInt<15>(Op32.getConstantOperandVal(1)))
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return false;
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ToPromote.insert(Op32.getNode());
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ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
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return true;
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}
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// The higher-order bits of AND are zero if that is true for at least one of
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// the operands.
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if (Op32.getMachineOpcode() == PPC::AND) {
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SmallPtrSet<SDNode *, 16> ToPromote1, ToPromote2;
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bool Op0OK =
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PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1);
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bool Op1OK =
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PeepholePPC64ZExtGather(Op32.getOperand(1), ToPromote2);
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if (!Op0OK && !Op1OK)
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return false;
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ToPromote.insert(Op32.getNode());
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if (Op0OK)
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ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
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if (Op1OK)
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ToPromote.insert(ToPromote2.begin(), ToPromote2.end());
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return true;
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}
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// For ANDI and ANDIS, the higher-order bits are zero if either that is true
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// of the first operand, or if the second operand is positive (so that it is
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// not sign extended).
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if (Op32.getMachineOpcode() == PPC::ANDIo ||
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Op32.getMachineOpcode() == PPC::ANDISo) {
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SmallPtrSet<SDNode *, 16> ToPromote1;
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bool Op0OK =
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PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1);
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bool Op1OK = isUInt<15>(Op32.getConstantOperandVal(1));
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if (!Op0OK && !Op1OK)
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return false;
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ToPromote.insert(Op32.getNode());
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if (Op0OK)
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ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
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return true;
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}
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return false;
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}
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void PPCDAGToDAGISel::PeepholePPC64ZExt() {
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if (!PPCSubTarget->isPPC64())
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return;
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// When we zero-extend from i32 to i64, we use a pattern like this:
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// def : Pat<(i64 (zext i32:$in)),
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// (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
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// 0, 32)>;
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// There are several 32-bit shift/rotate instructions, however, that will
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// clear the higher-order bits of their output, rendering the RLDICL
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// unnecessary. When that happens, we remove it here, and redefine the
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// relevant 32-bit operation to be a 64-bit operation.
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SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
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++Position;
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bool MadeChange = false;
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while (Position != CurDAG->allnodes_begin()) {
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SDNode *N = --Position;
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// Skip dead nodes and any non-machine opcodes.
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if (N->use_empty() || !N->isMachineOpcode())
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continue;
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if (N->getMachineOpcode() != PPC::RLDICL)
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continue;
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if (N->getConstantOperandVal(1) != 0 ||
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N->getConstantOperandVal(2) != 32)
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continue;
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SDValue ISR = N->getOperand(0);
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if (!ISR.isMachineOpcode() ||
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ISR.getMachineOpcode() != TargetOpcode::INSERT_SUBREG)
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continue;
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if (!ISR.hasOneUse())
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continue;
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if (ISR.getConstantOperandVal(2) != PPC::sub_32)
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continue;
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SDValue IDef = ISR.getOperand(0);
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if (!IDef.isMachineOpcode() ||
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IDef.getMachineOpcode() != TargetOpcode::IMPLICIT_DEF)
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continue;
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// We now know that we're looking at a canonical i32 -> i64 zext. See if we
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// can get rid of it.
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SDValue Op32 = ISR->getOperand(1);
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if (!Op32.isMachineOpcode())
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continue;
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// There are some 32-bit instructions that always clear the high-order 32
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// bits, there are also some instructions (like AND) that we can look
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// through.
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SmallPtrSet<SDNode *, 16> ToPromote;
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if (!PeepholePPC64ZExtGather(Op32, ToPromote))
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continue;
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// If the ToPromote set contains nodes that have uses outside of the set
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// (except for the original INSERT_SUBREG), then abort the transformation.
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bool OutsideUse = false;
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for (SDNode *PN : ToPromote) {
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for (SDNode *UN : PN->uses()) {
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if (!ToPromote.count(UN) && UN != ISR.getNode()) {
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OutsideUse = true;
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break;
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}
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}
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if (OutsideUse)
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break;
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}
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if (OutsideUse)
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continue;
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MadeChange = true;
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// We now know that this zero extension can be removed by promoting to
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// nodes in ToPromote to 64-bit operations, where for operations in the
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// frontier of the set, we need to insert INSERT_SUBREGs for their
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// operands.
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for (SDNode *PN : ToPromote) {
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unsigned NewOpcode;
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switch (PN->getMachineOpcode()) {
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default:
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llvm_unreachable("Don't know the 64-bit variant of this instruction");
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case PPC::RLWINM: NewOpcode = PPC::RLWINM8; break;
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case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break;
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case PPC::SLW: NewOpcode = PPC::SLW8; break;
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case PPC::SRW: NewOpcode = PPC::SRW8; break;
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case PPC::LI: NewOpcode = PPC::LI8; break;
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case PPC::LIS: NewOpcode = PPC::LIS8; break;
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case PPC::RLWIMI: NewOpcode = PPC::RLWIMI8; break;
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case PPC::OR: NewOpcode = PPC::OR8; break;
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case PPC::SELECT_I4: NewOpcode = PPC::SELECT_I8; break;
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case PPC::ORI: NewOpcode = PPC::ORI8; break;
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case PPC::ORIS: NewOpcode = PPC::ORIS8; break;
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case PPC::AND: NewOpcode = PPC::AND8; break;
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case PPC::ANDIo: NewOpcode = PPC::ANDIo8; break;
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case PPC::ANDISo: NewOpcode = PPC::ANDISo8; break;
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}
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// Note: During the replacement process, the nodes will be in an
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// inconsistent state (some instructions will have operands with values
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// of the wrong type). Once done, however, everything should be right
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// again.
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SmallVector<SDValue, 4> Ops;
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for (const SDValue &V : PN->ops()) {
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if (!ToPromote.count(V.getNode()) && V.getValueType() == MVT::i32 &&
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!isa<ConstantSDNode>(V)) {
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SDValue ReplOpOps[] = { ISR.getOperand(0), V, ISR.getOperand(2) };
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SDNode *ReplOp =
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CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, SDLoc(V),
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ISR.getNode()->getVTList(), ReplOpOps);
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Ops.push_back(SDValue(ReplOp, 0));
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} else {
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Ops.push_back(V);
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}
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}
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// Because all to-be-promoted nodes only have users that are other
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// promoted nodes (or the original INSERT_SUBREG), we can safely replace
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// the i32 result value type with i64.
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SmallVector<EVT, 2> NewVTs;
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SDVTList VTs = PN->getVTList();
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for (unsigned i = 0, ie = VTs.NumVTs; i != ie; ++i)
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if (VTs.VTs[i] == MVT::i32)
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NewVTs.push_back(MVT::i64);
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else
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NewVTs.push_back(VTs.VTs[i]);
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DEBUG(dbgs() << "PPC64 ZExt Peephole morphing:\nOld: ");
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DEBUG(PN->dump(CurDAG));
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CurDAG->SelectNodeTo(PN, NewOpcode, CurDAG->getVTList(NewVTs), Ops);
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DEBUG(dbgs() << "\nNew: ");
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DEBUG(PN->dump(CurDAG));
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DEBUG(dbgs() << "\n");
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}
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// Now we replace the original zero extend and its associated INSERT_SUBREG
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// with the value feeding the INSERT_SUBREG (which has now been promoted to
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// return an i64).
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DEBUG(dbgs() << "PPC64 ZExt Peephole replacing:\nOld: ");
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DEBUG(N->dump(CurDAG));
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DEBUG(dbgs() << "\nNew: ");
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DEBUG(Op32.getNode()->dump(CurDAG));
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DEBUG(dbgs() << "\n");
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ReplaceUses(N, Op32.getNode());
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}
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if (MadeChange)
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CurDAG->RemoveDeadNodes();
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}
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void PPCDAGToDAGISel::PeepholePPC64() {
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// These optimizations are currently supported only for 64-bit SVR4.
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if (PPCSubTarget->isDarwin() || !PPCSubTarget->isPPC64())
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@ -547,6 +547,11 @@ defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
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defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
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"extsh", "$rA, $rS", IIC_IntSimple,
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[(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
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defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
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"slw", "$rA, $rS, $rB", IIC_IntGeneral, []>;
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defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
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"srw", "$rA, $rS, $rB", IIC_IntGeneral, []>;
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} // Interpretation64Bit
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// For fast-isel:
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@ -645,7 +650,11 @@ defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
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"rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
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[]>;
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let isCommutable = 1 in {
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defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA),
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(ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME),
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"rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
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[]>;
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// RLWIMI can be commuted if the rotate amount is zero.
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let Interpretation64Bit = 1, isCodeGenOnly = 1 in
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defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA),
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@ -653,7 +662,6 @@ defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA),
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u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
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IIC_IntRotate, []>, PPC970_DGroup_Cracked,
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RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
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}
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let isSelect = 1 in
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def ISEL8 : AForm_4<31, 15,
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@ -230,10 +230,12 @@ PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
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// Normal instructions can be commuted the obvious way.
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if (MI->getOpcode() != PPC::RLWIMI &&
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MI->getOpcode() != PPC::RLWIMIo &&
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MI->getOpcode() != PPC::RLWIMI8 &&
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MI->getOpcode() != PPC::RLWIMI8o)
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MI->getOpcode() != PPC::RLWIMIo)
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return TargetInstrInfo::commuteInstruction(MI, NewMI);
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// Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
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// 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
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// changing the relative order of the mask operands might change what happens
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// to the high-bits of the mask (and, thus, the result).
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// Cannot commute if it has a non-zero rotate count.
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if (MI->getOperand(3).getImm() != 0)
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32
test/CodeGen/PowerPC/rm-zext.ll
Normal file
32
test/CodeGen/PowerPC/rm-zext.ll
Normal file
@ -0,0 +1,32 @@
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; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Function Attrs: nounwind readnone
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define signext i32 @foo(i32 signext %a) #0 {
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entry:
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%mul = mul nsw i32 %a, %a
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%shr2 = lshr i32 %mul, 5
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ret i32 %shr2
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; CHECK-LABEL @foo
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; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32
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; CHECK: blr
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}
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define zeroext i32 @test6(i32 zeroext %x) #0 {
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entry:
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%and = lshr i32 %x, 16
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%shr = and i32 %and, 255
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%and1 = shl i32 %x, 16
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%shl = and i32 %and1, 16711680
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%or = or i32 %shr, %shl
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ret i32 %or
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; CHECK-LABEL @test6
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; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32
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; CHECK: blr
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}
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attributes #0 = { nounwind readnone }
|
||||
|
||||
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Reference in New Issue
Block a user