Don't use a densemap for keeping track of which vregs are already loaded, just

use a simple vector.  This speeds up -spiller=simple from taking 22s to taking
.1s on povray (debug build).  This change does not modify the generated code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16607 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-09-30 02:33:48 +00:00
parent 7f690e6258
commit 4ea1b828eb

View File

@ -133,14 +133,17 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction& MF,
const TargetMachine& TM = MF.getTarget();
const MRegisterInfo& MRI = *TM.getRegisterInfo();
DenseMap<bool, VirtReg2IndexFunctor> Loaded;
// LoadedRegs - Keep track of which vregs are loaded, so that we only load
// each vreg once (in the case where a spilled vreg is used by multiple
// operands). This is always smaller than the number of operands to the
// current machine instr, so it should be small.
std::vector<unsigned> LoadedRegs;
for (MachineFunction::iterator mbbi = MF.begin(), E = MF.end();
mbbi != E; ++mbbi) {
DEBUG(std::cerr << mbbi->getBasicBlock()->getName() << ":\n");
for (MachineBasicBlock::iterator mii = mbbi->begin(),
mie = mbbi->end(); mii != mie; ++mii) {
Loaded.grow(MF.getSSARegMap()->getLastVirtReg());
for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
MachineOperand& mop = mii->getOperand(i);
if (mop.isRegister() && mop.getReg() &&
@ -148,10 +151,11 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction& MF,
unsigned virtReg = mop.getReg();
unsigned physReg = VRM.getPhys(virtReg);
if (mop.isUse() && VRM.hasStackSlot(mop.getReg()) &&
!Loaded[virtReg]) {
std::find(LoadedRegs.begin(), LoadedRegs.end(),
virtReg) == LoadedRegs.end()) {
MRI.loadRegFromStackSlot(*mbbi, mii, physReg,
VRM.getStackSlot(virtReg));
Loaded[virtReg] = true;
LoadedRegs.push_back(virtReg);
DEBUG(std::cerr << '\t';
prior(mii)->print(std::cerr, &TM));
++NumLoads;
@ -166,7 +170,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction& MF,
}
}
DEBUG(std::cerr << '\t'; mii->print(std::cerr, &TM));
Loaded.clear();
LoadedRegs.clear();
}
}
return true;