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Mess around with allocation order. In particular, I think we ought to be

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using the local & in regs first because they are not clobbered by calls.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14228 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brian Gaeke 2004-06-18 08:19:08 +00:00
parent fbaae01269
commit 4f217fdd10
2 changed files with 6 additions and 6 deletions
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6
lib/Target/Sparc/SparcRegisterInfo.td
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@ -69,10 +69,10 @@ let Namespace = "V8" in {
// FIXME: the register order should be defined in terms of the preferred
// allocation order...
//
def IntRegs : RegisterClass<i32, 8, [G1, G2, G3, G4, G5, G6, G7,
O0, O1, O2, O3, O4, O5, O7,
L0, L1, L2, L3, L4, L5, L6, L7,
def IntRegs : RegisterClass<i32, 8, [L0, L1, L2, L3, L4, L5, L6, L7,
I0, I1, I2, I3, I4, I5,
G1, G2, G3, G4, G5, G6, G7,
O0, O1, O2, O3, O4, O5, O7,
// Non-allocatable regs
O6, I6, I7, G0]> {
let Methods = [{

6
lib/Target/SparcV8/SparcV8RegisterInfo.td
View File

@ -69,10 +69,10 @@ let Namespace = "V8" in {
// FIXME: the register order should be defined in terms of the preferred
// allocation order...
//
def IntRegs : RegisterClass<i32, 8, [G1, G2, G3, G4, G5, G6, G7,
O0, O1, O2, O3, O4, O5, O7,
L0, L1, L2, L3, L4, L5, L6, L7,
def IntRegs : RegisterClass<i32, 8, [L0, L1, L2, L3, L4, L5, L6, L7,
I0, I1, I2, I3, I4, I5,
G1, G2, G3, G4, G5, G6, G7,
O0, O1, O2, O3, O4, O5, O7,
// Non-allocatable regs
O6, I6, I7, G0]> {
let Methods = [{