From 4f2256187cf518356475d6846198e5d8c004e076 Mon Sep 17 00:00:00 2001
From: Hao Liu <Hao.Liu@arm.com>
Date: Thu, 13 Feb 2014 02:36:58 +0000
Subject: [PATCH] [AArch64]Add support for spilling FPR8/FPR16.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201287 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/AArch64/AArch64InstrInfo.cpp       |  8 +++++
 test/CodeGen/AArch64/neon-spill-fpr8-fpr16.ll | 30 +++++++++++++++++++
 2 files changed, 38 insertions(+)
 create mode 100644 test/CodeGen/AArch64/neon-spill-fpr8-fpr16.ll

diff --git a/lib/Target/AArch64/AArch64InstrInfo.cpp b/lib/Target/AArch64/AArch64InstrInfo.cpp
index 9c27f82d2b3..092af05e199 100644
--- a/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -487,6 +487,10 @@ AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
     default:
       llvm_unreachable("Unknown size for regclass");
     }
+  } else if (AArch64::FPR8RegClass.hasSubClassEq(RC)) {
+    StoreOp = AArch64::LSFP8_STR;
+  } else if (AArch64::FPR16RegClass.hasSubClassEq(RC)) {
+    StoreOp = AArch64::LSFP16_STR;
   } else if (RC->hasType(MVT::f32) || RC->hasType(MVT::f64) ||
              RC->hasType(MVT::f128)) {
     switch (RC->getSize()) {
@@ -553,6 +557,10 @@ AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
     default:
       llvm_unreachable("Unknown size for regclass");
     }
+  } else if (AArch64::FPR8RegClass.hasSubClassEq(RC)) {
+    LoadOp = AArch64::LSFP8_LDR;
+  } else if (AArch64::FPR16RegClass.hasSubClassEq(RC)) {
+    LoadOp = AArch64::LSFP16_LDR;
   } else if (RC->hasType(MVT::f32) || RC->hasType(MVT::f64) ||
              RC->hasType(MVT::f128)) {
     switch (RC->getSize()) {
diff --git a/test/CodeGen/AArch64/neon-spill-fpr8-fpr16.ll b/test/CodeGen/AArch64/neon-spill-fpr8-fpr16.ll
new file mode 100644
index 00000000000..bb3300ee9a9
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-spill-fpr8-fpr16.ll
@@ -0,0 +1,30 @@
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
+
+; This file tests the spill of FPR8/FPR16. The volatile loads/stores force the
+; allocator to keep the value live until it's needed.
+
+%bigtype_v1i8 = type [20 x <1 x i8>]
+
+define void @spill_fpr8(%bigtype_v1i8* %addr) {
+; CHECK-LABEL: spill_fpr8:
+; CHECK: 1-byte Folded Spill
+; CHECK: 1-byte Folded Reload
+  %val1 = load volatile %bigtype_v1i8* %addr
+  %val2 = load volatile %bigtype_v1i8* %addr
+  store volatile %bigtype_v1i8 %val1, %bigtype_v1i8* %addr
+  store volatile %bigtype_v1i8 %val2, %bigtype_v1i8* %addr
+  ret void
+}
+
+%bigtype_v1i16 = type [20 x <1 x i16>]
+
+define void @spill_fpr16(%bigtype_v1i16* %addr) {
+; CHECK-LABEL: spill_fpr16:
+; CHECK: 2-byte Folded Spill
+; CHECK: 2-byte Folded Reload
+  %val1 = load volatile %bigtype_v1i16* %addr
+  %val2 = load volatile %bigtype_v1i16* %addr
+  store volatile %bigtype_v1i16 %val1, %bigtype_v1i16* %addr
+  store volatile %bigtype_v1i16 %val2, %bigtype_v1i16* %addr
+  ret void
+}
\ No newline at end of file