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Fix X86RegisterInfo::getMatchingSuperRegClass for sub_8bit_hi.
It is OK for B to be any GR8_ABCD_H superclass, the returned register class doesn't have to map surjectively onto B. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130892 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -229,19 +229,14 @@ X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
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}
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break;
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case X86::sub_8bit_hi:
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if (B == &X86::GR8_ABCD_HRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
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A == &X86::GR64_NOREXRegClass ||
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A == &X86::GR64_NOSPRegClass ||
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A == &X86::GR64_NOREX_NOSPRegClass)
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return &X86::GR64_ABCDRegClass;
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else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
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A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
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return &X86::GR32_ABCDRegClass;
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else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
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A == &X86::GR16_NOREXRegClass)
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return &X86::GR16_ABCDRegClass;
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}
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if (B == &X86::GR8_ABCD_HRegClass ||
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B->hasSubClass(&X86::GR8_ABCD_HRegClass))
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switch (A->getSize()) {
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case 2: return getCommonSubClass(A, &X86::GR16_ABCDRegClass);
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case 4: return getCommonSubClass(A, &X86::GR32_ABCDRegClass);
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case 8: return getCommonSubClass(A, &X86::GR64_ABCDRegClass);
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default: return 0;
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}
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break;
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case X86::sub_16bit:
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if (B == &X86::GR16RegClass) {
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