RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-12-30 08:24:12 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[x86][AVX512] add Multiply High Op

Browse Source 
include encoding and intrinsics tests.

review
http://reviews.llvm.org/D10896

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241406 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Asaf Badouh 2015-07-05 12:23:20 +00:00
parent bb803fd76e
commit 5047893c31
8 changed files with 327 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
include/llvm/IR/IntrinsicsX86.td
View File

@ -4466,6 +4466,24 @@ let TargetPrefix = "x86" in {
def int_x86_avx512_mask_pmull_q_512 : GCCBuiltin<"__builtin_ia32_pmullq512_mask">,
Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, llvm_v8i64_ty,
llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx512_mask_pmulhu_w_512 : GCCBuiltin<"__builtin_ia32_pmulhuw512_mask">,
Intrinsic<[llvm_v32i16_ty], [llvm_v32i16_ty, llvm_v32i16_ty,
llvm_v32i16_ty, llvm_i32_ty], [IntrNoMem]>;
def int_x86_avx512_mask_pmulh_w_512 : GCCBuiltin<"__builtin_ia32_pmulhw512_mask">,
Intrinsic<[llvm_v32i16_ty], [llvm_v32i16_ty, llvm_v32i16_ty,
llvm_v32i16_ty, llvm_i32_ty], [IntrNoMem]>;
def int_x86_avx512_mask_pmulhu_w_128 : GCCBuiltin<"__builtin_ia32_pmulhuw128_mask">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty,
llvm_v8i16_ty, llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx512_mask_pmulhu_w_256 : GCCBuiltin<"__builtin_ia32_pmulhuw256_mask">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty, llvm_v16i16_ty,
llvm_v16i16_ty, llvm_i16_ty], [IntrNoMem]>;
def int_x86_avx512_mask_pmulh_w_128 : GCCBuiltin<"__builtin_ia32_pmulhw128_mask">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty,
llvm_v8i16_ty, llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx512_mask_pmulh_w_256 : GCCBuiltin<"__builtin_ia32_pmulhw256_mask">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty, llvm_v16i16_ty,
llvm_v16i16_ty, llvm_i16_ty], [IntrNoMem]>;
def int_x86_avx512_mask_pavg_b_512 : GCCBuiltin<"__builtin_ia32_pavgb512_mask">,
Intrinsic<[llvm_v64i8_ty], [llvm_v64i8_ty, llvm_v64i8_ty,
llvm_v64i8_ty, llvm_i64_ty], [IntrNoMem]>;

2
lib/Target/X86/X86ISelLowering.cpp
View File

@ -1473,6 +1473,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::SUB, MVT::v32i16, Legal);
setOperationAction(ISD::SUB, MVT::v64i8, Legal);
setOperationAction(ISD::MUL, MVT::v32i16, Legal);
setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);

4
lib/Target/X86/X86InstrAVX512.td
View File

@ -3136,6 +3136,10 @@ defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
SSE_INTALU_ITINS_P, HasBWI, 1>;
defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulh", mulhs, SSE_INTALU_ITINS_P,
HasBWI, 1>;
defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhu", mulhu, SSE_INTMUL_ITINS_P,
HasBWI, 1>;
defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg,
SSE_INTALU_ITINS_P, HasBWI, 1>;

6
lib/Target/X86/X86IntrinsicsInfo.h
View File

@ -650,6 +650,12 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
X86ISD::PMULDQ, 0),
X86_INTRINSIC_DATA(avx512_mask_pmul_dq_512, INTR_TYPE_2OP_MASK,
X86ISD::PMULDQ, 0),
X86_INTRINSIC_DATA(avx512_mask_pmulh_w_128, INTR_TYPE_2OP_MASK, ISD::MULHS, 0),
X86_INTRINSIC_DATA(avx512_mask_pmulh_w_256, INTR_TYPE_2OP_MASK, ISD::MULHS, 0),
X86_INTRINSIC_DATA(avx512_mask_pmulh_w_512, INTR_TYPE_2OP_MASK, ISD::MULHS, 0),
X86_INTRINSIC_DATA(avx512_mask_pmulhu_w_128, INTR_TYPE_2OP_MASK, ISD::MULHU, 0),
X86_INTRINSIC_DATA(avx512_mask_pmulhu_w_256, INTR_TYPE_2OP_MASK, ISD::MULHU, 0),
X86_INTRINSIC_DATA(avx512_mask_pmulhu_w_512, INTR_TYPE_2OP_MASK, ISD::MULHU, 0),
X86_INTRINSIC_DATA(avx512_mask_pmull_d_128, INTR_TYPE_2OP_MASK, ISD::MUL, 0),
X86_INTRINSIC_DATA(avx512_mask_pmull_d_256, INTR_TYPE_2OP_MASK, ISD::MUL, 0),
X86_INTRINSIC_DATA(avx512_mask_pmull_d_512, INTR_TYPE_2OP_MASK, ISD::MUL, 0),

27
test/CodeGen/X86/avx512bw-intrinsics.ll
View File

@ -997,3 +997,30 @@ define <64 x i8>@test_int_x86_avx512_mask_pabs_b_512(<64 x i8> %x0, <64 x i8> %x
ret <64 x i8> %res2
}
declare <32 x i16> @llvm.x86.avx512.mask.pmulhu.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)
; CHECK-LABEL: @test_int_x86_avx512_mask_pmulhu_w_512
; CHECK-NOT: call
; CHECK: kmov
; CHECK: {%k1}
; CHECK: vpmulhuw {{.*}}encoding: [0x62
define <32 x i16>@test_int_x86_avx512_mask_pmulhu_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {
%res = call <32 x i16> @llvm.x86.avx512.mask.pmulhu.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)
%res1 = call <32 x i16> @llvm.x86.avx512.mask.pmulhu.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)
%res2 = add <32 x i16> %res, %res1
ret <32 x i16> %res2
}
declare <32 x i16> @llvm.x86.avx512.mask.pmulh.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)
; CHECK-LABEL: @test_int_x86_avx512_mask_pmulh_w_512
; CHECK-NOT: call
; CHECK: kmov
; CHECK: {%k1}
; CHECK: vpmulhw {{.*}}encoding: [0x62
define <32 x i16>@test_int_x86_avx512_mask_pmulh_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {
%res = call <32 x i16> @llvm.x86.avx512.mask.pmulh.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)
%res1 = call <32 x i16> @llvm.x86.avx512.mask.pmulh.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)
%res2 = add <32 x i16> %res, %res1
ret <32 x i16> %res2
}

54
test/CodeGen/X86/avx512bwvl-intrinsics.ll
View File

@ -3763,3 +3763,57 @@ define <16 x i16>@test_int_x86_avx512_mask_pabs_w_256(<16 x i16> %x0, <16 x i16>
ret <16 x i16> %res2
}
declare <8 x i16> @llvm.x86.avx512.mask.pmulhu.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)
; CHECK-LABEL: @test_int_x86_avx512_mask_pmulhu_w_128
; CHECK-NOT: call
; CHECK: kmov
; CHECK: {%k1}
; CHECK: vpmulhuw {{.*}}encoding: [0x62
define <8 x i16>@test_int_x86_avx512_mask_pmulhu_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {
%res = call <8 x i16> @llvm.x86.avx512.mask.pmulhu.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3)
%res1 = call <8 x i16> @llvm.x86.avx512.mask.pmulhu.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1)
%res2 = add <8 x i16> %res, %res1
ret <8 x i16> %res2
}
declare <16 x i16> @llvm.x86.avx512.mask.pmulhu.w.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)
; CHECK-LABEL: @test_int_x86_avx512_mask_pmulhu_w_256
; CHECK-NOT: call
; CHECK: kmov
; CHECK: {%k1}
; CHECK: vpmulhuw {{.*}}encoding: [0x62
define <16 x i16>@test_int_x86_avx512_mask_pmulhu_w_256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %x3) {
%res = call <16 x i16> @llvm.x86.avx512.mask.pmulhu.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %x3)
%res1 = call <16 x i16> @llvm.x86.avx512.mask.pmulhu.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 -1)
%res2 = add <16 x i16> %res, %res1
ret <16 x i16> %res2
}
declare <8 x i16> @llvm.x86.avx512.mask.pmulh.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)
; CHECK-LABEL: @test_int_x86_avx512_mask_pmulh_w_128
; CHECK-NOT: call
; CHECK: kmov
; CHECK: {%k1}
; CHECK: vpmulhw {{.*}}encoding: [0x62
define <8 x i16>@test_int_x86_avx512_mask_pmulh_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {
%res = call <8 x i16> @llvm.x86.avx512.mask.pmulh.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3)
%res1 = call <8 x i16> @llvm.x86.avx512.mask.pmulh.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1)
%res2 = add <8 x i16> %res, %res1
ret <8 x i16> %res2
}
declare <16 x i16> @llvm.x86.avx512.mask.pmulh.w.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)
; CHECK-LABEL: @test_int_x86_avx512_mask_pmulh_w_256
; CHECK-NOT: call
; CHECK: kmov
; CHECK: {%k1}
; CHECK: vpmulhw {{.*}}encoding: [0x62
define <16 x i16>@test_int_x86_avx512_mask_pmulh_w_256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %x3) {
%res = call <16 x i16> @llvm.x86.avx512.mask.pmulh.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %x3)
%res1 = call <16 x i16> @llvm.x86.avx512.mask.pmulh.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 -1)
%res2 = add <16 x i16> %res, %res1
ret <16 x i16> %res2
}

73
test/MC/X86/x86-64-avx512bw.s
View File

@ -3667,3 +3667,76 @@
// CHECK: vpabsw -8256(%rdx), %zmm30
// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x1d,0xb2,0xc0,0xdf,0xff,0xff]
vpabsw -8256(%rdx), %zmm30
// CHECK: vpmulhuw %zmm21, %zmm24, %zmm21
// CHECK: encoding: [0x62,0xa1,0x3d,0x40,0xe4,0xed]
vpmulhuw %zmm21, %zmm24, %zmm21
// CHECK: vpmulhuw %zmm21, %zmm24, %zmm21 {%k3}
// CHECK: encoding: [0x62,0xa1,0x3d,0x43,0xe4,0xed]
vpmulhuw %zmm21, %zmm24, %zmm21 {%k3}
// CHECK: vpmulhuw %zmm21, %zmm24, %zmm21 {%k3} {z}
// CHECK: encoding: [0x62,0xa1,0x3d,0xc3,0xe4,0xed]
vpmulhuw %zmm21, %zmm24, %zmm21 {%k3} {z}
// CHECK: vpmulhuw (%rcx), %zmm24, %zmm21
// CHECK: encoding: [0x62,0xe1,0x3d,0x40,0xe4,0x29]
vpmulhuw (%rcx), %zmm24, %zmm21
// CHECK: vpmulhuw 291(%rax,%r14,8), %zmm24, %zmm21
// CHECK: encoding: [0x62,0xa1,0x3d,0x40,0xe4,0xac,0xf0,0x23,0x01,0x00,0x00]
vpmulhuw 291(%rax,%r14,8), %zmm24, %zmm21
// CHECK: vpmulhuw 8128(%rdx), %zmm24, %zmm21
// CHECK: encoding: [0x62,0xe1,0x3d,0x40,0xe4,0x6a,0x7f]
vpmulhuw 8128(%rdx), %zmm24, %zmm21
// CHECK: vpmulhuw 8192(%rdx), %zmm24, %zmm21
// CHECK: encoding: [0x62,0xe1,0x3d,0x40,0xe4,0xaa,0x00,0x20,0x00,0x00]
vpmulhuw 8192(%rdx), %zmm24, %zmm21
// CHECK: vpmulhuw -8192(%rdx), %zmm24, %zmm21
// CHECK: encoding: [0x62,0xe1,0x3d,0x40,0xe4,0x6a,0x80]
vpmulhuw -8192(%rdx), %zmm24, %zmm21
// CHECK: vpmulhuw -8256(%rdx), %zmm24, %zmm21
// CHECK: encoding: [0x62,0xe1,0x3d,0x40,0xe4,0xaa,0xc0,0xdf,0xff,0xff]
vpmulhuw -8256(%rdx), %zmm24, %zmm21
// CHECK: vpmulhw %zmm27, %zmm26, %zmm30
// CHECK: encoding: [0x62,0x01,0x2d,0x40,0xe5,0xf3]
vpmulhw %zmm27, %zmm26, %zmm30
// CHECK: vpmulhw %zmm27, %zmm26, %zmm30 {%k6}
// CHECK: encoding: [0x62,0x01,0x2d,0x46,0xe5,0xf3]
vpmulhw %zmm27, %zmm26, %zmm30 {%k6}
// CHECK: vpmulhw %zmm27, %zmm26, %zmm30 {%k6} {z}
// CHECK: encoding: [0x62,0x01,0x2d,0xc6,0xe5,0xf3]
vpmulhw %zmm27, %zmm26, %zmm30 {%k6} {z}
// CHECK: vpmulhw (%rcx), %zmm26, %zmm30
// CHECK: encoding: [0x62,0x61,0x2d,0x40,0xe5,0x31]
vpmulhw (%rcx), %zmm26, %zmm30
// CHECK: vpmulhw 291(%rax,%r14,8), %zmm26, %zmm30
// CHECK: encoding: [0x62,0x21,0x2d,0x40,0xe5,0xb4,0xf0,0x23,0x01,0x00,0x00]
vpmulhw 291(%rax,%r14,8), %zmm26, %zmm30
// CHECK: vpmulhw 8128(%rdx), %zmm26, %zmm30
// CHECK: encoding: [0x62,0x61,0x2d,0x40,0xe5,0x72,0x7f]
vpmulhw 8128(%rdx), %zmm26, %zmm30
// CHECK: vpmulhw 8192(%rdx), %zmm26, %zmm30
// CHECK: encoding: [0x62,0x61,0x2d,0x40,0xe5,0xb2,0x00,0x20,0x00,0x00]
vpmulhw 8192(%rdx), %zmm26, %zmm30
// CHECK: vpmulhw -8192(%rdx), %zmm26, %zmm30
// CHECK: encoding: [0x62,0x61,0x2d,0x40,0xe5,0x72,0x80]
vpmulhw -8192(%rdx), %zmm26, %zmm30
// CHECK: vpmulhw -8256(%rdx), %zmm26, %zmm30
// CHECK: encoding: [0x62,0x61,0x2d,0x40,0xe5,0xb2,0xc0,0xdf,0xff,0xff]
vpmulhw -8256(%rdx), %zmm26, %zmm30

143
test/MC/X86/x86-64-avx512bw_vl.s
View File

@ -6583,3 +6583,146 @@
// CHECK: encoding: [0x62,0xe2,0x6d,0x20,0x00,0x9a,0xe0,0xef,0xff,0xff]
vpshufb -4128(%rdx), %ymm18, %ymm19
// CHECK: vpmulhuw %xmm18, %xmm21, %xmm24
// CHECK: encoding: [0x62,0x21,0x55,0x00,0xe4,0xc2]
vpmulhuw %xmm18, %xmm21, %xmm24
// CHECK: vpmulhuw %xmm18, %xmm21, %xmm24 {%k3}
// CHECK: encoding: [0x62,0x21,0x55,0x03,0xe4,0xc2]
vpmulhuw %xmm18, %xmm21, %xmm24 {%k3}
// CHECK: vpmulhuw %xmm18, %xmm21, %xmm24 {%k3} {z}
// CHECK: encoding: [0x62,0x21,0x55,0x83,0xe4,0xc2]
vpmulhuw %xmm18, %xmm21, %xmm24 {%k3} {z}
// CHECK: vpmulhuw (%rcx), %xmm21, %xmm24
// CHECK: encoding: [0x62,0x61,0x55,0x00,0xe4,0x01]
vpmulhuw (%rcx), %xmm21, %xmm24
// CHECK: vpmulhuw 291(%rax,%r14,8), %xmm21, %xmm24
// CHECK: encoding: [0x62,0x21,0x55,0x00,0xe4,0x84,0xf0,0x23,0x01,0x00,0x00]
vpmulhuw 291(%rax,%r14,8), %xmm21, %xmm24
// CHECK: vpmulhuw 2032(%rdx), %xmm21, %xmm24
// CHECK: encoding: [0x62,0x61,0x55,0x00,0xe4,0x42,0x7f]
vpmulhuw 2032(%rdx), %xmm21, %xmm24
// CHECK: vpmulhuw 2048(%rdx), %xmm21, %xmm24
// CHECK: encoding: [0x62,0x61,0x55,0x00,0xe4,0x82,0x00,0x08,0x00,0x00]
vpmulhuw 2048(%rdx), %xmm21, %xmm24
// CHECK: vpmulhuw -2048(%rdx), %xmm21, %xmm24
// CHECK: encoding: [0x62,0x61,0x55,0x00,0xe4,0x42,0x80]
vpmulhuw -2048(%rdx), %xmm21, %xmm24
// CHECK: vpmulhuw -2064(%rdx), %xmm21, %xmm24
// CHECK: encoding: [0x62,0x61,0x55,0x00,0xe4,0x82,0xf0,0xf7,0xff,0xff]
vpmulhuw -2064(%rdx), %xmm21, %xmm24
// CHECK: vpmulhuw %ymm19, %ymm28, %ymm19
// CHECK: encoding: [0x62,0xa1,0x1d,0x20,0xe4,0xdb]
vpmulhuw %ymm19, %ymm28, %ymm19
// CHECK: vpmulhuw %ymm19, %ymm28, %ymm19 {%k2}
// CHECK: encoding: [0x62,0xa1,0x1d,0x22,0xe4,0xdb]
vpmulhuw %ymm19, %ymm28, %ymm19 {%k2}
// CHECK: vpmulhuw %ymm19, %ymm28, %ymm19 {%k2} {z}
// CHECK: encoding: [0x62,0xa1,0x1d,0xa2,0xe4,0xdb]
vpmulhuw %ymm19, %ymm28, %ymm19 {%k2} {z}
// CHECK: vpmulhuw (%rcx), %ymm28, %ymm19
// CHECK: encoding: [0x62,0xe1,0x1d,0x20,0xe4,0x19]
vpmulhuw (%rcx), %ymm28, %ymm19
// CHECK: vpmulhuw 291(%rax,%r14,8), %ymm28, %ymm19
// CHECK: encoding: [0x62,0xa1,0x1d,0x20,0xe4,0x9c,0xf0,0x23,0x01,0x00,0x00]
vpmulhuw 291(%rax,%r14,8), %ymm28, %ymm19
// CHECK: vpmulhuw 4064(%rdx), %ymm28, %ymm19
// CHECK: encoding: [0x62,0xe1,0x1d,0x20,0xe4,0x5a,0x7f]
vpmulhuw 4064(%rdx), %ymm28, %ymm19
// CHECK: vpmulhuw 4096(%rdx), %ymm28, %ymm19
// CHECK: encoding: [0x62,0xe1,0x1d,0x20,0xe4,0x9a,0x00,0x10,0x00,0x00]
vpmulhuw 4096(%rdx), %ymm28, %ymm19
// CHECK: vpmulhuw -4096(%rdx), %ymm28, %ymm19
// CHECK: encoding: [0x62,0xe1,0x1d,0x20,0xe4,0x5a,0x80]
vpmulhuw -4096(%rdx), %ymm28, %ymm19
// CHECK: vpmulhuw -4128(%rdx), %ymm28, %ymm19
// CHECK: encoding: [0x62,0xe1,0x1d,0x20,0xe4,0x9a,0xe0,0xef,0xff,0xff]
vpmulhuw -4128(%rdx), %ymm28, %ymm19
// CHECK: vpmulhw %xmm25, %xmm20, %xmm22
// CHECK: encoding: [0x62,0x81,0x5d,0x00,0xe5,0xf1]
vpmulhw %xmm25, %xmm20, %xmm22
// CHECK: vpmulhw %xmm25, %xmm20, %xmm22 {%k2}
// CHECK: encoding: [0x62,0x81,0x5d,0x02,0xe5,0xf1]
vpmulhw %xmm25, %xmm20, %xmm22 {%k2}
// CHECK: vpmulhw %xmm25, %xmm20, %xmm22 {%k2} {z}
// CHECK: encoding: [0x62,0x81,0x5d,0x82,0xe5,0xf1]
vpmulhw %xmm25, %xmm20, %xmm22 {%k2} {z}
// CHECK: vpmulhw (%rcx), %xmm20, %xmm22
// CHECK: encoding: [0x62,0xe1,0x5d,0x00,0xe5,0x31]
vpmulhw (%rcx), %xmm20, %xmm22
// CHECK: vpmulhw 291(%rax,%r14,8), %xmm20, %xmm22
// CHECK: encoding: [0x62,0xa1,0x5d,0x00,0xe5,0xb4,0xf0,0x23,0x01,0x00,0x00]
vpmulhw 291(%rax,%r14,8), %xmm20, %xmm22
// CHECK: vpmulhw 2032(%rdx), %xmm20, %xmm22
// CHECK: encoding: [0x62,0xe1,0x5d,0x00,0xe5,0x72,0x7f]
vpmulhw 2032(%rdx), %xmm20, %xmm22
// CHECK: vpmulhw 2048(%rdx), %xmm20, %xmm22
// CHECK: encoding: [0x62,0xe1,0x5d,0x00,0xe5,0xb2,0x00,0x08,0x00,0x00]
vpmulhw 2048(%rdx), %xmm20, %xmm22
// CHECK: vpmulhw -2048(%rdx), %xmm20, %xmm22
// CHECK: encoding: [0x62,0xe1,0x5d,0x00,0xe5,0x72,0x80]
vpmulhw -2048(%rdx), %xmm20, %xmm22
// CHECK: vpmulhw -2064(%rdx), %xmm20, %xmm22
// CHECK: encoding: [0x62,0xe1,0x5d,0x00,0xe5,0xb2,0xf0,0xf7,0xff,0xff]
vpmulhw -2064(%rdx), %xmm20, %xmm22
// CHECK: vpmulhw %ymm24, %ymm27, %ymm22
// CHECK: encoding: [0x62,0x81,0x25,0x20,0xe5,0xf0]
vpmulhw %ymm24, %ymm27, %ymm22
// CHECK: vpmulhw %ymm24, %ymm27, %ymm22 {%k1}
// CHECK: encoding: [0x62,0x81,0x25,0x21,0xe5,0xf0]
vpmulhw %ymm24, %ymm27, %ymm22 {%k1}
// CHECK: vpmulhw %ymm24, %ymm27, %ymm22 {%k1} {z}
// CHECK: encoding: [0x62,0x81,0x25,0xa1,0xe5,0xf0]
vpmulhw %ymm24, %ymm27, %ymm22 {%k1} {z}
// CHECK: vpmulhw (%rcx), %ymm27, %ymm22
// CHECK: encoding: [0x62,0xe1,0x25,0x20,0xe5,0x31]
vpmulhw (%rcx), %ymm27, %ymm22
// CHECK: vpmulhw 291(%rax,%r14,8), %ymm27, %ymm22
// CHECK: encoding: [0x62,0xa1,0x25,0x20,0xe5,0xb4,0xf0,0x23,0x01,0x00,0x00]
vpmulhw 291(%rax,%r14,8), %ymm27, %ymm22
// CHECK: vpmulhw 4064(%rdx), %ymm27, %ymm22
// CHECK: encoding: [0x62,0xe1,0x25,0x20,0xe5,0x72,0x7f]
vpmulhw 4064(%rdx), %ymm27, %ymm22
// CHECK: vpmulhw 4096(%rdx), %ymm27, %ymm22
// CHECK: encoding: [0x62,0xe1,0x25,0x20,0xe5,0xb2,0x00,0x10,0x00,0x00]
vpmulhw 4096(%rdx), %ymm27, %ymm22
// CHECK: vpmulhw -4096(%rdx), %ymm27, %ymm22
// CHECK: encoding: [0x62,0xe1,0x25,0x20,0xe5,0x72,0x80]
vpmulhw -4096(%rdx), %ymm27, %ymm22
// CHECK: vpmulhw -4128(%rdx), %ymm27, %ymm22
// CHECK: encoding: [0x62,0xe1,0x25,0x20,0xe5,0xb2,0xe0,0xef,0xff,0xff]
vpmulhw -4128(%rdx), %ymm27, %ymm22