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Initial support for some Thumb2 instructions.
Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73622 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
e3a6165423
commit
52237119a9
@ -52,8 +52,13 @@ public:
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virtual const char *getPassName() const {
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return "ARM Instruction Selection";
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}
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}
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/// getI32Imm - Return a target constant with the specified value, of type i32.
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inline SDValue getI32Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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SDNode *Select(SDValue Op);
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virtual void InstructionSelect();
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bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
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@ -84,6 +89,9 @@ public:
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bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
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SDValue &OffImm);
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bool SelectShifterOperand(SDValue Op, SDValue N,
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SDValue &BaseReg, SDValue &Opc);
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bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
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SDValue &B, SDValue &C);
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@ -509,8 +517,30 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
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return false;
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}
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bool ARMDAGToDAGISel::SelectShifterOperand(SDValue Op,
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SDValue N,
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SDValue &BaseReg,
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SDValue &Opc) {
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ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
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// Don't match base register only case. That is matched to a separate
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// lower complexity pattern with explicit register operand.
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if (ShOpcVal == ARM_AM::no_shift) return false;
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BaseReg = N.getOperand(0);
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unsigned ShImmVal = 0;
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1)))
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ShImmVal = RHS->getZExtValue() & 31;
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else
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return false;
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Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
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return true;
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}
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bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
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SDValue N,
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SDValue N,
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SDValue &BaseReg,
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SDValue &ShReg,
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SDValue &Opc) {
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@ -549,6 +579,10 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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switch (N->getOpcode()) {
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default: break;
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case ISD::Constant: {
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// ARMv6T2 and later should materialize imms via MOV / MOVT pair.
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if (Subtarget->hasV6T2Ops() || Subtarget->hasThumb2())
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break;
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unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
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bool UseCP = true;
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if (Subtarget->isThumb())
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@ -1384,6 +1384,12 @@ def : ARMV5TEPat<(add GPR:$acc,
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include "ARMInstrThumb.td"
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//===----------------------------------------------------------------------===//
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// Thumb2 Support
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//
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include "ARMInstrThumb2.td"
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//===----------------------------------------------------------------------===//
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// Floating Point Support
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//
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@ -10,3 +10,199 @@
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// This file describes the Thumb2 instruction set.
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//
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//===----------------------------------------------------------------------===//
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// Shifted operands. No register controlled shifts for Thumb2.
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// Note: We do not support rrx shifted operands yet.
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def t2_so_reg : Operand<i32>, // reg imm
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ComplexPattern<i32, 2, "SelectShifterOperand",
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[shl,srl,sra,rotr]> {
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let PrintMethod = "printSOOperand";
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let MIOperandInfo = (ops GPR, i32imm);
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}
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def LO16 : SDNodeXForm<imm, [{
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// Transformation function: shift the immediate value down into the low bits.
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return getI32Imm((unsigned short)N->getZExtValue());
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}]>;
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def HI16 : SDNodeXForm<imm, [{
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// Transformation function: shift the immediate value down into the low bits.
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return getI32Imm((unsigned)N->getZExtValue() >> 16);
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}]>;
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def imm16high : PatLeaf<(i32 imm), [{
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// Returns true if all bits out of the [31..16] range are 0.
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return ((N->getZExtValue() & 0xFFFF0000ULL) == N->getZExtValue());
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}], HI16>;
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def imm16high0xffff : PatLeaf<(i32 imm), [{
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// Returns true if lo 16 bits are set and this is a 32-bit value.
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return ((N->getZExtValue() & 0x0000FFFFULL) == 0xFFFFULL);
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}], HI16>;
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def imm0_4095 : PatLeaf<(i32 imm), [{
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return (uint32_t)N->getZExtValue() < 4096;
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}]>;
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def imm0_4095_neg : PatLeaf<(i32 imm), [{
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return (uint32_t)-N->getZExtValue() < 4096;
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}], imm_neg_XFORM>;
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def imm0_65535 : PatLeaf<(i32 imm), [{
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return N->getZExtValue() < 65536;
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}]>;
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// A6.3.2 Modified immediate constants in Thumb instructions (#<const>)
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// FIXME: Move it the the addrmode matcher code.
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def t2_so_imm : PatLeaf<(i32 imm), [{
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uint64_t v = N->getZExtValue();
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if (v == 0 || v > 0xffffffffUL) return false;
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// variant1 - 0b0000x - 8-bit which could be zero (not supported for now)
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// variant2 - 0b00nnx - 8-bit repeated inside the 32-bit room
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unsigned hi16 = (unsigned)(v >> 16);
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unsigned lo16 = (unsigned)(v & 0xffffUL);
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bool valid = (hi16 == lo16) && (
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(v & 0x00ff00ffUL) == 0 || // type 0001x
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(v & 0xff00ff00UL) == 0 || // type 0010x
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((lo16 >> 8) == (lo16 & 0xff))); // type 0011x
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if (valid) return true;
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// variant3 - 0b01000..0b11111 - 8-bit shifted inside the 32-bit room
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unsigned shift = CountLeadingZeros_32(v);
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uint64_t mask = (0xff000000ULL >> shift);
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// If valid, it is type 01000 + shift
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return ((shift < 24) && (v & mask) > 0) && ((v & (~mask)) == 0);
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}]>;
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//===----------------------------------------------------------------------===//
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// Thumb-2 to cover the functionality of the ARM instruction set.
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//
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/// T2I_bin_irs - Defines a set of (op reg, {so_imm|reg|so_reg}) patterns for a
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// binary operation that produces a value.
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multiclass T2I_bin_irs<string opc, PatFrag opnode> {
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// shifted imm
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def ri : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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!strconcat(opc, " $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
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Requires<[HasThumb2]>;
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// register
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def rr : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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!strconcat(opc, " $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
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Requires<[HasThumb2]>;
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// shifted register
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def rs : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
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!strconcat(opc, " $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
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Requires<[HasThumb2]>;
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}
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/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
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/// instruction modifies the CPSR register.
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let Defs = [CPSR] in {
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multiclass T2I_bin_s_irs<string opc, PatFrag opnode> {
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// shifted imm
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def ri : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
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Requires<[HasThumb2]>;
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// register
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def rr : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
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Requires<[HasThumb2]>;
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// shifted register
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def rs : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
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Requires<[HasThumb2]>;
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}
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}
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/// T2I_bin_c_irs - Similar to T2I_bin_irs except it uses the 's' bit. Also the
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/// instruction can optionally set the CPSR register.
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let Uses = [CPSR] in {
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multiclass T2I_bin_c_irs<string opc, PatFrag opnode> {
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// shifted imm
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def ri : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs, cc_out:$s),
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!strconcat(opc, "${s} $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
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Requires<[HasThumb2]>;
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// register
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def rr : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs, cc_out:$s),
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!strconcat(opc, "${s} $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
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Requires<[HasThumb2]>;
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// shifted register
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def rs : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs, cc_out:$s),
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!strconcat(opc, "${s} $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
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Requires<[HasThumb2]>;
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}
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}
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions.
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//
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//===----------------------------------------------------------------------===//
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// Move Instructions.
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//
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def tMOVi16 : PseudoInst<(outs GPR:$dst), (ins i32imm:$src),
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"mov $dst, $src",
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[(set GPR:$dst, imm0_65535:$src)]>,
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Requires<[HasThumb2]>;
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let isTwoAddress = 1 in
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def tMOVTi16 : PseudoInst<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
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"movt $dst, $imm",
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[(set GPR:$dst, (or (and GPR:$src, 0xffff),
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imm16high:$imm))]>,
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Requires<[HasThumb2]>;
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def : Pat<(and (or GPR:$src, imm16high:$imm1), imm16high0xffff:$imm2),
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(tMOVTi16 GPR:$src, (HI16 imm16high:$imm1))>,
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Requires<[HasThumb2]>;
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def : Pat<(i32 imm:$imm),
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(tMOVTi16 (tMOVi16 (LO16 imm:$imm)),(HI16 imm:$imm))>,
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Requires<[HasThumb2]>;
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions.
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//
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defm t2ADD : T2I_bin_irs <"add", BinOpFrag<(add node:$LHS, node:$RHS)>>;
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defm t2SUB : T2I_bin_irs <"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
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def tADDri12 : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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"add $dst, $lhs, $rhs",
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[(set GPR:$dst, (add GPR:$lhs, imm0_4095:$rhs))]>,
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Requires<[HasThumb2]>;
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def tSUBri12 : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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"sub $dst, $lhs, $rhs",
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[(set GPR:$dst, (add GPR:$lhs, imm0_4095_neg:$rhs))]>,
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Requires<[HasThumb2]>;
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defm t2ADDS : T2I_bin_s_irs<"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
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defm t2SUBS : T2I_bin_s_irs<"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
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defm t2ADC : T2I_bin_c_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
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defm t2SBC : T2I_bin_c_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
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def tMLS : PseudoInst<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
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"mls $dst, $a, $b, $c",
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[(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
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Requires<[HasThumb2]>;
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def tORNrs : PseudoInst<(outs GPR:$dst), (ins GPR:$src1, t2_so_reg:$src2),
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"orn $dst, $src1, $src2",
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[(set GPR:$dst, (or GPR:$src1, (not t2_so_reg: $src2)))]>,
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Requires<[HasThumb2]>;
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@ -97,6 +97,7 @@ namespace {
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const char *Modifier = 0);
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void printSOImmOperand(const MachineInstr *MI, int opNum);
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void printSOImm2PartOperand(const MachineInstr *MI, int opNum);
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void printSOOperand(const MachineInstr *MI, int OpNum);
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void printSORegOperand(const MachineInstr *MI, int opNum);
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void printAddrMode2Operand(const MachineInstr *MI, int OpNo);
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void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNo);
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@ -396,6 +397,28 @@ void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
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printSOImm(O, ARM_AM::getSOImmVal(V2), VerboseAsm, TAI);
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}
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// Constant shifts so_reg is a 3-operand unit corresponding to register forms of
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// the A5.1 "Addressing Mode 1 - Data-processing operands" forms. This
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// includes:
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// REG 0 - e.g. R5
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// REG IMM, SH_OPC - e.g. R5, LSL #3
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void ARMAsmPrinter::printSOOperand(const MachineInstr *MI, int OpNum) {
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const MachineOperand &MO1 = MI->getOperand(OpNum);
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const MachineOperand &MO2 = MI->getOperand(OpNum+1);
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unsigned Reg = MO1.getReg();
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assert(TargetRegisterInfo::isPhysicalRegister(Reg));
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O << TM.getRegisterInfo()->getAsmName(Reg);
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// Print the shift opc.
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O << ", "
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<< ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
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<< " ";
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assert(MO2.isImm() && "Not a valid t2_so_reg value!");
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O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
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}
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// so_reg is a 4-operand unit corresponding to register forms of the A5.1
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// "Addressing Mode 1 - Data-processing operands" forms. This includes:
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// REG 0 0 - e.g. R5
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50
test/CodeGen/ARM/thumb2-add.ll
Normal file
50
test/CodeGen/ARM/thumb2-add.ll
Normal file
@ -0,0 +1,50 @@
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | grep #255
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | grep #256
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | grep #257
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | grep #4094
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | grep #4095
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | grep #4096
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | grep lsl | grep #8
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define i32 @t2ADDrc_255(i32 %lhs) {
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%Rd = add i32 %lhs, 255;
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ret i32 %Rd
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}
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define i32 @t2ADDrc_256(i32 %lhs) {
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%Rd = add i32 %lhs, 256;
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ret i32 %Rd
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}
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define i32 @t2ADDrc_257(i32 %lhs) {
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%Rd = add i32 %lhs, 257;
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ret i32 %Rd
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}
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define i32 @t2ADDrc_4094(i32 %lhs) {
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%Rd = add i32 %lhs, 4094;
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ret i32 %Rd
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}
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define i32 @t2ADDrc_4095(i32 %lhs) {
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%Rd = add i32 %lhs, 4095;
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ret i32 %Rd
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}
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define i32 @t2ADDrc_4096(i32 %lhs) {
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%Rd = add i32 %lhs, 4096;
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ret i32 %Rd
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}
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define i32 @t2ADDrr(i32 %lhs, i32 %rhs) {
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%Rd = add i32 %lhs, %rhs;
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ret i32 %Rd
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}
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define i32 @t2ADDrs(i32 %lhs, i32 %rhs) {
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%tmp = shl i32 %rhs, 8
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%Rd = add i32 %lhs, %tmp;
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ret i32 %Rd
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}
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127
test/CodeGen/ARM/thumb2-mov.ll
Normal file
127
test/CodeGen/ARM/thumb2-mov.ll
Normal file
@ -0,0 +1,127 @@
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep #11206827
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep #2868947712
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep #2880154539
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep #251658240
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep #3948544
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep #258
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep #4026531840
|
||||
|
||||
; Test #<const>
|
||||
|
||||
; var 2.1 - 0x00ab00ab
|
||||
define i32 @t2_const_var2_1_ok_1(i32 %lhs) {
|
||||
%ret = add i32 %lhs, 11206827 ; 0x00ab00ab
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
define i32 @t2_const_var2_1_fail_1(i32 %lhs) {
|
||||
%ret = add i32 %lhs, 11206843 ; 0x00ab00bb
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
define i32 @t2_const_var2_1_fail_2(i32 %lhs) {
|
||||
%ret = add i32 %lhs, 27984043 ; 0x01ab00ab
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
define i32 @t2_const_var2_1_fail_3(i32 %lhs) {
|
||||
%ret = add i32 %lhs, 27984299 ; 0x01ab01ab
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
define i32 @t2_const_var2_1_fail_4(i32 %lhs) {
|
||||
%ret = add i32 %lhs, 28027649 ; 0x01abab01
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
; var 2.2 - 0xab00ab00
|
||||
define i32 @t2_const_var2_2_ok_1(i32 %lhs) {
|
||||
%ret = add i32 %lhs, 2868947712 ; 0xab00ab00
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
define i32 @t2_const_var2_2_fail_1(i32 %lhs) {
|
||||
%ret = add i32 %lhs, 2868951552 ; 0xab00ba00
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
define i32 @t2_const_var2_2_fail_2(i32 %lhs) {
|
||||
%ret = add i32 %lhs, 2868947728 ; 0xab00ab10
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
define i32 @t2_const_var2_2_fail_3(i32 %lhs) {
|
||||
%ret = add i32 %lhs, 2869996304 ; 0xab10ab10
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
define i32 @t2_const_var2_2_fail_4(i32 %lhs) {
|
||||
%ret = add i32 %lhs, 279685904 ; 0x10abab10
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
; var 2.3 - 0xabababab
|
||||
define i32 @t2_const_var2_3_ok_1(i32 %lhs) {
|
||||
%ret = add i32 %lhs, 2880154539 ; 0xabababab
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
define i32 @t2_const_var2_3_fail_1(i32 %lhs) {
|
||||
%ret = add i32 %lhs, 2880154554 ; 0xabababba
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
define i32 @t2_const_var2_3_fail_2(i32 %lhs) {
|
||||
%ret = add i32 %lhs, 2880158379 ; 0xababbaab
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
define i32 @t2_const_var2_3_fail_3(i32 %lhs) {
|
||||
%ret = add i32 %lhs, 2881137579 ; 0xabbaabab
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
define i32 @t2_const_var2_3_fail_4(i32 %lhs) {
|
||||
%ret = add i32 %lhs, 3131812779 ; 0xbaababab
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
; var 3 - 0x0F000000
|
||||
define i32 @t2_const_var3_1_ok_1(i32 %lhs) {
|
||||
%ret = add i32 %lhs, 251658240 ; 0x0F000000
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
define i32 @t2_const_var3_2_ok_1(i32 %lhs) {
|
||||
%ret = add i32 %lhs, 3948544 ; 0b00000000001111000100000000000000
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
define i32 @t2_const_var3_2_fail_1(i32 %lhs) {
|
||||
%ret = add i32 %lhs, 3940352 ; 0b00000000001111000010000000000000
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
define i32 @t2_const_var3_3_ok_1(i32 %lhs) {
|
||||
%ret = add i32 %lhs, 258 ; 0b00000000000000000000000100000010
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
define i32 @t2_const_var3_4_ok_1(i32 %lhs) {
|
||||
%ret = add i32 %lhs, 4026531840 ; 0xF0000000
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
65
test/CodeGen/ARM/thumb2-mov2.ll
Normal file
65
test/CodeGen/ARM/thumb2-mov2.ll
Normal file
@ -0,0 +1,65 @@
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep movt | grep #1234
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep movt | grep #1234
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep movt | grep #1234
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep movt | grep #1234
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt
|
||||
|
||||
define i32 @t2MOVTi16_ok_1(i32 %a) {
|
||||
%1 = and i32 %a, 65535
|
||||
%2 = shl i32 1234, 16
|
||||
%3 = or i32 %1, %2
|
||||
|
||||
ret i32 %3
|
||||
}
|
||||
|
||||
define i32 @t2MOVTi16_test_1(i32 %a) {
|
||||
%1 = shl i32 255, 8
|
||||
%2 = shl i32 1234, 8
|
||||
%3 = or i32 %1, 255 ; This give us 0xFFFF in %3
|
||||
%4 = shl i32 %2, 8 ; This gives us (1234 << 16) in %4
|
||||
%5 = and i32 %a, %3
|
||||
%6 = or i32 %4, %5
|
||||
|
||||
ret i32 %6
|
||||
}
|
||||
|
||||
define i32 @t2MOVTi16_test_2(i32 %a) {
|
||||
%1 = shl i32 255, 8
|
||||
%2 = shl i32 1234, 8
|
||||
%3 = or i32 %1, 255 ; This give us 0xFFFF in %3
|
||||
%4 = shl i32 %2, 6
|
||||
%5 = and i32 %a, %3
|
||||
%6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6
|
||||
%7 = or i32 %5, %6
|
||||
|
||||
ret i32 %7
|
||||
}
|
||||
|
||||
define i32 @t2MOVTi16_test_3(i32 %a) {
|
||||
%1 = shl i32 255, 8
|
||||
%2 = shl i32 1234, 8
|
||||
%3 = or i32 %1, 255 ; This give us 0xFFFF in %3
|
||||
%4 = shl i32 %2, 6
|
||||
%5 = and i32 %a, %3
|
||||
%6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6
|
||||
%7 = lshr i32 %6, 6
|
||||
%8 = shl i32 %7, 6
|
||||
%9 = or i32 %5, %8
|
||||
|
||||
ret i32 %9
|
||||
}
|
||||
|
||||
define i32 @t2MOVTi16_test_nomatch_1(i32 %a) {
|
||||
%1 = shl i32 255, 8
|
||||
%2 = shl i32 1234, 8
|
||||
%3 = or i32 %1, 255 ; This give us 0xFFFF in %3
|
||||
%4 = shl i32 %2, 6
|
||||
%5 = and i32 %a, %3
|
||||
%6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6
|
||||
%7 = lshr i32 %6, 3
|
||||
%8 = or i32 %5, %7
|
||||
|
||||
ret i32 %8
|
||||
}
|
||||
|
||||
|
||||
40
test/CodeGen/ARM/thumb2-shifter.ll
Normal file
40
test/CodeGen/ARM/thumb2-shifter.ll
Normal file
@ -0,0 +1,40 @@
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep lsl
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep lsr
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep asr
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep ror
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov
|
||||
|
||||
define i32 @t2ADDrs_lsl(i32 %X, i32 %Y) {
|
||||
%A = shl i32 %Y, 16
|
||||
%B = add i32 %X, %A
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @t2ADDrs_lsr(i32 %X, i32 %Y) {
|
||||
%A = lshr i32 %Y, 16
|
||||
%B = add i32 %X, %A
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @t2ADDrs_asr(i32 %X, i32 %Y) {
|
||||
%A = ashr i32 %Y, 16
|
||||
%B = add i32 %X, %A
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
; i32 ror(n) = (x >> n) | (x << (32 - n))
|
||||
define i32 @t2ADDrs_ror(i32 %X, i32 %Y) {
|
||||
%A = lshr i32 %Y, 16
|
||||
%B = shl i32 %Y, 16
|
||||
%C = or i32 %B, %A
|
||||
%R = add i32 %X, %C
|
||||
ret i32 %R
|
||||
}
|
||||
|
||||
define i32 @t2ADDrs_noRegShift(i32 %X, i32 %Y, i8 %sh) {
|
||||
%shift.upgrd.1 = zext i8 %sh to i32
|
||||
%A = shl i32 %Y, %shift.upgrd.1
|
||||
%B = add i32 %X, %A
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user