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[AArch64] Add tests for bool vector reductions; NFC
Baseline tests for PR41635. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359723 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nikita Popov
parent
97aed04cd1
commit
534153e0e5
304
test/CodeGen/AArch64/vecreduce-bool.ll
Normal file
304
test/CodeGen/AArch64/vecreduce-bool.ll
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@ -0,0 +1,304 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
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declare i1 @llvm.experimental.vector.reduce.and.i1.v1i1(<1 x i1> %a)
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declare i1 @llvm.experimental.vector.reduce.and.i1.v2i1(<2 x i1> %a)
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declare i1 @llvm.experimental.vector.reduce.and.i1.v4i1(<4 x i1> %a)
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declare i1 @llvm.experimental.vector.reduce.and.i1.v8i1(<8 x i1> %a)
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declare i1 @llvm.experimental.vector.reduce.and.i1.v16i1(<16 x i1> %a)
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declare i1 @llvm.experimental.vector.reduce.and.i1.v32i1(<32 x i1> %a)
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declare i1 @llvm.experimental.vector.reduce.or.i1.v1i1(<1 x i1> %a)
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declare i1 @llvm.experimental.vector.reduce.or.i1.v2i1(<2 x i1> %a)
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declare i1 @llvm.experimental.vector.reduce.or.i1.v4i1(<4 x i1> %a)
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declare i1 @llvm.experimental.vector.reduce.or.i1.v8i1(<8 x i1> %a)
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declare i1 @llvm.experimental.vector.reduce.or.i1.v16i1(<16 x i1> %a)
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declare i1 @llvm.experimental.vector.reduce.or.i1.v32i1(<32 x i1> %a)
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define i32 @reduce_and_v1(<1 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_and_v1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: smov w8, v0.b[0]
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; CHECK-NEXT: cmp w8, #0 // =0
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; CHECK-NEXT: csel w0, w0, w1, lt
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; CHECK-NEXT: ret
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%x = icmp slt <1 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.and.i1.v1i1(<1 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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define i32 @reduce_and_v2(<2 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_and_v2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shl v0.2s, v0.2s, #24
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; CHECK-NEXT: sshr v0.2s, v0.2s, #24
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; CHECK-NEXT: cmlt v0.2s, v0.2s, #0
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; CHECK-NEXT: mov w8, v0.s[1]
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: and w8, w9, w8
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; CHECK-NEXT: tst w8, #0x1
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; CHECK-NEXT: csel w0, w0, w1, ne
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; CHECK-NEXT: ret
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%x = icmp slt <2 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.and.i1.v2i1(<2 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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define i32 @reduce_and_v4(<4 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_and_v4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shl v0.4h, v0.4h, #8
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; CHECK-NEXT: sshr v0.4h, v0.4h, #8
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; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
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; CHECK-NEXT: umov w10, v0.h[1]
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; CHECK-NEXT: umov w11, v0.h[0]
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; CHECK-NEXT: umov w9, v0.h[2]
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; CHECK-NEXT: and w10, w11, w10
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; CHECK-NEXT: umov w8, v0.h[3]
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; CHECK-NEXT: and w9, w10, w9
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; CHECK-NEXT: and w8, w9, w8
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; CHECK-NEXT: tst w8, #0x1
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; CHECK-NEXT: csel w0, w0, w1, ne
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; CHECK-NEXT: ret
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%x = icmp slt <4 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.and.i1.v4i1(<4 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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define i32 @reduce_and_v8(<8 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_and_v8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
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; CHECK-NEXT: umov w14, v0.b[1]
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; CHECK-NEXT: umov w15, v0.b[0]
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; CHECK-NEXT: umov w13, v0.b[2]
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; CHECK-NEXT: and w14, w15, w14
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; CHECK-NEXT: umov w12, v0.b[3]
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; CHECK-NEXT: and w13, w14, w13
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; CHECK-NEXT: umov w11, v0.b[4]
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; CHECK-NEXT: and w12, w13, w12
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; CHECK-NEXT: umov w10, v0.b[5]
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; CHECK-NEXT: and w11, w12, w11
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; CHECK-NEXT: umov w9, v0.b[6]
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; CHECK-NEXT: and w10, w11, w10
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; CHECK-NEXT: umov w8, v0.b[7]
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; CHECK-NEXT: and w9, w10, w9
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; CHECK-NEXT: and w8, w9, w8
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; CHECK-NEXT: tst w8, #0x1
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; CHECK-NEXT: csel w0, w0, w1, ne
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; CHECK-NEXT: ret
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%x = icmp slt <8 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.and.i1.v8i1(<8 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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define i32 @reduce_and_v16(<16 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_and_v16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
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; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: umov w8, v0.b[1]
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; CHECK-NEXT: umov w9, v0.b[0]
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; CHECK-NEXT: and w8, w9, w8
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; CHECK-NEXT: umov w9, v0.b[2]
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; CHECK-NEXT: and w8, w8, w9
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; CHECK-NEXT: umov w9, v0.b[3]
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; CHECK-NEXT: and w8, w8, w9
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; CHECK-NEXT: umov w9, v0.b[4]
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; CHECK-NEXT: and w8, w8, w9
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; CHECK-NEXT: umov w9, v0.b[5]
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; CHECK-NEXT: and w8, w8, w9
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; CHECK-NEXT: umov w9, v0.b[6]
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; CHECK-NEXT: and w8, w8, w9
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; CHECK-NEXT: umov w9, v0.b[7]
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; CHECK-NEXT: and w8, w8, w9
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; CHECK-NEXT: tst w8, #0x1
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; CHECK-NEXT: csel w0, w0, w1, ne
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; CHECK-NEXT: ret
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%x = icmp slt <16 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.and.i1.v16i1(<16 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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define i32 @reduce_and_v32(<32 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_and_v32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v1.16b, v1.16b, #0
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; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: umov w8, v0.b[1]
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; CHECK-NEXT: umov w9, v0.b[0]
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; CHECK-NEXT: and w8, w9, w8
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; CHECK-NEXT: umov w9, v0.b[2]
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; CHECK-NEXT: and w8, w8, w9
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; CHECK-NEXT: umov w9, v0.b[3]
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; CHECK-NEXT: and w8, w8, w9
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; CHECK-NEXT: umov w9, v0.b[4]
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; CHECK-NEXT: and w8, w8, w9
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; CHECK-NEXT: umov w9, v0.b[5]
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; CHECK-NEXT: and w8, w8, w9
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; CHECK-NEXT: umov w9, v0.b[6]
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; CHECK-NEXT: and w8, w8, w9
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; CHECK-NEXT: umov w9, v0.b[7]
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; CHECK-NEXT: and w8, w8, w9
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; CHECK-NEXT: tst w8, #0x1
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; CHECK-NEXT: csel w0, w0, w1, ne
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; CHECK-NEXT: ret
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%x = icmp slt <32 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.and.i1.v32i1(<32 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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define i32 @reduce_or_v1(<1 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_or_v1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: smov w8, v0.b[0]
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; CHECK-NEXT: cmp w8, #0 // =0
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; CHECK-NEXT: csel w0, w0, w1, lt
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; CHECK-NEXT: ret
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%x = icmp slt <1 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.or.i1.v1i1(<1 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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define i32 @reduce_or_v2(<2 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_or_v2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shl v0.2s, v0.2s, #24
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; CHECK-NEXT: sshr v0.2s, v0.2s, #24
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; CHECK-NEXT: cmlt v0.2s, v0.2s, #0
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; CHECK-NEXT: mov w8, v0.s[1]
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: orr w8, w9, w8
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; CHECK-NEXT: tst w8, #0x1
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; CHECK-NEXT: csel w0, w0, w1, ne
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; CHECK-NEXT: ret
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%x = icmp slt <2 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.or.i1.v2i1(<2 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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define i32 @reduce_or_v4(<4 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_or_v4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shl v0.4h, v0.4h, #8
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; CHECK-NEXT: sshr v0.4h, v0.4h, #8
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; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
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; CHECK-NEXT: umov w10, v0.h[1]
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; CHECK-NEXT: umov w11, v0.h[0]
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; CHECK-NEXT: umov w9, v0.h[2]
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; CHECK-NEXT: orr w10, w11, w10
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; CHECK-NEXT: umov w8, v0.h[3]
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; CHECK-NEXT: orr w9, w10, w9
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; CHECK-NEXT: orr w8, w9, w8
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; CHECK-NEXT: tst w8, #0x1
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; CHECK-NEXT: csel w0, w0, w1, ne
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; CHECK-NEXT: ret
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%x = icmp slt <4 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.or.i1.v4i1(<4 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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define i32 @reduce_or_v8(<8 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_or_v8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
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; CHECK-NEXT: umov w14, v0.b[1]
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; CHECK-NEXT: umov w15, v0.b[0]
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; CHECK-NEXT: umov w13, v0.b[2]
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; CHECK-NEXT: orr w14, w15, w14
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; CHECK-NEXT: umov w12, v0.b[3]
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; CHECK-NEXT: orr w13, w14, w13
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; CHECK-NEXT: umov w11, v0.b[4]
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; CHECK-NEXT: orr w12, w13, w12
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; CHECK-NEXT: umov w10, v0.b[5]
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; CHECK-NEXT: orr w11, w12, w11
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; CHECK-NEXT: umov w9, v0.b[6]
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; CHECK-NEXT: orr w10, w11, w10
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; CHECK-NEXT: umov w8, v0.b[7]
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; CHECK-NEXT: orr w9, w10, w9
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; CHECK-NEXT: orr w8, w9, w8
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; CHECK-NEXT: tst w8, #0x1
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; CHECK-NEXT: csel w0, w0, w1, ne
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; CHECK-NEXT: ret
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%x = icmp slt <8 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.or.i1.v8i1(<8 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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define i32 @reduce_or_v16(<16 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_or_v16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
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; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: umov w8, v0.b[1]
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; CHECK-NEXT: umov w9, v0.b[0]
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; CHECK-NEXT: orr w8, w9, w8
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; CHECK-NEXT: umov w9, v0.b[2]
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; CHECK-NEXT: orr w8, w8, w9
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; CHECK-NEXT: umov w9, v0.b[3]
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; CHECK-NEXT: orr w8, w8, w9
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; CHECK-NEXT: umov w9, v0.b[4]
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; CHECK-NEXT: orr w8, w8, w9
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; CHECK-NEXT: umov w9, v0.b[5]
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; CHECK-NEXT: orr w8, w8, w9
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; CHECK-NEXT: umov w9, v0.b[6]
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; CHECK-NEXT: orr w8, w8, w9
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; CHECK-NEXT: umov w9, v0.b[7]
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; CHECK-NEXT: orr w8, w8, w9
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; CHECK-NEXT: tst w8, #0x1
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; CHECK-NEXT: csel w0, w0, w1, ne
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; CHECK-NEXT: ret
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%x = icmp slt <16 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.or.i1.v16i1(<16 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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define i32 @reduce_or_v32(<32 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_or_v32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v1.16b, v1.16b, #0
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; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
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; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: umov w8, v0.b[1]
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; CHECK-NEXT: umov w9, v0.b[0]
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; CHECK-NEXT: orr w8, w9, w8
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; CHECK-NEXT: umov w9, v0.b[2]
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; CHECK-NEXT: orr w8, w8, w9
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; CHECK-NEXT: umov w9, v0.b[3]
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; CHECK-NEXT: orr w8, w8, w9
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; CHECK-NEXT: umov w9, v0.b[4]
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; CHECK-NEXT: orr w8, w8, w9
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; CHECK-NEXT: umov w9, v0.b[5]
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; CHECK-NEXT: orr w8, w8, w9
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; CHECK-NEXT: umov w9, v0.b[6]
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; CHECK-NEXT: orr w8, w8, w9
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; CHECK-NEXT: umov w9, v0.b[7]
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; CHECK-NEXT: orr w8, w8, w9
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; CHECK-NEXT: tst w8, #0x1
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; CHECK-NEXT: csel w0, w0, w1, ne
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; CHECK-NEXT: ret
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%x = icmp slt <32 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.or.i1.v32i1(<32 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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