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R600/SI: Add a VALU pattern for i64 xor

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211373 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2014-06-20 17:05:57 +00:00
parent 69e4786797
commit 538c95179c
2 changed files with 33 additions and 4 deletions
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11
lib/Target/R600/SIInstructions.td
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@ -1773,15 +1773,18 @@ def : RsqPat<V_RSQ_F64_e32, f64>;
// VOP2 Patterns
//===----------------------------------------------------------------------===//
def : Pat <
(or i64:$src0, i64:$src1),
class BinOp64Pat <SDNode node, Instruction inst> : Pat <
(node i64:$src0, i64:$src1),
(INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub0),
(inst (EXTRACT_SUBREG i64:$src0, sub0),
(EXTRACT_SUBREG i64:$src1, sub0)), sub0),
(V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub1),
(inst (EXTRACT_SUBREG i64:$src0, sub1),
(EXTRACT_SUBREG i64:$src1, sub1)), sub1)
>;
def : BinOp64Pat <or, V_OR_B32_e32>;
def : BinOp64Pat <xor, V_XOR_B32_e32>;
class SextInReg <ValueType vt, int ShiftAmt> : Pat <
(sext_inreg i32:$src0, vt),
(V_ASHRREV_I32_e32 ShiftAmt, (V_LSHLREV_B32_e32 ShiftAmt, $src0))

26
test/CodeGen/R600/xor.ll
View File

@ -130,3 +130,29 @@ define void @vector_not_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i64
store i64 %result, i64 addrspace(1)* %out
ret void
}
; Test that we have a pattern to match xor inside a branch.
; Note that in the future the backend may be smart enough to
; use an SALU instruction for this.
; SI-CHECK-LABEL: @xor_cf
; SI-CHECK: V_XOR
; SI-CHECK: V_XOR
define void @xor_cf(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b) {
entry:
%0 = icmp eq i64 %a, 0
br i1 %0, label %if, label %else
if:
%1 = xor i64 %a, %b
br label %endif
else:
%2 = load i64 addrspace(1)* %in
br label %endif
endif:
%3 = phi i64 [%1, %if], [%2, %else]
store i64 %3, i64 addrspace(1)* %out
ret void
}