mirror of
https://github.com/RPCS3/llvm.git
synced 2024-12-14 15:39:06 +00:00
Change errs() to dbgs().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92093 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Greene
parent
afd52024e5
commit
5393b25234
@ -127,11 +127,11 @@ AggressiveAntiDepBreaker(MachineFunction& MFi,
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CriticalPathSet |= CPSet;
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}
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DEBUG(errs() << "AntiDep Critical-Path Registers:");
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DEBUG(dbgs() << "AntiDep Critical-Path Registers:");
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DEBUG(for (int r = CriticalPathSet.find_first(); r != -1;
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r = CriticalPathSet.find_next(r))
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errs() << " " << TRI->getName(r));
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DEBUG(errs() << '\n');
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dbgs() << " " << TRI->getName(r));
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DEBUG(dbgs() << '\n');
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}
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AggressiveAntiDepBreaker::~AggressiveAntiDepBreaker() {
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@ -218,9 +218,9 @@ void AggressiveAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
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PrescanInstruction(MI, Count, PassthruRegs);
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ScanInstruction(MI, Count);
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DEBUG(errs() << "Observe: ");
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DEBUG(dbgs() << "Observe: ");
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DEBUG(MI->dump());
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DEBUG(errs() << "\tRegs:");
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DEBUG(dbgs() << "\tRegs:");
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unsigned *DefIndices = State->GetDefIndices();
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for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
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@ -232,14 +232,14 @@ void AggressiveAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
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// schedule region).
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if (State->IsLive(Reg)) {
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DEBUG(if (State->GetGroup(Reg) != 0)
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errs() << " " << TRI->getName(Reg) << "=g" <<
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dbgs() << " " << TRI->getName(Reg) << "=g" <<
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State->GetGroup(Reg) << "->g0(region live-out)");
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State->UnionGroups(Reg, 0);
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} else if ((DefIndices[Reg] < InsertPosIndex) && (DefIndices[Reg] >= Count)) {
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DefIndices[Reg] = Count;
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}
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}
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DEBUG(errs() << '\n');
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DEBUG(dbgs() << '\n');
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}
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bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr *MI,
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@ -333,8 +333,8 @@ void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
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RegRefs.erase(Reg);
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State->LeaveGroup(Reg);
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DEBUG(if (header != NULL) {
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errs() << header << TRI->getName(Reg); header = NULL; });
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DEBUG(errs() << "->g" << State->GetGroup(Reg) << tag);
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dbgs() << header << TRI->getName(Reg); header = NULL; });
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DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);
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}
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// Repeat for subregisters.
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for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
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@ -346,13 +346,13 @@ void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
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RegRefs.erase(SubregReg);
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State->LeaveGroup(SubregReg);
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DEBUG(if (header != NULL) {
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errs() << header << TRI->getName(Reg); header = NULL; });
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DEBUG(errs() << " " << TRI->getName(SubregReg) << "->g" <<
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dbgs() << header << TRI->getName(Reg); header = NULL; });
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DEBUG(dbgs() << " " << TRI->getName(SubregReg) << "->g" <<
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State->GetGroup(SubregReg) << tag);
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}
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}
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DEBUG(if ((header == NULL) && (footer != NULL)) errs() << footer);
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DEBUG(if ((header == NULL) && (footer != NULL)) dbgs() << footer);
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}
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void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, unsigned Count,
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@ -375,20 +375,20 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, unsigned Cou
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HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n");
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}
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DEBUG(errs() << "\tDef Groups:");
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DEBUG(dbgs() << "\tDef Groups:");
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isDef()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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DEBUG(errs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg));
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DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg));
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// If MI's defs have a special allocation requirement, don't allow
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// any def registers to be changed. Also assume all registers
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// defined in a call must not be changed (ABI).
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if (MI->getDesc().isCall() || MI->getDesc().hasExtraDefRegAllocReq()) {
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DEBUG(if (State->GetGroup(Reg) != 0) errs() << "->g0(alloc-req)");
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DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
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State->UnionGroups(Reg, 0);
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}
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@ -398,7 +398,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, unsigned Cou
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unsigned AliasReg = *Alias;
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if (State->IsLive(AliasReg)) {
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State->UnionGroups(Reg, AliasReg);
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DEBUG(errs() << "->g" << State->GetGroup(Reg) << "(via " <<
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DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " <<
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TRI->getName(AliasReg) << ")");
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}
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}
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@ -411,7 +411,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, unsigned Cou
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RegRefs.insert(std::make_pair(Reg, RR));
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}
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DEBUG(errs() << '\n');
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DEBUG(dbgs() << '\n');
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// Scan the register defs for this instruction and update
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// live-ranges.
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@ -437,7 +437,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, unsigned Cou
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void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
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unsigned Count) {
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DEBUG(errs() << "\tUse Groups:");
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DEBUG(dbgs() << "\tUse Groups:");
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std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
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RegRefs = State->GetRegRefs();
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@ -449,7 +449,7 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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DEBUG(errs() << " " << TRI->getName(Reg) << "=g" <<
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DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" <<
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State->GetGroup(Reg));
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// It wasn't previously live but now it is, this is a kill. Forget
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@ -461,7 +461,7 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
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// any use registers to be changed. Also assume all registers
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// used in a call must not be changed (ABI).
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if (MI->getDesc().isCall() || MI->getDesc().hasExtraSrcRegAllocReq()) {
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DEBUG(if (State->GetGroup(Reg) != 0) errs() << "->g0(alloc-req)");
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DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
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State->UnionGroups(Reg, 0);
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}
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@ -473,12 +473,12 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
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RegRefs.insert(std::make_pair(Reg, RR));
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}
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DEBUG(errs() << '\n');
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DEBUG(dbgs() << '\n');
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// Form a group of all defs and uses of a KILL instruction to ensure
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// that all registers are renamed as a group.
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if (MI->getOpcode() == TargetInstrInfo::KILL) {
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DEBUG(errs() << "\tKill Group:");
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DEBUG(dbgs() << "\tKill Group:");
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unsigned FirstReg = 0;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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@ -488,15 +488,15 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
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if (Reg == 0) continue;
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if (FirstReg != 0) {
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DEBUG(errs() << "=" << TRI->getName(Reg));
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DEBUG(dbgs() << "=" << TRI->getName(Reg));
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State->UnionGroups(FirstReg, Reg);
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} else {
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DEBUG(errs() << " " << TRI->getName(Reg));
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DEBUG(dbgs() << " " << TRI->getName(Reg));
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FirstReg = Reg;
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}
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}
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DEBUG(errs() << "->g" << State->GetGroup(FirstReg) << '\n');
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DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n');
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}
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}
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@ -525,7 +525,7 @@ BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
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BV &= RCBV;
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}
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DEBUG(errs() << " " << RC->getName());
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DEBUG(dbgs() << " " << RC->getName());
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}
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return BV;
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@ -552,7 +552,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
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// Find the "superest" register in the group. At the same time,
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// collect the BitVector of registers that can be used to rename
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// each register.
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DEBUG(errs() << "\tRename Candidates for Group g" << AntiDepGroupIndex << ":\n");
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DEBUG(dbgs() << "\tRename Candidates for Group g" << AntiDepGroupIndex << ":\n");
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std::map<unsigned, BitVector> RenameRegisterMap;
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unsigned SuperReg = 0;
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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@ -562,15 +562,15 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
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// If Reg has any references, then collect possible rename regs
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if (RegRefs.count(Reg) > 0) {
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DEBUG(errs() << "\t\t" << TRI->getName(Reg) << ":");
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DEBUG(dbgs() << "\t\t" << TRI->getName(Reg) << ":");
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BitVector BV = GetRenameRegisters(Reg);
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RenameRegisterMap.insert(std::pair<unsigned, BitVector>(Reg, BV));
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DEBUG(errs() << " ::");
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DEBUG(dbgs() << " ::");
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DEBUG(for (int r = BV.find_first(); r != -1; r = BV.find_next(r))
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errs() << " " << TRI->getName(r));
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DEBUG(errs() << "\n");
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dbgs() << " " << TRI->getName(r));
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DEBUG(dbgs() << "\n");
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}
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}
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@ -591,7 +591,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
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if (renamecnt++ % DebugDiv != DebugMod)
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return false;
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errs() << "*** Performing rename " << TRI->getName(SuperReg) <<
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dbgs() << "*** Performing rename " << TRI->getName(SuperReg) <<
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" for debug ***\n";
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}
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#endif
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@ -606,11 +606,11 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
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const TargetRegisterClass::iterator RB = SuperRC->allocation_order_begin(MF);
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const TargetRegisterClass::iterator RE = SuperRC->allocation_order_end(MF);
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if (RB == RE) {
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DEBUG(errs() << "\tEmpty Super Regclass!!\n");
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DEBUG(dbgs() << "\tEmpty Super Regclass!!\n");
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return false;
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}
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DEBUG(errs() << "\tFind Registers:");
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DEBUG(dbgs() << "\tFind Registers:");
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if (RenameOrder.count(SuperRC) == 0)
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RenameOrder.insert(RenameOrderType::value_type(SuperRC, RE));
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@ -625,7 +625,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
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// Don't replace a register with itself.
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if (NewSuperReg == SuperReg) continue;
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DEBUG(errs() << " [" << TRI->getName(NewSuperReg) << ':');
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DEBUG(dbgs() << " [" << TRI->getName(NewSuperReg) << ':');
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RenameMap.clear();
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// For each referenced group register (which must be a SuperReg or
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@ -642,12 +642,12 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
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NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx);
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}
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DEBUG(errs() << " " << TRI->getName(NewReg));
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DEBUG(dbgs() << " " << TRI->getName(NewReg));
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// Check if Reg can be renamed to NewReg.
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BitVector BV = RenameRegisterMap[Reg];
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if (!BV.test(NewReg)) {
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DEBUG(errs() << "(no rename)");
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DEBUG(dbgs() << "(no rename)");
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goto next_super_reg;
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}
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@ -656,7 +656,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
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// must also check all aliases of NewReg, because we can't define a
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// register when any sub or super is already live.
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if (State->IsLive(NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) {
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DEBUG(errs() << "(live)");
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DEBUG(dbgs() << "(live)");
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goto next_super_reg;
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} else {
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bool found = false;
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@ -664,7 +664,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
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*Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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if (State->IsLive(AliasReg) || (KillIndices[Reg] > DefIndices[AliasReg])) {
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DEBUG(errs() << "(alias " << TRI->getName(AliasReg) << " live)");
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DEBUG(dbgs() << "(alias " << TRI->getName(AliasReg) << " live)");
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found = true;
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break;
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}
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@ -681,14 +681,14 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
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// renamed, as recorded in RenameMap.
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RenameOrder.erase(SuperRC);
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RenameOrder.insert(RenameOrderType::value_type(SuperRC, R));
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DEBUG(errs() << "]\n");
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DEBUG(dbgs() << "]\n");
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return true;
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next_super_reg:
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DEBUG(errs() << ']');
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DEBUG(dbgs() << ']');
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} while (R != EndR);
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DEBUG(errs() << '\n');
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DEBUG(dbgs() << '\n');
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// No registers are free and available!
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return false;
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@ -740,13 +740,13 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
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}
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#ifndef NDEBUG
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DEBUG(errs() << "\n===== Aggressive anti-dependency breaking\n");
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DEBUG(errs() << "Available regs:");
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DEBUG(dbgs() << "\n===== Aggressive anti-dependency breaking\n");
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DEBUG(dbgs() << "Available regs:");
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for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
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if (!State->IsLive(Reg))
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DEBUG(errs() << " " << TRI->getName(Reg));
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DEBUG(dbgs() << " " << TRI->getName(Reg));
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}
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DEBUG(errs() << '\n');
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DEBUG(dbgs() << '\n');
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#endif
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// Attempt to break anti-dependence edges. Walk the instructions
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@ -758,7 +758,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
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I != E; --Count) {
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MachineInstr *MI = --I;
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DEBUG(errs() << "Anti: ");
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DEBUG(dbgs() << "Anti: ");
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DEBUG(MI->dump());
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std::set<unsigned> PassthruRegs;
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@ -795,30 +795,30 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
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(Edge->getKind() != SDep::Output)) continue;
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unsigned AntiDepReg = Edge->getReg();
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DEBUG(errs() << "\tAntidep reg: " << TRI->getName(AntiDepReg));
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DEBUG(dbgs() << "\tAntidep reg: " << TRI->getName(AntiDepReg));
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assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
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if (!AllocatableSet.test(AntiDepReg)) {
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// Don't break anti-dependencies on non-allocatable registers.
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DEBUG(errs() << " (non-allocatable)\n");
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DEBUG(dbgs() << " (non-allocatable)\n");
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continue;
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} else if ((ExcludeRegs != NULL) && ExcludeRegs->test(AntiDepReg)) {
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// Don't break anti-dependencies for critical path registers
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// if not on the critical path
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DEBUG(errs() << " (not critical-path)\n");
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DEBUG(dbgs() << " (not critical-path)\n");
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continue;
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} else if (PassthruRegs.count(AntiDepReg) != 0) {
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// If the anti-dep register liveness "passes-thru", then
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// don't try to change it. It will be changed along with
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// the use if required to break an earlier antidep.
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DEBUG(errs() << " (passthru)\n");
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DEBUG(dbgs() << " (passthru)\n");
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continue;
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} else {
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// No anti-dep breaking for implicit deps
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MachineOperand *AntiDepOp = MI->findRegisterDefOperand(AntiDepReg);
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assert(AntiDepOp != NULL && "Can't find index for defined register operand");
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if ((AntiDepOp == NULL) || AntiDepOp->isImplicit()) {
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DEBUG(errs() << " (implicit)\n");
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DEBUG(dbgs() << " (implicit)\n");
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continue;
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}
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@ -844,13 +844,13 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
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PE = PathSU->Preds.end(); P != PE; ++P) {
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if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti) &&
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(P->getKind() != SDep::Output)) {
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DEBUG(errs() << " (real dependency)\n");
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DEBUG(dbgs() << " (real dependency)\n");
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AntiDepReg = 0;
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break;
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} else if ((P->getSUnit() != NextSU) &&
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(P->getKind() == SDep::Data) &&
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(P->getReg() == AntiDepReg)) {
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DEBUG(errs() << " (other dependency)\n");
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DEBUG(dbgs() << " (other dependency)\n");
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AntiDepReg = 0;
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break;
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}
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@ -865,16 +865,16 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
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// Determine AntiDepReg's register group.
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const unsigned GroupIndex = State->GetGroup(AntiDepReg);
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if (GroupIndex == 0) {
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DEBUG(errs() << " (zero group)\n");
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DEBUG(dbgs() << " (zero group)\n");
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continue;
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}
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DEBUG(errs() << '\n');
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DEBUG(dbgs() << '\n');
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// Look for a suitable register to use to break the anti-dependence.
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std::map<unsigned, unsigned> RenameMap;
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if (FindSuitableFreeRegisters(GroupIndex, RenameOrder, RenameMap)) {
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DEBUG(errs() << "\tBreaking anti-dependence edge on "
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DEBUG(dbgs() << "\tBreaking anti-dependence edge on "
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<< TRI->getName(AntiDepReg) << ":");
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// Handle each group register...
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@ -883,7 +883,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
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unsigned CurrReg = S->first;
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unsigned NewReg = S->second;
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DEBUG(errs() << " " << TRI->getName(CurrReg) << "->" <<
|
||||
DEBUG(dbgs() << " " << TRI->getName(CurrReg) << "->" <<
|
||||
TRI->getName(NewReg) << "(" <<
|
||||
RegRefs.count(CurrReg) << " refs)");
|
||||
|
||||
@ -917,7 +917,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
|
||||
}
|
||||
|
||||
++Broken;
|
||||
DEBUG(errs() << '\n');
|
||||
DEBUG(dbgs() << '\n');
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user