From 53bf81ae5973ba8ac185466746ece7bb5e0ae3da Mon Sep 17 00:00:00 2001 From: Chandler Carruth Date: Fri, 3 Oct 2014 10:11:39 +0000 Subject: [PATCH] [x86] Unbreak SSE1 with the new vector shuffle lowering. We can't widen element types to form illegal vector types. I've added a special SSE1 test case here that makes sure we don't break this going forward. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218974 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 12 +- test/CodeGen/X86/vector-shuffle-sse1.ll | 235 ++++++++++++++++++++++++ 2 files changed, 243 insertions(+), 4 deletions(-) create mode 100644 test/CodeGen/X86/vector-shuffle-sse1.ll diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 9089d138ddc..bbb06aea233 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -10263,10 +10263,14 @@ static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget, ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2) : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2); MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2); - V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); - V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2); - return DAG.getNode(ISD::BITCAST, dl, VT, - DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask)); + // Make sure that the new vector type is legal. For example, v2f64 isn't + // legal on SSE1. + if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) { + V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); + V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2); + return DAG.getNode(ISD::BITCAST, dl, VT, + DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask)); + } } int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0; diff --git a/test/CodeGen/X86/vector-shuffle-sse1.ll b/test/CodeGen/X86/vector-shuffle-sse1.ll new file mode 100644 index 00000000000..43daf85b875 --- /dev/null +++ b/test/CodeGen/X86/vector-shuffle-sse1.ll @@ -0,0 +1,235 @@ +; RUN: llc < %s -mcpu=x86-64 -mattr=-sse2 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=SSE1 + +target triple = "x86_64-unknown-unknown" + +define <4 x float> @shuffle_v4f32_0001(<4 x float> %a, <4 x float> %b) { +; SSE1-LABEL: shuffle_v4f32_0001: +; SSE1: # BB#0: +; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,1] +; SSE1-NEXT: retq + %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + ret <4 x float> %shuffle +} +define <4 x float> @shuffle_v4f32_0020(<4 x float> %a, <4 x float> %b) { +; SSE1-LABEL: shuffle_v4f32_0020: +; SSE1: # BB#0: +; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,2,0] +; SSE1-NEXT: retq + %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + ret <4 x float> %shuffle +} +define <4 x float> @shuffle_v4f32_0300(<4 x float> %a, <4 x float> %b) { +; SSE1-LABEL: shuffle_v4f32_0300: +; SSE1: # BB#0: +; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3,0,0] +; SSE1-NEXT: retq + %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + ret <4 x float> %shuffle +} +define <4 x float> @shuffle_v4f32_1000(<4 x float> %a, <4 x float> %b) { +; SSE1-LABEL: shuffle_v4f32_1000: +; SSE1: # BB#0: +; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0,0,0] +; SSE1-NEXT: retq + %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + ret <4 x float> %shuffle +} +define <4 x float> @shuffle_v4f32_2200(<4 x float> %a, <4 x float> %b) { +; SSE1-LABEL: shuffle_v4f32_2200: +; SSE1: # BB#0: +; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,2,0,0] +; SSE1-NEXT: retq + %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + ret <4 x float> %shuffle +} +define <4 x float> @shuffle_v4f32_3330(<4 x float> %a, <4 x float> %b) { +; SSE1-LABEL: shuffle_v4f32_3330: +; SSE1: # BB#0: +; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,0] +; SSE1-NEXT: retq + %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + ret <4 x float> %shuffle +} +define <4 x float> @shuffle_v4f32_3210(<4 x float> %a, <4 x float> %b) { +; SSE1-LABEL: shuffle_v4f32_3210: +; SSE1: # BB#0: +; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,2,1,0] +; SSE1-NEXT: retq + %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + ret <4 x float> %shuffle +} +define <4 x float> @shuffle_v4f32_0011(<4 x float> %a, <4 x float> %b) { +; SSE1-LABEL: shuffle_v4f32_0011: +; SSE1: # BB#0: +; SSE1-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0,0,1,1] +; SSE1-NEXT: retq + %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + ret <4 x float> %shuffle +} +define <4 x float> @shuffle_v4f32_2233(<4 x float> %a, <4 x float> %b) { +; SSE1-LABEL: shuffle_v4f32_2233: +; SSE1: # BB#0: +; SSE1-NEXT: unpckhps {{.*#+}} xmm0 = xmm0[2,2,3,3] +; SSE1-NEXT: retq + %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + ret <4 x float> %shuffle +} +define <4 x float> @shuffle_v4f32_0022(<4 x float> %a, <4 x float> %b) { +; SSE1-LABEL: shuffle_v4f32_0022: +; SSE1: # BB#0: +; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,2,2] +; SSE1-NEXT: retq + %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + ret <4 x float> %shuffle +} +define <4 x float> @shuffle_v4f32_1133(<4 x float> %a, <4 x float> %b) { +; SSE1-LABEL: shuffle_v4f32_1133: +; SSE1: # BB#0: +; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,3,3] +; SSE1-NEXT: retq + %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + ret <4 x float> %shuffle +} + +define <4 x float> @shuffle_v4f32_4zzz(<4 x float> %a) { +; SSE1-LABEL: shuffle_v4f32_4zzz: +; SSE1: # BB#0: +; SSE1-NEXT: xorps %xmm1, %xmm1 +; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[1,0] +; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3] +; SSE1-NEXT: retq + %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> + ret <4 x float> %shuffle +} + +define <4 x float> @shuffle_v4f32_z4zz(<4 x float> %a) { +; SSE1-LABEL: shuffle_v4f32_z4zz: +; SSE1: # BB#0: +; SSE1-NEXT: xorps %xmm1, %xmm1 +; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[2,0] +; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[3,0] +; SSE1-NEXT: retq + %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> + ret <4 x float> %shuffle +} + +define <4 x float> @shuffle_v4f32_zz4z(<4 x float> %a) { +; SSE1-LABEL: shuffle_v4f32_zz4z: +; SSE1: # BB#0: +; SSE1-NEXT: xorps %xmm1, %xmm1 +; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0] +; SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,2] +; SSE1-NEXT: movaps %xmm1, %xmm0 +; SSE1-NEXT: retq + %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> + ret <4 x float> %shuffle +} + +define <4 x float> @shuffle_v4f32_zuu4(<4 x float> %a) { +; SSE1-LABEL: shuffle_v4f32_zuu4: +; SSE1: # BB#0: +; SSE1-NEXT: xorps %xmm1, %xmm1 +; SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0] +; SSE1-NEXT: movaps %xmm1, %xmm0 +; SSE1-NEXT: retq + %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> + ret <4 x float> %shuffle +} + +define <4 x float> @shuffle_v4f32_zzz7(<4 x float> %a) { +; SSE1-LABEL: shuffle_v4f32_zzz7: +; SSE1: # BB#0: +; SSE1-NEXT: xorps %xmm1, %xmm1 +; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0] +; SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0] +; SSE1-NEXT: movaps %xmm1, %xmm0 +; SSE1-NEXT: retq + %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> + ret <4 x float> %shuffle +} + +define <4 x float> @shuffle_v4f32_z6zz(<4 x float> %a) { +; SSE1-LABEL: shuffle_v4f32_z6zz: +; SSE1: # BB#0: +; SSE1-NEXT: xorps %xmm1, %xmm1 +; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[0,0] +; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] +; SSE1-NEXT: retq + %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> + ret <4 x float> %shuffle +} + +define <4 x float> @insert_reg_and_zero_v4f32(float %a) { +; SSE1-LABEL: insert_reg_and_zero_v4f32: +; SSE1: # BB#0: +; SSE1-NEXT: xorps %xmm1, %xmm1 +; SSE1-NEXT: movss %xmm0, %xmm1 +; SSE1-NEXT: movaps %xmm1, %xmm0 +; SSE1-NEXT: retq + %v = insertelement <4 x float> undef, float %a, i32 0 + %shuffle = shufflevector <4 x float> %v, <4 x float> zeroinitializer, <4 x i32> + ret <4 x float> %shuffle +} + +define <4 x float> @insert_mem_and_zero_v4f32(float* %ptr) { +; SSE1-LABEL: insert_mem_and_zero_v4f32: +; SSE1: # BB#0: +; SSE1-NEXT: movss (%rdi), %xmm0 +; SSE1-NEXT: retq + %a = load float* %ptr + %v = insertelement <4 x float> undef, float %a, i32 0 + %shuffle = shufflevector <4 x float> %v, <4 x float> zeroinitializer, <4 x i32> + ret <4 x float> %shuffle +} + +define <4 x float> @insert_mem_lo_v4f32(<2 x float>* %ptr, <4 x float> %b) { +; SSE1-LABEL: insert_mem_lo_v4f32: +; SSE1: # BB#0: +; SSE1-NEXT: movq (%rdi), %rax +; SSE1-NEXT: movl %eax, {{[-0-9]+}}(%rsp) +; SSE1-NEXT: shrq $32, %rax +; SSE1-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; SSE1-NEXT: movss {{[-0-9]+}}(%rsp), %xmm1 +; SSE1-NEXT: movss {{[-0-9]+}}(%rsp), %xmm2 +; SSE1-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] +; SSE1-NEXT: xorps %xmm2, %xmm2 +; SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,1] +; SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3] +; SSE1-NEXT: movaps %xmm1, %xmm0 +; SSE1-NEXT: retq + %a = load <2 x float>* %ptr + %v = shufflevector <2 x float> %a, <2 x float> undef, <4 x i32> + %shuffle = shufflevector <4 x float> %v, <4 x float> %b, <4 x i32> + ret <4 x float> %shuffle +} + +define <4 x float> @insert_mem_hi_v4f32(<2 x float>* %ptr, <4 x float> %b) { +; SSE1-LABEL: insert_mem_hi_v4f32: +; SSE1: # BB#0: +; SSE1-NEXT: movq (%rdi), %rax +; SSE1-NEXT: movl %eax, {{[-0-9]+}}(%rsp) +; SSE1-NEXT: shrq $32, %rax +; SSE1-NEXT: movl %eax, {{[-0-9]+}}(%rsp) +; SSE1-NEXT: movss {{[-0-9]+}}(%rsp), %xmm1 +; SSE1-NEXT: movss {{[-0-9]+}}(%rsp), %xmm2 +; SSE1-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] +; SSE1-NEXT: xorps %xmm2, %xmm2 +; SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,1] +; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,1] +; SSE1-NEXT: retq + %a = load <2 x float>* %ptr + %v = shufflevector <2 x float> %a, <2 x float> undef, <4 x i32> + %shuffle = shufflevector <4 x float> %v, <4 x float> %b, <4 x i32> + ret <4 x float> %shuffle +} + +define <4 x float> @shuffle_mem_v4f32_3210(<4 x float>* %ptr) { +; SSE1-LABEL: shuffle_mem_v4f32_3210: +; SSE1: # BB#0: +; SSE1-NEXT: movaps (%rdi), %xmm0 +; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,2,1,0] +; SSE1-NEXT: retq + %a = load <4 x float>* %ptr + %shuffle = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> + ret <4 x float> %shuffle +}