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Code clean up.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135954 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2011-07-25 20:18:48 +00:00
parent 8cb2d61bce
commit 54134708f5
5 changed files with 1 additions and 23 deletions
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6
lib/Target/ARM/ARM.h
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@ -29,13 +29,7 @@ class ARMBaseTargetMachine;
class FunctionPass;
class JITCodeEmitter;
class MachineInstr;
class MCCodeEmitter;
class MCInst;
class MCInstrInfo;
class MCObjectWriter;
class MCSubtargetInfo;
class TargetAsmBackend;
class formatted_raw_ostream;
FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
CodeGenOpt::Level OptLevel);

3
lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
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@ -20,9 +20,6 @@
#include "ARMMCTargetDesc.h"
#include "llvm/Support/ErrorHandling.h"
// Note that the following auto-generated files only defined enum types, and
// so are safe to include here.
namespace llvm {
// Enums corresponding to ARM condition codes

2
lib/Target/PowerPC/MCTargetDesc/PPCBaseInfo.h
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@ -22,7 +22,7 @@
namespace llvm {
/// getRegisterNumbering - Given the enum value for some register, e.g.
/// getPPCRegisterNumbering - Given the enum value for some register, e.g.
/// PPC::F14, return the number that it corresponds to (e.g. 14).
inline static unsigned getPPCRegisterNumbering(unsigned RegEnum) {
using namespace PPC;

5
lib/Target/PowerPC/PPC.h
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@ -31,12 +31,7 @@ namespace llvm {
class MachineInstr;
class AsmPrinter;
class MCInst;
class MCCodeEmitter;
class MCContext;
class MCInstrInfo;
class MCSubtargetInfo;
class TargetMachine;
class TargetAsmBackend;
FunctionPass *createPPCBranchSelectionPass();
FunctionPass *createPPCISelDag(PPCTargetMachine &TM);

8
lib/Target/X86/X86.h
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@ -25,16 +25,8 @@ namespace llvm {
class FunctionPass;
class JITCodeEmitter;
class MachineCodeEmitter;
class MCCodeEmitter;
class MCContext;
class MCInstrInfo;
class MCObjectWriter;
class MCSubtargetInfo;
class Target;
class TargetAsmBackend;
class X86TargetMachine;
class formatted_raw_ostream;
class raw_ostream;
/// createX86ISelDag - This pass converts a legalized DAG into a
/// X86-specific DAG, ready for instruction scheduling.