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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157020 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1,4 +1,4 @@
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//===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//excess
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//===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -808,7 +808,8 @@ traceCandidate(const char *Label, unsigned QID, SUnit *SU,
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}
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#endif
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/// Return true if the LHS reg pressure effect is better than RHS.
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/// pickNodeFromQueue helper that returns true if the LHS reg pressure effect is
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/// more desirable than RHS from scheduling standpoint.
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static bool compareRPDelta(const RegPressureDelta &LHS,
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const RegPressureDelta &RHS) {
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// Compare each component of pressure in decreasing order of importance
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