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R600/SI: Use VALU for i1 XOR

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213528 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2014-07-21 14:01:10 +00:00
parent ad9769a118
commit 54a2540fee
3 changed files with 12 additions and 6 deletions
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10
lib/Target/R600/SIInstructions.td
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@ -1521,6 +1521,11 @@ def V_OR_I1 : InstSI <
[(set i1:$dst, (or i1:$src0, i1:$src1))]
>;
def V_XOR_I1 : InstSI <
(outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
[(set i1:$dst, (xor i1:$src0, i1:$src1))]
>;
// SI pseudo instructions. These are used by the CFG structurizer pass
// and should be lowered to ISA instructions prior to codegen.
@ -1786,11 +1791,6 @@ let Predicates = [isSI] in {
// SOP2 Patterns
//===----------------------------------------------------------------------===//
def : Pat <
(i1 (xor i1:$src0, i1:$src1)),
(S_XOR_B64 $src0, $src1)
>;
//===----------------------------------------------------------------------===//
// SOPP Patterns
//===----------------------------------------------------------------------===//

6
lib/Target/R600/SILowerI1Copies.cpp
View File

@ -102,6 +102,12 @@ bool SILowerI1Copies::runOnMachineFunction(MachineFunction &MF) {
continue;
}
if (MI.getOpcode() == AMDGPU::V_XOR_I1) {
I1Defs.push_back(MI.getOperand(0).getReg());
MI.setDesc(TII->get(AMDGPU::V_XOR_B32_e32));
continue;
}
if (MI.getOpcode() != AMDGPU::COPY ||
!TargetRegisterInfo::isVirtualRegister(MI.getOperand(0).getReg()) ||
!TargetRegisterInfo::isVirtualRegister(MI.getOperand(1).getReg()))

2
test/CodeGen/R600/xor.ll
View File

@ -42,7 +42,7 @@ define void @xor_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in
;EG-CHECK: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], PS}}
;SI-CHECK: @xor_i1
;SI-CHECK: S_XOR_B64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
;SI-CHECK: V_XOR_B32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @xor_i1(float addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) {
%a = load float addrspace(1) * %in0