RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2025-01-20 17:03:09 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[PowerPC] Clean up -mattr=+vsx tests to always specify -mcpu

Browse Source 
We recently discovered an issue that reinforces what a good idea it is
to always specify -mcpu in our code generation tests, particularly for
-mattr=+vsx.  This patch ensures that all tests that specify
-mattr=+vsx also specify -mcpu=pwr7 or -mcpu=pwr8, as appropriate.

Some of the uses of -mattr=+vsx added recently don't make much sense
(when specified for -mtriple=powerpc-apple-darwin8 or -march=ppc32,
for example).  For cases like this I've just removed the extra VSX
test commands; there's enough coverage without them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220173 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Schmidt 2014-10-19 21:29:21 +00:00
parent 1d142d4d47
commit 551a3d7b56
11 changed files with 8 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
test/CodeGen/PowerPC/2007-09-08-unaligned.ll
View File

@ -2,10 +2,6 @@
; RUN: llc -mattr=-vsx < %s | grep stfs | count 1
; RUN: llc -mattr=-vsx < %s | grep lfd | count 2
; RUN: llc -mattr=-vsx < %s | grep lfs | count 2
; RUN: llc -mattr=+vsx < %s | grep stxsdx | count 3
; RUN: llc -mattr=+vsx < %s | grep stfs | count 1
; RUN: llc -mattr=+vsx < %s | grep lxsdx | count 2
; RUN: llc -mattr=+vsx < %s | grep lfs | count 2
; ModuleID = 'foo.c'
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc-apple-darwin8"

4
test/CodeGen/PowerPC/2012-10-12-bitcast.ll
View File

@ -1,5 +1,5 @@
; RUN: llc -mattr=-vsx -mattr=+altivec < %s | FileCheck %s
; RUN: llc -mattr=+vsx -mattr=+altivec < %s | FileCheck -check-prefix=CHECK-VSX %s
; RUN: llc -mattr=-vsx -mattr=+altivec -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -mattr=+vsx -mattr=+altivec -mcpu=pwr7 < %s | FileCheck -check-prefix=CHECK-VSX %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"

6
test/CodeGen/PowerPC/buildvec_canonicalize.ll
View File

@ -1,5 +1,4 @@
; RUN: llc < %s -mattr=-vsx -march=ppc32 -mattr=+altivec --enable-unsafe-fp-math | FileCheck %s
; RUN: llc < %s -mattr=+vsx -march=ppc32 -mattr=+altivec --enable-unsafe-fp-math | FileCheck -check-prefix=CHECK-VSX %s
define void @VXOR(<4 x float>* %P1, <4 x i32>* %P2, <4 x float>* %P3) {
%tmp = load <4 x float>* %P3 ; <<4 x float>> [#uses=1]
@ -15,9 +14,6 @@ define void @VXOR(<4 x float>* %P1, <4 x i32>* %P2, <4 x float>* %P3) {
; CHECK: @VXOR
; CHECK: vsplti
; CHECK: vxor
; CHECK-VSX: @VXOR
; CHECK-VSX: vxor
; CHECK-VSX: xvmulsp
define void @VSPLTI(<4 x i32>* %P2, <8 x i16>* %P3) {
store <4 x i32> bitcast (<16 x i8> < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > to <4 x i32>), <4 x i32>* %P2
@ -26,5 +22,3 @@ define void @VSPLTI(<4 x i32>* %P2, <8 x i16>* %P3) {
}
; CHECK: @VSPLTI
; CHECK: vsplti
; CHECK-VSX: @VSPLTI
; CHECK-VSX: vsplti

1
test/CodeGen/PowerPC/fabs.ll
View File

@ -1,5 +1,4 @@
; RUN: llc < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin | grep "fabs f1, f1"
; RUN: llc < %s -mattr=+vsx -march=ppc32 -mtriple=powerpc-apple-darwin | grep "xsabsdp f1, f1"
define double @fabs(double %f) {
entry:

1
test/CodeGen/PowerPC/fnabs.ll
View File

@ -1,5 +1,4 @@
; RUN: llc < %s -mattr=-vsx -march=ppc32 | grep fnabs
; RUN: llc < %s -mattr=+vsx -march=ppc32 | grep xsnabsdp
declare double @fabs(double)

1
test/CodeGen/PowerPC/fp-branch.ll
View File

@ -1,5 +1,4 @@
; RUN: llc < %s -mattr=-vsx -march=ppc32 | grep fcmp | count 1
; RUN: llc < %s -mattr=+vsx -march=ppc32 | grep xscmpudp | count 1
declare i1 @llvm.isunordered.f64(double, double)

1
test/CodeGen/PowerPC/fp_to_uint.ll
View File

@ -1,5 +1,4 @@
; RUN: llc < %s -mattr=-vsx -march=ppc32 | grep fctiwz | count 1
; RUN: llc < %s -mattr=+vsx -march=ppc32 | grep xscvdpsxws | count 1
define i16 @foo(float %a) {

4
test/CodeGen/PowerPC/i64_fp.ll
View File

@ -17,10 +17,6 @@
; RUN: not grep fcfid
; RUN: llc < %s -mattr=-vsx -march=ppc32 -mcpu=g4 | \
; RUN: not grep fctidz
; RUN: llc < %s -mattr=+vsx -march=ppc32 -mattr=+64bit | \
; RUN: grep xscvdpsxds
; RUN: llc < %s -mattr=+vsx -march=ppc32 -mattr=+64bit | \
; RUN: grep xscvsxddp
define double @X(double %Y) {
%A = fptosi double %Y to i64 ; <i64> [#uses=1]

3
test/CodeGen/PowerPC/unsafe-math.ll
View File

@ -1,9 +1,6 @@
; RUN: llc < %s -mattr=-vsx -march=ppc32 | grep fmul | count 2
; RUN: llc < %s -mattr=-vsx -march=ppc32 -enable-unsafe-fp-math | \
; RUN: grep fmul | count 1
; RUN: llc < %s -mattr=+vsx -march=ppc32 | grep xsmuldp | count 2
; RUN: llc < %s -mattr=+vsx -march=ppc32 -enable-unsafe-fp-math | \
; RUN: grep xsmuldp | count 1
define double @foo(double %X) nounwind {
%tmp1 = fmul double %X, 1.23

9
test/CodeGen/PowerPC/vec_mul.ll
View File

@ -1,9 +1,8 @@
; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -march=ppc32 -mattr=+altivec -mattr=-vsx | FileCheck %s
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=-vsx | FileCheck %s
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=-vsx | FileCheck %s -check-prefix=CHECK-LE
; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -march=ppc32 -mattr=+altivec -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=+vsx | FileCheck %s -check-prefix=CHECK-LE-VSX
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=-vsx -mcpu=pwr7 | FileCheck %s
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=-vsx -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-LE
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=+vsx -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-VSX
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=+vsx -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-LE-VSX
define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) {
%tmp = load <4 x i32>* %X ; <<4 x i32>> [#uses=1]

5
test/CodeGen/PowerPC/vrspill.ll
View File

@ -1,7 +1,6 @@
; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -verify-machineinstrs -fast-isel=false < %s | FileCheck %s
; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -mattr=+vsx -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK-VSX %s
; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=+vsx -verify-machineinstrs -fast-isel=false < %s | FileCheck -check-prefix=CHECK-VSX %s
; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -verify-machineinstrs -fast-isel=false -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=+vsx -verify-machineinstrs -fast-isel=false -mcpu=pwr7 < %s | FileCheck -check-prefix=CHECK-VSX %s
; This verifies that we generate correct spill/reload code for vector regs.