From 55474c1f67319809e27f3be6f94cc8dc77904868 Mon Sep 17 00:00:00 2001 From: Ulrich Weigand Date: Mon, 14 Mar 2016 13:50:03 +0000 Subject: [PATCH] [SystemZ] Avoid LER on z13 due to partial register dependencies On the z13, it turns out to be more efficient to access a full floating-point register than just the upper half (as done e.g. by the LE and LER instructions). Current code already takes this into account when loading from memory by using the LDE instruction in place of LE. However, we still generate LER, which shows the same performance issues as LE in certain circumstances. This patch changes the back-end to emit LDR instead of LER to implement FP32 register-to-register copies on z13. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263431 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/SystemZ/SystemZInstrFP.td | 4 +++ lib/Target/SystemZ/SystemZInstrInfo.cpp | 3 ++- test/CodeGen/SystemZ/fp-move-01.ll | 1 - test/CodeGen/SystemZ/fp-move-12.ll | 33 +++++++++++++++++++++++++ test/CodeGen/SystemZ/vec-sub-01.ll | 2 +- 5 files changed, 40 insertions(+), 3 deletions(-) create mode 100644 test/CodeGen/SystemZ/fp-move-12.ll diff --git a/lib/Target/SystemZ/SystemZInstrFP.td b/lib/Target/SystemZ/SystemZInstrFP.td index 0cb267290cc..82dccd3878b 100644 --- a/lib/Target/SystemZ/SystemZInstrFP.td +++ b/lib/Target/SystemZ/SystemZInstrFP.td @@ -37,6 +37,10 @@ let hasSideEffects = 0 in { def LER : UnaryRR <"le", 0x38, null_frag, FP32, FP32>; def LDR : UnaryRR <"ld", 0x28, null_frag, FP64, FP64>; def LXR : UnaryRRE<"lx", 0xB365, null_frag, FP128, FP128>; + + // For z13 we prefer LDR over LER to avoid partial register dependencies. + let isCodeGenOnly = 1 in + def LDR32 : UnaryRR<"ld", 0x28, null_frag, FP32, FP32>; } // Moves between two floating-point registers that also set the condition diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp index 39c43739e1c..8dadd017770 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -572,7 +572,8 @@ void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB, if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg)) Opcode = SystemZ::LGR; else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg)) - Opcode = SystemZ::LER; + // For z13 we prefer LDR over LER to avoid partial register dependencies. + Opcode = STI.hasVector() ? SystemZ::LDR32 : SystemZ::LER; else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg)) Opcode = SystemZ::LDR; else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg)) diff --git a/test/CodeGen/SystemZ/fp-move-01.ll b/test/CodeGen/SystemZ/fp-move-01.ll index 843b1b6a6e6..55c09e5d779 100644 --- a/test/CodeGen/SystemZ/fp-move-01.ll +++ b/test/CodeGen/SystemZ/fp-move-01.ll @@ -1,7 +1,6 @@ ; Test moves between FPRs. ; ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s ; Test f32 moves. define float @f1(float %a, float %b) { diff --git a/test/CodeGen/SystemZ/fp-move-12.ll b/test/CodeGen/SystemZ/fp-move-12.ll new file mode 100644 index 00000000000..131f7c374ca --- /dev/null +++ b/test/CodeGen/SystemZ/fp-move-12.ll @@ -0,0 +1,33 @@ +; Test moves between FPRs on z13. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test that we use LDR instead of LER. +define float @f1(float %a, float %b) { +; CHECK-LABEL: f1: +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + ret float %b +} + +; Test f64 moves. +define double @f2(double %a, double %b) { +; CHECK-LABEL: f2: +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + ret double %b +} + +; Test f128 moves. Since f128s are passed by reference, we need to force +; a copy by other means. +define void @f3(fp128 *%x) { +; CHECK-LABEL: f3: +; CHECK: lxr +; CHECK: axbr +; CHECK: br %r14 + %val = load volatile fp128 , fp128 *%x + %sum = fadd fp128 %val, %val + store volatile fp128 %sum, fp128 *%x + store volatile fp128 %val, fp128 *%x + ret void +} diff --git a/test/CodeGen/SystemZ/vec-sub-01.ll b/test/CodeGen/SystemZ/vec-sub-01.ll index 4afad8bef65..9829bd02433 100644 --- a/test/CodeGen/SystemZ/vec-sub-01.ll +++ b/test/CodeGen/SystemZ/vec-sub-01.ll @@ -52,7 +52,7 @@ define <4 x float> @f5(<4 x float> %val1, <4 x float> %val2) { ; CHECK-DAG: vrepf %v[[C2:[0-5]]], %v[[A2]], 2 ; CHECK-DAG: vrepf %v[[D1:[0-5]]], %v[[A1]], 3 ; CHECK-DAG: vrepf %v[[D2:[0-5]]], %v[[A2]], 3 -; CHECK-DAG: ler %f[[A1copy:[0-5]]], %f[[A1]] +; CHECK-DAG: ldr %f[[A1copy:[0-5]]], %f[[A1]] ; CHECK-DAG: sebr %f[[A1copy]], %f[[A2]] ; CHECK-DAG: sebr %f[[B1]], %f[[B2]] ; CHECK-DAG: sebr %f[[C1]], %f[[C2]]