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Reduce the size of MCRelaxableFragment.

Browse Source 
MCRelaxableFragment previously kept a copy of MCSubtargetInfo and
MCInst to enable re-encoding the MCInst later during relaxation. A copy
of MCSubtargetInfo (instead of a reference or pointer) was needed
because the feature bits could be modified by the parser.

This commit replaces the MCSubtargetInfo copy in MCRelaxableFragment
with a constant reference to MCSubtargetInfo. The copies of
MCSubtargetInfo are kept in MCContext, and the target parsers are now
responsible for asking MCContext to provide a copy whenever the feature
bits of MCSubtargetInfo have to be toggled.
 
With this patch, I saw a 4% reduction in peak memory usage when I
compiled verify-uselistorder.lto.bc using llc.

rdar://problem/21736951

Differential Revision: http://reviews.llvm.org/D14346


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253127 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2015-11-14 06:35:56 +00:00
parent 09dcb16d13
commit 55c0268714
19 changed files with 76 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
include/llvm/MC/MCAssembler.h
View File

@ -266,9 +266,7 @@ class MCRelaxableFragment : public MCEncodedFragmentWithFixups<8, 1> {
MCInst Inst;
/// STI - The MCSubtargetInfo in effect when the instruction was encoded.
/// Keep a copy instead of a reference to make sure that updates to STI
/// in the assembler are not seen here.
const MCSubtargetInfo STI;
const MCSubtargetInfo &STI;
public:
MCRelaxableFragment(const MCInst &Inst, const MCSubtargetInfo &STI,

6
include/llvm/MC/MCContext.h
View File

@ -17,6 +17,7 @@
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/Twine.h"
#include "llvm/MC/MCDwarf.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/SectionKind.h"
#include "llvm/Support/Allocator.h"
#include "llvm/Support/Compiler.h"
@ -207,6 +208,8 @@ namespace llvm {
std::map<COFFSectionKey, MCSectionCOFF *> COFFUniquingMap;
StringMap<bool> ELFRelSecNames;
SpecificBumpPtrAllocator<MCSubtargetInfo> MCSubtargetAllocator;
/// Do automatic reset in destructor
bool AutoReset;
@ -380,6 +383,9 @@ namespace llvm {
MCSectionCOFF *getAssociativeCOFFSection(MCSectionCOFF *Sec,
const MCSymbol *KeySym);
// Create and save a copy of STI and return a reference to the copy.
MCSubtargetInfo &getSubtargetCopy(const MCSubtargetInfo &STI);
/// @}
/// \name Dwarf Management

7
include/llvm/MC/MCTargetAsmParser.h
View File

@ -93,7 +93,10 @@ private:
MCTargetAsmParser(const MCTargetAsmParser &) = delete;
void operator=(const MCTargetAsmParser &) = delete;
protected: // Can only create subclasses.
MCTargetAsmParser(MCTargetOptions const &, MCSubtargetInfo &STI);
MCTargetAsmParser(MCTargetOptions const &, const MCSubtargetInfo &STI);
/// Create a copy of STI and return a non-const reference to it.
MCSubtargetInfo &copySTI();
/// AvailableFeatures - The current set of available features.
uint64_t AvailableFeatures;
@ -109,7 +112,7 @@ protected: // Can only create subclasses.
MCTargetOptions MCOptions;
/// Current STI.
MCSubtargetInfo &STI;
const MCSubtargetInfo *STI;
public:
~MCTargetAsmParser() override;

8
include/llvm/Support/TargetRegistry.h
View File

@ -115,7 +115,7 @@ public:
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(
MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII,
const MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII,
const MCTargetOptions &Options);
typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T,
const MCSubtargetInfo &STI,
@ -382,7 +382,7 @@ public:
///
/// \param Parser The target independent parser implementation to use for
/// parsing and lexing.
MCTargetAsmParser *createMCAsmParser(MCSubtargetInfo &STI,
MCTargetAsmParser *createMCAsmParser(const MCSubtargetInfo &STI,
MCAsmParser &Parser,
const MCInstrInfo &MII,
const MCTargetOptions &Options) const {
@ -1133,8 +1133,8 @@ template <class MCAsmParserImpl> struct RegisterMCAsmParser {
}
private:
static MCTargetAsmParser *Allocator(MCSubtargetInfo &STI, MCAsmParser &P,
const MCInstrInfo &MII,
static MCTargetAsmParser *Allocator(const MCSubtargetInfo &STI,
MCAsmParser &P, const MCInstrInfo &MII,
const MCTargetOptions &Options) {
return new MCAsmParserImpl(STI, P, MII, Options);
}

3
lib/CodeGen/AsmPrinter/AsmPrinter.cpp
View File

@ -235,7 +235,8 @@ bool AsmPrinter::doInitialization(Module &M) {
TM.getTargetFeatureString()));
OutStreamer->AddComment("Start of file scope inline assembly");
OutStreamer->AddBlankLine();
EmitInlineAsm(M.getModuleInlineAsm()+"\n", *STI, TM.Options.MCOptions);
EmitInlineAsm(M.getModuleInlineAsm()+"\n",
OutContext.getSubtargetCopy(*STI), TM.Options.MCOptions);
OutStreamer->AddComment("End of file scope inline assembly");
OutStreamer->AddBlankLine();
}

10
lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
View File

@ -127,19 +127,13 @@ void AsmPrinter::EmitInlineAsm(StringRef Str, const MCSubtargetInfo &STI,
std::unique_ptr<MCAsmParser> Parser(
createMCAsmParser(SrcMgr, OutContext, *OutStreamer, *MAI));
// Create a temporary copy of the original STI because the parser may modify
// it. For example, when switching between arm and thumb mode. If the target
// needs to emit code to return to the original state it can do so in
// emitInlineAsmEnd().
MCSubtargetInfo TmpSTI = STI;
// We create a new MCInstrInfo here since we might be at the module level
// and not have a MachineFunction to initialize the TargetInstrInfo from and
// we only need MCInstrInfo for asm parsing. We create one unconditionally
// because it's not subtarget dependent.
std::unique_ptr<MCInstrInfo> MII(TM.getTarget().createMCInstrInfo());
std::unique_ptr<MCTargetAsmParser> TAP(TM.getTarget().createMCAsmParser(
TmpSTI, *Parser, *MII, MCOptions));
STI, *Parser, *MII, MCOptions));
if (!TAP)
report_fatal_error("Inline asm not supported by this streamer because"
" we don't have an asm parser for this target\n");
@ -154,7 +148,7 @@ void AsmPrinter::EmitInlineAsm(StringRef Str, const MCSubtargetInfo &STI,
// Don't implicitly switch to the text section before the asm.
int Res = Parser->Run(/*NoInitialTextSection*/ true,
/*NoFinalize*/ true);
emitInlineAsmEnd(STI, &TmpSTI);
emitInlineAsmEnd(STI, &TAP->getSTI());
if (Res && !HasDiagHandler)
report_fatal_error("Error parsing inline asm\n");
}

5
lib/MC/MCContext.cpp
View File

@ -78,6 +78,7 @@ void MCContext::reset() {
ELFAllocator.DestroyAll();
MachOAllocator.DestroyAll();
MCSubtargetAllocator.DestroyAll();
UsedNames.clear();
Symbols.clear();
SectionSymbols.clear();
@ -439,6 +440,10 @@ MCSectionCOFF *MCContext::getAssociativeCOFFSection(MCSectionCOFF *Sec,
COFF::IMAGE_COMDAT_SELECT_ASSOCIATIVE);
}
MCSubtargetInfo &MCContext::getSubtargetCopy(const MCSubtargetInfo &STI) {
return *new (MCSubtargetAllocator.Allocate()) MCSubtargetInfo(STI);
}
//===----------------------------------------------------------------------===//
// Dwarf Management
//===----------------------------------------------------------------------===//

14
lib/MC/MCParser/MCTargetAsmParser.cpp
View File

@ -12,15 +12,21 @@
using namespace llvm;
MCTargetAsmParser::MCTargetAsmParser(MCTargetOptions const &MCOptions,
MCSubtargetInfo &STI)
const MCSubtargetInfo &STI)
: AvailableFeatures(0), ParsingInlineAsm(false), MCOptions(MCOptions),
STI(STI)
STI(&STI)
{
}
MCTargetAsmParser::~MCTargetAsmParser() {
}
const MCSubtargetInfo &MCTargetAsmParser::getSTI() const {
return STI;
MCSubtargetInfo &MCTargetAsmParser::copySTI() {
MCSubtargetInfo &STICopy = getContext().getSubtargetCopy(getSTI());
STI = &STICopy;
return STICopy;
}
const MCSubtargetInfo &MCTargetAsmParser::getSTI() const {
return *STI;
}

2
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
View File

@ -114,7 +114,7 @@ public:
#define GET_OPERAND_DIAGNOSTIC_TYPES
#include "AArch64GenAsmMatcher.inc"
};
AArch64AsmParser(MCSubtargetInfo &STI, MCAsmParser &Parser,
AArch64AsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
const MCInstrInfo &MII, const MCTargetOptions &Options)
: MCTargetAsmParser(Options, STI) {
MCAsmParserExtension::Initialize(Parser);

6
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
View File

@ -364,14 +364,16 @@ public:
Match_PreferE32 = FIRST_TARGET_MATCH_RESULT_TY
};
AMDGPUAsmParser(MCSubtargetInfo &STI, MCAsmParser &_Parser,
AMDGPUAsmParser(const MCSubtargetInfo &STI, MCAsmParser &_Parser,
const MCInstrInfo &MII,
const MCTargetOptions &Options)
: MCTargetAsmParser(Options, STI), MII(MII), Parser(_Parser),
ForcedEncodingSize(0) {
MCAsmParserExtension::Initialize(Parser);
if (getSTI().getFeatureBits().none()) {
// Set default features.
STI.ToggleFeature("SOUTHERN_ISLANDS");
copySTI().ToggleFeature("SOUTHERN_ISLANDS");
}
setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));

7
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -283,6 +283,7 @@ class ARMAsmParser : public MCTargetAsmParser {
}
void SwitchMode() {
MCSubtargetInfo &STI = copySTI();
uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
setAvailableFeatures(FB);
}
@ -348,7 +349,7 @@ public:
};
ARMAsmParser(MCSubtargetInfo &STI, MCAsmParser &Parser,
ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
const MCInstrInfo &MII, const MCTargetOptions &Options)
: MCTargetAsmParser(Options, STI), MII(MII), UC(Parser) {
MCAsmParserExtension::Initialize(Parser);
@ -9038,6 +9039,7 @@ bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
}
Triple T;
MCSubtargetInfo &STI = copySTI();
STI.setDefaultFeatures(T.getARMCPUForArch(Arch));
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
@ -9170,6 +9172,7 @@ bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
return false;
}
MCSubtargetInfo &STI = copySTI();
STI.setDefaultFeatures(CPU);
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
@ -9188,6 +9191,7 @@ bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
return false;
}
MCSubtargetInfo &STI = copySTI();
for (auto Feature : Features)
STI.ApplyFeatureFlag(Feature);
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
@ -9968,6 +9972,7 @@ bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
return false;
}
MCSubtargetInfo &STI = copySTI();
FeatureBitset ToggleFeatures = EnableFeature
? (~STI.getFeatureBits() & Extension.Features)
: ( STI.getFeatureBits() & Extension.Features);

2
lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
View File

@ -133,7 +133,7 @@ class HexagonAsmParser : public MCTargetAsmParser {
/// }
public:
HexagonAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
HexagonAsmParser(const MCSubtargetInfo &_STI, MCAsmParser &_Parser,
const MCInstrInfo &MII, const MCTargetOptions &Options)
: MCTargetAsmParser(Options, _STI), Parser(_Parser),
MCII (MII), MCB(HexagonMCInstrInfo::createBundle()), InBrackets(false) {

7
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -346,6 +346,7 @@ class MipsAsmParser : public MCTargetAsmParser {
// FeatureMipsGP64 | FeatureMips1)
// Clearing Mips3 is equivalent to clear (FeatureMips3 | FeatureMips4).
void selectArch(StringRef ArchFeature) {
MCSubtargetInfo &STI = copySTI();
FeatureBitset FeatureBits = STI.getFeatureBits();
FeatureBits &= ~MipsAssemblerOptions::AllArchRelatedMask;
STI.setFeatureBits(FeatureBits);
@ -356,6 +357,7 @@ class MipsAsmParser : public MCTargetAsmParser {
void setFeatureBits(uint64_t Feature, StringRef FeatureString) {
if (!(getSTI().getFeatureBits()[Feature])) {
MCSubtargetInfo &STI = copySTI();
setAvailableFeatures(
ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
@ -364,6 +366,7 @@ class MipsAsmParser : public MCTargetAsmParser {
void clearFeatureBits(uint64_t Feature, StringRef FeatureString) {
if (getSTI().getFeatureBits()[Feature]) {
MCSubtargetInfo &STI = copySTI();
setAvailableFeatures(
ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
@ -388,7 +391,7 @@ public:
#undef GET_OPERAND_DIAGNOSTIC_TYPES
};
MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
MipsAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
const MCInstrInfo &MII, const MCTargetOptions &Options)
: MCTargetAsmParser(Options, sti),
ABI(MipsABIInfo::computeTargetABI(Triple(sti.getTargetTriple()),
@ -4746,6 +4749,7 @@ bool MipsAsmParser::parseSetPopDirective() {
if (AssemblerOptions.size() == 2)
return reportParseError(Loc, ".set pop with no .set push");
MCSubtargetInfo &STI = copySTI();
AssemblerOptions.pop_back();
setAvailableFeatures(
ComputeAvailableFeatures(AssemblerOptions.back()->getFeatures()));
@ -4819,6 +4823,7 @@ bool MipsAsmParser::parseSetMips0Directive() {
return reportParseError("unexpected token, expected end of statement");
// Reset assembler options to their initial values.
MCSubtargetInfo &STI = copySTI();
setAvailableFeatures(
ComputeAvailableFeatures(AssemblerOptions.front()->getFeatures()));
STI.setFeatureBits(AssemblerOptions.front()->getFeatures());

2
lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
View File

@ -290,7 +290,7 @@ class PPCAsmParser : public MCTargetAsmParser {
public:
PPCAsmParser(MCSubtargetInfo &STI, MCAsmParser &,
PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &,
const MCInstrInfo &MII, const MCTargetOptions &Options)
: MCTargetAsmParser(Options, STI), MII(MII) {
// Check for 64-bit vs. 32-bit pointer mode.

2
lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
View File

@ -88,7 +88,7 @@ class SparcAsmParser : public MCTargetAsmParser {
SmallVectorImpl<MCInst> &Instructions);
public:
SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
SparcAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
const MCInstrInfo &MII,
const MCTargetOptions &Options)
: MCTargetAsmParser(Options, sti), Parser(parser) {

2
lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
View File

@ -385,7 +385,7 @@ private:
bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
public:
SystemZAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
const MCInstrInfo &MII,
const MCTargetOptions &Options)
: MCTargetAsmParser(Options, sti), Parser(parser) {

24
lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
View File

@ -182,7 +182,7 @@ public:
std::vector<unsigned> BusyRegs;
};
X86AddressSanitizer(const MCSubtargetInfo &STI)
X86AddressSanitizer(const MCSubtargetInfo *&STI)
: X86AsmInstrumentation(STI), RepPrefix(false), OrigSPOffset(0) {}
~X86AddressSanitizer() override {}
@ -261,13 +261,13 @@ protected:
MCContext &Ctx, int64_t *Residue);
bool is64BitMode() const {
return STI.getFeatureBits()[X86::Mode64Bit];
return STI->getFeatureBits()[X86::Mode64Bit];
}
bool is32BitMode() const {
return STI.getFeatureBits()[X86::Mode32Bit];
return STI->getFeatureBits()[X86::Mode32Bit];
}
bool is16BitMode() const {
return STI.getFeatureBits()[X86::Mode16Bit];
return STI->getFeatureBits()[X86::Mode16Bit];
}
unsigned getPointerWidth() {
@ -503,7 +503,7 @@ class X86AddressSanitizer32 : public X86AddressSanitizer {
public:
static const long kShadowOffset = 0x20000000;
X86AddressSanitizer32(const MCSubtargetInfo &STI)
X86AddressSanitizer32(const MCSubtargetInfo *&STI)
: X86AddressSanitizer(STI) {}
~X86AddressSanitizer32() override {}
@ -760,7 +760,7 @@ class X86AddressSanitizer64 : public X86AddressSanitizer {
public:
static const long kShadowOffset = 0x7fff8000;
X86AddressSanitizer64(const MCSubtargetInfo &STI)
X86AddressSanitizer64(const MCSubtargetInfo *&STI)
: X86AddressSanitizer(STI) {}
~X86AddressSanitizer64() override {}
@ -1030,7 +1030,7 @@ void X86AddressSanitizer64::InstrumentMOVSImpl(unsigned AccessSize,
} // End anonymous namespace
X86AsmInstrumentation::X86AsmInstrumentation(const MCSubtargetInfo &STI)
X86AsmInstrumentation::X86AsmInstrumentation(const MCSubtargetInfo *&STI)
: STI(STI), InitialFrameReg(0) {}
X86AsmInstrumentation::~X86AsmInstrumentation() {}
@ -1043,7 +1043,7 @@ void X86AsmInstrumentation::InstrumentAndEmitInstruction(
void X86AsmInstrumentation::EmitInstruction(MCStreamer &Out,
const MCInst &Inst) {
Out.EmitInstruction(Inst, STI);
Out.EmitInstruction(Inst, *STI);
}
unsigned X86AsmInstrumentation::GetFrameRegGeneric(const MCContext &Ctx,
@ -1067,14 +1067,14 @@ unsigned X86AsmInstrumentation::GetFrameRegGeneric(const MCContext &Ctx,
X86AsmInstrumentation *
CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
const MCContext &Ctx, const MCSubtargetInfo &STI) {
Triple T(STI.getTargetTriple());
const MCContext &Ctx, const MCSubtargetInfo *&STI) {
Triple T(STI->getTargetTriple());
const bool hasCompilerRTSupport = T.isOSLinux();
if (ClAsanInstrumentAssembly && hasCompilerRTSupport &&
MCOptions.SanitizeAddress) {
if (STI.getFeatureBits()[X86::Mode32Bit] != 0)
if (STI->getFeatureBits()[X86::Mode32Bit] != 0)
return new X86AddressSanitizer32(STI);
if (STI.getFeatureBits()[X86::Mode64Bit] != 0)
if (STI->getFeatureBits()[X86::Mode64Bit] != 0)
return new X86AddressSanitizer64(STI);
}
return new X86AsmInstrumentation(STI);

10
lib/Target/X86/AsmParser/X86AsmInstrumentation.h
View File

@ -28,7 +28,8 @@ class X86AsmInstrumentation;
X86AsmInstrumentation *
CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
const MCContext &Ctx, const MCSubtargetInfo &STI);
const MCContext &Ctx,
const MCSubtargetInfo *&STI);
class X86AsmInstrumentation {
public:
@ -48,15 +49,16 @@ public:
protected:
friend X86AsmInstrumentation *
CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
const MCContext &Ctx, const MCSubtargetInfo &STI);
const MCContext &Ctx,
const MCSubtargetInfo *&STI);
X86AsmInstrumentation(const MCSubtargetInfo &STI);
X86AsmInstrumentation(const MCSubtargetInfo *&STI);
unsigned GetFrameRegGeneric(const MCContext &Ctx, MCStreamer &Out);
void EmitInstruction(MCStreamer &Out, const MCInst &Inst);
const MCSubtargetInfo &STI;
const MCSubtargetInfo *&STI;
unsigned InitialFrameReg;
};

3
lib/Target/X86/AsmParser/X86AsmParser.cpp
View File

@ -770,6 +770,7 @@ private:
return getSTI().getFeatureBits()[X86::Mode16Bit];
}
void SwitchMode(unsigned mode) {
MCSubtargetInfo &STI = copySTI();
FeatureBitset AllModes({X86::Mode64Bit, X86::Mode32Bit, X86::Mode16Bit});
FeatureBitset OldMode = STI.getFeatureBits() & AllModes;
unsigned FB = ComputeAvailableFeatures(
@ -799,7 +800,7 @@ private:
/// }
public:
X86AsmParser(MCSubtargetInfo &sti, MCAsmParser &Parser,
X86AsmParser(const MCSubtargetInfo &sti, MCAsmParser &Parser,
const MCInstrInfo &mii, const MCTargetOptions &Options)
: MCTargetAsmParser(Options, sti), MII(mii), InstInfo(nullptr) {