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https://github.com/RPCS3/llvm.git
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Use movlps, movlpd, movss and movsd specific nodes instead of pattern matching with movlp pattern fragment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112694 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
191bd64a39
commit
56098f5d26
@ -2593,7 +2593,10 @@ static bool isTargetShuffle(unsigned Opcode) {
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case X86ISD::SHUFPD:
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case X86ISD::SHUFPS:
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case X86ISD::MOVLHPS:
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case X86ISD::MOVLHPD:
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case X86ISD::MOVHLPS:
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case X86ISD::MOVLPS:
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case X86ISD::MOVLPD:
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case X86ISD::MOVSHDUP:
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case X86ISD::MOVSLDUP:
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case X86ISD::MOVSS:
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@ -2648,6 +2651,8 @@ static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
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case X86ISD::MOVLHPS:
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case X86ISD::MOVLHPD:
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case X86ISD::MOVHLPS:
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case X86ISD::MOVLPS:
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case X86ISD::MOVLPD:
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case X86ISD::MOVSS:
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case X86ISD::MOVSD:
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case X86ISD::PUNPCKLDQ:
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@ -3664,7 +3669,6 @@ SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG) {
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SDValue V = SDValue(N, 0);
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EVT VT = V.getValueType();
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unsigned Opcode = V.getOpcode();
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int NumElems = VT.getVectorNumElements();
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// Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
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if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
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@ -3673,6 +3677,7 @@ SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG) {
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if (Index < 0)
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return DAG.getUNDEF(VT.getVectorElementType());
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int NumElems = VT.getVectorNumElements();
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SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
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return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG);
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}
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@ -3698,8 +3703,9 @@ SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG) {
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if (Opcode == ISD::BIT_CONVERT) {
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V = V.getOperand(0);
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EVT SrcVT = V.getValueType();
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unsigned NumElems = VT.getVectorNumElements();
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if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != (unsigned)NumElems)
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if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
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return SDValue();
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}
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@ -5061,6 +5067,67 @@ SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
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return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
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}
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static
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SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
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SDValue V1 = Op.getOperand(0);
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SDValue V2 = Op.getOperand(1);
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EVT VT = Op.getValueType();
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unsigned NumElems = VT.getVectorNumElements();
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// Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
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// operand of these instructions is only memory, so check if there's a
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// potencial load folding here, otherwise use SHUFPS or MOVSD to match the
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// same masks.
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bool CanFoldLoad = false;
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SDValue TmpV1 = V1;
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SDValue TmpV2 = V2;
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// Trivial case, when V2 is a load.
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if (TmpV2.getOpcode() == ISD::BIT_CONVERT)
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TmpV2 = TmpV2.getOperand(0);
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if (TmpV2.getOpcode() == ISD::SCALAR_TO_VECTOR)
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TmpV2 = TmpV2.getOperand(0);
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if (MayFoldLoad(TmpV2))
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CanFoldLoad = true;
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// When V1 is a load, it can be folded later into a store in isel, example:
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// (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
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// turns into:
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// (MOVLPSmr addr:$src1, VR128:$src2)
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// So, recognize this potential and also use MOVLPS or MOVLPD
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if (TmpV1.getOpcode() == ISD::BIT_CONVERT)
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TmpV1 = TmpV1.getOperand(0);
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if (MayFoldLoad(TmpV1))
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CanFoldLoad = true;
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if (CanFoldLoad) {
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if (HasSSE2 && NumElems == 2)
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return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
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if (NumElems == 4)
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return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
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}
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
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// movl and movlp will both match v2i64, but v2i64 is never matched by
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// movl earlier because we make it strict to avoid messing with the movlp load
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// folding logic (see the code above getMOVLP call). Match it here then,
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// this is horrible, but will stay like this until we move all shuffle
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// matching to x86 specific nodes. Note that for the 1st condition all
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// types are matched with movsd.
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if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp))
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return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
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else if (HasSSE2)
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return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
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assert(VT != MVT::v4i32 && "unsupported shuffle type");
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// Invert the operand order and use SHUFPS to match it.
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return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1,
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X86::getShuffleSHUFImmediate(SVOp), DAG);
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}
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SDValue
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X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
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@ -5182,7 +5249,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
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if (X86::isMOVLPMask(SVOp))
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return Op;
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return getMOVLP(Op, dl, DAG, HasSSE2);
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}
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if (ShouldXformToMOVHLPS(SVOp) ||
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@ -8433,6 +8500,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
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case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
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case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
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case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
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case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
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case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
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case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
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case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
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@ -269,6 +269,8 @@ namespace llvm {
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MOVLHPD,
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MOVHLPS,
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MOVHLPD,
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MOVLPS,
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MOVLPD,
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MOVSD,
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MOVSS,
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UNPCKLPS,
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@ -134,9 +134,6 @@ def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
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def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
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SDTCisSameAs<0,2>, SDTCisInt<3>]>;
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def SDTShuff2OpLd : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
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SDTCisPtrTy<2>]>;
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def SDTShuff2OpLdI : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisPtrTy<1>,
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SDTCisInt<2>]>;
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@ -161,14 +158,11 @@ def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
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def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
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def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
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def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
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def X86Movhlpd : SDNode<"X86ISD::MOVHLPD", SDTShuff2Op>;
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def X86MovlpsLd : SDNode<"X86ISD::MOVLPS", SDTShuff2OpLd,
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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def X86MovlpdLd : SDNode<"X86ISD::MOVLPD", SDTShuff2OpLd,
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
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def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
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def X86Unpcklps : SDNode<"X86ISD::UNPCKLPS", SDTShuff2Op>;
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def X86Unpcklpd : SDNode<"X86ISD::UNPCKLPD", SDTShuff2Op>;
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@ -5840,9 +5840,9 @@ def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
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(MOVSDrr (v2f64 VR128:$src1),
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(EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
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def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
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(MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
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(MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
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def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
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(MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
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(MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
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// Shuffle with MOVSHDUP
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def : Pat<(v4i32 (X86Movshdup VR128:$src)),
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@ -5901,7 +5901,25 @@ def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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(PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
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// Extra patterns to match stores
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// Shuffle with MOVLPS
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def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
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(MOVLPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
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(MOVLPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(X86Movlps VR128:$src1,
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(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
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(MOVLPSrm VR128:$src1, addr:$src2)>;
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// Shuffle with MOVLPD
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def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
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(MOVLPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
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(MOVLPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2f64 (X86Movlpd VR128:$src1,
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(scalar_to_vector (loadf64 addr:$src2)))),
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(MOVLPDrm VR128:$src1, addr:$src2)>;
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// Extra patterns to match stores with MOVHPS/PD and MOVLPS/PD
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def : Pat<(store (f64 (vector_extract
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(v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))),addr:$dst),
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(MOVHPSmr addr:$dst, VR128:$src)>;
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@ -5909,3 +5927,13 @@ def : Pat<(store (f64 (vector_extract
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(v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
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(MOVHPDmr addr:$dst, VR128:$src)>;
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def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),addr:$src1),
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(MOVLPSmr addr:$src1, VR128:$src2)>;
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def : Pat<(store (v4i32 (X86Movlps
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(bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
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(MOVLPSmr addr:$src1, VR128:$src2)>;
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def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
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(MOVLPDmr addr:$src1, VR128:$src2)>;
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def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
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(MOVLPDmr addr:$src1, VR128:$src2)>;
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