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TLI: Remove DAG argument from getRegisterByName

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Replace with the MachineFunction. X86 is the only user, and only uses
it for the function. This removes one obstacle from using this in
GlobalISel. The other is the more tolerable EVT argument.

The X86 use of the function seems questionable to me. It checks hasFP,
before frame lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373292 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2019-10-01 01:44:39 +00:00
parent 914e6761d9
commit 56aa8b8eb6
22 changed files with 66 additions and 68 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
include/llvm/CodeGen/TargetLowering.h
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@ -3671,8 +3671,8 @@ public:
/// Return the register ID of the name passed in. Used by named register /// Return the register ID of the name passed in. Used by named register
/// global variables extension. There is no target-independent behaviour /// global variables extension. There is no target-independent behaviour
/// so the default action is to bail. /// so the default action is to bail.
virtual unsigned getRegisterByName(const char* RegName, EVT VT, virtual Register getRegisterByName(const char* RegName, EVT VT,
SelectionDAG &DAG) const { const MachineFunction &MF) const {
report_fatal_error("Named registers not implemented for this target"); report_fatal_error("Named registers not implemented for this target");
} }

8
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -2231,9 +2231,9 @@ void SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
SDLoc dl(Op); SDLoc dl(Op);
MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1)); MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0)); const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
unsigned Reg = Register Reg =
TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0), TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0),
*CurDAG); CurDAG->getMachineFunction());
SDValue New = CurDAG->getCopyFromReg( SDValue New = CurDAG->getCopyFromReg(
Op->getOperand(0), dl, Reg, Op->getValueType(0)); Op->getOperand(0), dl, Reg, Op->getValueType(0));
New->setNodeId(-1); New->setNodeId(-1);
@ -2245,9 +2245,9 @@ void SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
SDLoc dl(Op); SDLoc dl(Op);
MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1)); MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0)); const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(), Register Reg = TLI->getRegisterByName(RegStr->getString().data(),
Op->getOperand(2).getValueType(), Op->getOperand(2).getValueType(),
*CurDAG); CurDAG->getMachineFunction());
SDValue New = CurDAG->getCopyToReg( SDValue New = CurDAG->getCopyToReg(
Op->getOperand(0), dl, Reg, Op->getOperand(2)); Op->getOperand(0), dl, Reg, Op->getOperand(2));
New->setNodeId(-1); New->setNodeId(-1);

6
lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -5489,9 +5489,9 @@ SDValue AArch64TargetLowering::LowerSPONENTRY(SDValue Op,
// FIXME? Maybe this could be a TableGen attribute on some registers and // FIXME? Maybe this could be a TableGen attribute on some registers and
// this table could be generated automatically from RegInfo. // this table could be generated automatically from RegInfo.
unsigned AArch64TargetLowering::getRegisterByName(const char* RegName, EVT VT, Register AArch64TargetLowering::
SelectionDAG &DAG) const { getRegisterByName(const char* RegName, EVT VT, const MachineFunction &MF) const {
unsigned Reg = MatchRegisterName(RegName); Register Reg = MatchRegisterName(RegName);
if (AArch64::X1 <= Reg && Reg <= AArch64::X28) { if (AArch64::X1 <= Reg && Reg <= AArch64::X28) {
const MCRegisterInfo *MRI = Subtarget->getRegisterInfo(); const MCRegisterInfo *MRI = Subtarget->getRegisterInfo();
unsigned DwarfRegNum = MRI->getDwarfRegNum(Reg, false); unsigned DwarfRegNum = MRI->getDwarfRegNum(Reg, false);

4
lib/Target/AArch64/AArch64ISelLowering.h
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@ -707,8 +707,8 @@ private:
unsigned combineRepeatedFPDivisors() const override; unsigned combineRepeatedFPDivisors() const override;
ConstraintType getConstraintType(StringRef Constraint) const override; ConstraintType getConstraintType(StringRef Constraint) const override;
unsigned getRegisterByName(const char* RegName, EVT VT, Register getRegisterByName(const char* RegName, EVT VT,
SelectionDAG &DAG) const override; const MachineFunction &MF) const override;
/// Examine constraint string and operand type and determine a weight value. /// Examine constraint string and operand type and determine a weight value.
/// The operand object must already have been set up with the operand type. /// The operand object must already have been set up with the operand type.

8
lib/Target/AMDGPU/SIISelLowering.cpp
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@ -2971,9 +2971,9 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
IsThisReturn ? OutVals[0] : SDValue()); IsThisReturn ? OutVals[0] : SDValue());
} }
unsigned SITargetLowering::getRegisterByName(const char* RegName, EVT VT, Register SITargetLowering::getRegisterByName(const char* RegName, EVT VT,
SelectionDAG &DAG) const { const MachineFunction &MF) const {
unsigned Reg = StringSwitch<unsigned>(RegName) Register Reg = StringSwitch<Register>(RegName)
.Case("m0", AMDGPU::M0) .Case("m0", AMDGPU::M0)
.Case("exec", AMDGPU::EXEC) .Case("exec", AMDGPU::EXEC)
.Case("exec_lo", AMDGPU::EXEC_LO) .Case("exec_lo", AMDGPU::EXEC_LO)
@ -2981,7 +2981,7 @@ unsigned SITargetLowering::getRegisterByName(const char* RegName, EVT VT,
.Case("flat_scratch", AMDGPU::FLAT_SCR) .Case("flat_scratch", AMDGPU::FLAT_SCR)
.Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO) .Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO)
.Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI) .Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI)
.Default(AMDGPU::NoRegister); .Default(Register());
if (Reg == AMDGPU::NoRegister) { if (Reg == AMDGPU::NoRegister) {
report_fatal_error(Twine("invalid register name \"" report_fatal_error(Twine("invalid register name \""

4
lib/Target/AMDGPU/SIISelLowering.h
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@ -319,8 +319,8 @@ public:
SDValue LowerCall(CallLoweringInfo &CLI, SDValue LowerCall(CallLoweringInfo &CLI,
SmallVectorImpl<SDValue> &InVals) const override; SmallVectorImpl<SDValue> &InVals) const override;
unsigned getRegisterByName(const char* RegName, EVT VT, Register getRegisterByName(const char* RegName, EVT VT,
SelectionDAG &DAG) const override; const MachineFunction &MF) const override;
MachineBasicBlock *splitKillBlock(MachineInstr &MI, MachineBasicBlock *splitKillBlock(MachineInstr &MI,
MachineBasicBlock *BB) const; MachineBasicBlock *BB) const;

6
lib/Target/ARM/ARMISelLowering.cpp
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@ -5483,9 +5483,9 @@ SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
// FIXME? Maybe this could be a TableGen attribute on some registers and // FIXME? Maybe this could be a TableGen attribute on some registers and
// this table could be generated automatically from RegInfo. // this table could be generated automatically from RegInfo.
unsigned ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT, Register ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,
SelectionDAG &DAG) const { const MachineFunction &MF) const {
unsigned Reg = StringSwitch<unsigned>(RegName) Register Reg = StringSwitch<unsigned>(RegName)
.Case("sp", ARM::SP) .Case("sp", ARM::SP)
.Default(0); .Default(0);
if (Reg) if (Reg)

4
lib/Target/ARM/ARMISelLowering.h
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@ -725,8 +725,8 @@ class VectorType;
void lowerABS(SDNode *N, SmallVectorImpl<SDValue> &Results, void lowerABS(SDNode *N, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) const; SelectionDAG &DAG) const;
unsigned getRegisterByName(const char* RegName, EVT VT, Register getRegisterByName(const char* RegName, EVT VT,
SelectionDAG &DAG) const override; const MachineFunction &MF) const override;
SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
SmallVectorImpl<SDNode *> &Created) const override; SmallVectorImpl<SDNode *> &Created) const override;

7
lib/Target/AVR/AVRISelLowering.cpp
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@ -2006,10 +2006,9 @@ void AVRTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
} }
unsigned AVRTargetLowering::getRegisterByName(const char *RegName, Register AVRTargetLowering::getRegisterByName(const char *RegName, EVT VT,
EVT VT, const MachineFunction &MF) const {
SelectionDAG &DAG) const { Register Reg;
unsigned Reg;
if (VT == MVT::i8) { if (VT == MVT::i8) {
Reg = StringSwitch<unsigned>(RegName) Reg = StringSwitch<unsigned>(RegName)

4
lib/Target/AVR/AVRISelLowering.h
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@ -125,8 +125,8 @@ public:
std::vector<SDValue> &Ops, std::vector<SDValue> &Ops,
SelectionDAG &DAG) const override; SelectionDAG &DAG) const override;
unsigned getRegisterByName(const char* RegName, EVT VT, Register getRegisterByName(const char* RegName, EVT VT,
SelectionDAG &DAG) const override; const MachineFunction &MF) const override;
bool shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL) bool shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL)
const override { const override {

8
lib/Target/Hexagon/HexagonISelLowering.cpp
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@ -240,12 +240,12 @@ bool HexagonTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
return true; return true;
} }
unsigned HexagonTargetLowering::getRegisterByName(const char* RegName, EVT VT, Register HexagonTargetLowering::getRegisterByName(const char* RegName, EVT VT,
SelectionDAG &DAG) const { const MachineFunction &) const {
// Just support r19, the linux kernel uses it. // Just support r19, the linux kernel uses it.
unsigned Reg = StringSwitch<unsigned>(RegName) Register Reg = StringSwitch<Register>(RegName)
.Case("r19", Hexagon::R19) .Case("r19", Hexagon::R19)
.Default(0); .Default(Register());
if (Reg) if (Reg)
return Reg; return Reg;

4
lib/Target/Hexagon/HexagonISelLowering.h
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@ -229,8 +229,8 @@ namespace HexagonISD {
bool mayBeEmittedAsTailCall(const CallInst *CI) const override; bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
unsigned getRegisterByName(const char* RegName, EVT VT, Register getRegisterByName(const char* RegName, EVT VT,
SelectionDAG &DAG) const override; const MachineFunction &MF) const override;
/// If a physical register, this returns the register that receives the /// If a physical register, this returns the register that receives the
/// exception address on entry to an EH pad. /// exception address on entry to an EH pad.

7
lib/Target/Lanai/LanaiISelLowering.cpp
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@ -212,10 +212,11 @@ SDValue LanaiTargetLowering::LowerOperation(SDValue Op,
// Lanai Inline Assembly Support // Lanai Inline Assembly Support
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
unsigned LanaiTargetLowering::getRegisterByName(const char *RegName, EVT /*VT*/, Register LanaiTargetLowering::getRegisterByName(
SelectionDAG & /*DAG*/) const { const char *RegName, EVT /*VT*/,
const MachineFunction & /*MF*/) const {
// Only unallocatable registers should be matched here. // Only unallocatable registers should be matched here.
unsigned Reg = StringSwitch<unsigned>(RegName) Register Reg = StringSwitch<unsigned>(RegName)
.Case("pc", Lanai::PC) .Case("pc", Lanai::PC)
.Case("sp", Lanai::SP) .Case("sp", Lanai::SP)
.Case("fp", Lanai::FP) .Case("fp", Lanai::FP)

4
lib/Target/Lanai/LanaiISelLowering.h
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@ -90,8 +90,8 @@ public:
SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
unsigned getRegisterByName(const char *RegName, EVT VT, Register getRegisterByName(const char *RegName, EVT VT,
SelectionDAG &DAG) const override; const MachineFunction &MF) const override;
std::pair<unsigned, const TargetRegisterClass *> std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const override; StringRef Constraint, MVT VT) const override;

12
lib/Target/Mips/MipsISelLowering.cpp
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@ -4566,20 +4566,20 @@ MachineBasicBlock *MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI,
// FIXME? Maybe this could be a TableGen attribute on some registers and // FIXME? Maybe this could be a TableGen attribute on some registers and
// this table could be generated automatically from RegInfo. // this table could be generated automatically from RegInfo.
unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT, Register MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT,
SelectionDAG &DAG) const { const MachineFunction &MF) const {
// Named registers is expected to be fairly rare. For now, just support $28 // Named registers is expected to be fairly rare. For now, just support $28
// since the linux kernel uses it. // since the linux kernel uses it.
if (Subtarget.isGP64bit()) { if (Subtarget.isGP64bit()) {
unsigned Reg = StringSwitch<unsigned>(RegName) Register Reg = StringSwitch<Register>(RegName)
.Case("$28", Mips::GP_64) .Case("$28", Mips::GP_64)
.Default(0); .Default(Register());
if (Reg) if (Reg)
return Reg; return Reg;
} else { } else {
unsigned Reg = StringSwitch<unsigned>(RegName) Register Reg = StringSwitch<Register>(RegName)
.Case("$28", Mips::GP) .Case("$28", Mips::GP)
.Default(0); .Default(Register());
if (Reg) if (Reg)
return Reg; return Reg;
} }

4
lib/Target/Mips/MipsISelLowering.h
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@ -347,8 +347,8 @@ class TargetRegisterClass;
void HandleByVal(CCState *, unsigned &, unsigned) const override; void HandleByVal(CCState *, unsigned &, unsigned) const override;
unsigned getRegisterByName(const char* RegName, EVT VT, Register getRegisterByName(const char* RegName, EVT VT,
SelectionDAG &DAG) const override; const MachineFunction &MF) const override;
/// If a physical register, this returns the register that receives the /// If a physical register, this returns the register that receives the
/// exception address on entry to an EH pad. /// exception address on entry to an EH pad.

12
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -14513,8 +14513,8 @@ SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
// FIXME? Maybe this could be a TableGen attribute on some registers and // FIXME? Maybe this could be a TableGen attribute on some registers and
// this table could be generated automatically from RegInfo. // this table could be generated automatically from RegInfo.
unsigned PPCTargetLowering::getRegisterByName(const char* RegName, EVT VT, Register PPCTargetLowering::getRegisterByName(const char* RegName, EVT VT,
SelectionDAG &DAG) const { const MachineFunction &MF) const {
bool isPPC64 = Subtarget.isPPC64(); bool isPPC64 = Subtarget.isPPC64();
bool isDarwinABI = Subtarget.isDarwinABI(); bool isDarwinABI = Subtarget.isDarwinABI();
@ -14523,12 +14523,12 @@ unsigned PPCTargetLowering::getRegisterByName(const char* RegName, EVT VT,
report_fatal_error("Invalid register global variable type"); report_fatal_error("Invalid register global variable type");
bool is64Bit = isPPC64 && VT == MVT::i64; bool is64Bit = isPPC64 && VT == MVT::i64;
unsigned Reg = StringSwitch<unsigned>(RegName) Register Reg = StringSwitch<Register>(RegName)
.Case("r1", is64Bit ? PPC::X1 : PPC::R1) .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
.Case("r2", (isDarwinABI || isPPC64) ? 0 : PPC::R2) .Case("r2", (isDarwinABI || isPPC64) ? Register() : PPC::R2)
.Case("r13", (!isPPC64 && isDarwinABI) ? 0 : .Case("r13", (!isPPC64 && isDarwinABI) ? Register() :
(is64Bit ? PPC::X13 : PPC::R13)) (is64Bit ? PPC::X13 : PPC::R13))
.Default(0); .Default(Register());
if (Reg) if (Reg)
return Reg; return Reg;

4
lib/Target/PowerPC/PPCISelLowering.h
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@ -733,8 +733,8 @@ namespace llvm {
SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
SmallVectorImpl<SDNode *> &Created) const override; SmallVectorImpl<SDNode *> &Created) const override;
unsigned getRegisterByName(const char* RegName, EVT VT, Register getRegisterByName(const char* RegName, EVT VT,
SelectionDAG &DAG) const override; const MachineFunction &MF) const override;
void computeKnownBitsForTargetNode(const SDValue Op, void computeKnownBitsForTargetNode(const SDValue Op,
KnownBits &Known, KnownBits &Known,

6
lib/Target/Sparc/SparcISelLowering.cpp
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@ -1016,9 +1016,9 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
// FIXME? Maybe this could be a TableGen attribute on some registers and // FIXME? Maybe this could be a TableGen attribute on some registers and
// this table could be generated automatically from RegInfo. // this table could be generated automatically from RegInfo.
unsigned SparcTargetLowering::getRegisterByName(const char* RegName, EVT VT, Register SparcTargetLowering::getRegisterByName(const char* RegName, EVT VT,
SelectionDAG &DAG) const { const MachineFunction &MF) const {
unsigned Reg = StringSwitch<unsigned>(RegName) Register Reg = StringSwitch<unsigned>(RegName)
.Case("i0", SP::I0).Case("i1", SP::I1).Case("i2", SP::I2).Case("i3", SP::I3) .Case("i0", SP::I0).Case("i1", SP::I1).Case("i2", SP::I2).Case("i3", SP::I3)
.Case("i4", SP::I4).Case("i5", SP::I5).Case("i6", SP::I6).Case("i7", SP::I7) .Case("i4", SP::I4).Case("i5", SP::I5).Case("i6", SP::I6).Case("i7", SP::I7)
.Case("o0", SP::O0).Case("o1", SP::O1).Case("o2", SP::O2).Case("o3", SP::O3) .Case("o0", SP::O0).Case("o1", SP::O1).Case("o2", SP::O2).Case("o3", SP::O3)

4
lib/Target/Sparc/SparcISelLowering.h
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@ -98,8 +98,8 @@ namespace llvm {
return MVT::i32; return MVT::i32;
} }
unsigned getRegisterByName(const char* RegName, EVT VT, Register getRegisterByName(const char* RegName, EVT VT,
SelectionDAG &DAG) const override; const MachineFunction &MF) const override;
/// If a physical register, this returns the register that receives the /// If a physical register, this returns the register that receives the
/// exception address on entry to an EH pad. /// exception address on entry to an EH pad.

10
lib/Target/X86/X86ISelLowering.cpp
View File

@ -24127,12 +24127,11 @@ SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
// FIXME? Maybe this could be a TableGen attribute on some registers and // FIXME? Maybe this could be a TableGen attribute on some registers and
// this table could be generated automatically from RegInfo. // this table could be generated automatically from RegInfo.
unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT, Register X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
SelectionDAG &DAG) const { const MachineFunction &MF) const {
const TargetFrameLowering &TFI = *Subtarget.getFrameLowering(); const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();
const MachineFunction &MF = DAG.getMachineFunction();
unsigned Reg = StringSwitch<unsigned>(RegName) Register Reg = StringSwitch<unsigned>(RegName)
.Case("esp", X86::ESP) .Case("esp", X86::ESP)
.Case("rsp", X86::RSP) .Case("rsp", X86::RSP)
.Case("ebp", X86::EBP) .Case("ebp", X86::EBP)
@ -24146,8 +24145,7 @@ unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
#ifndef NDEBUG #ifndef NDEBUG
else { else {
const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
unsigned FrameReg = Register FrameReg = RegInfo->getPtrSizedFrameRegister(MF);
RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
assert((FrameReg == X86::EBP || FrameReg == X86::RBP) && assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
"Invalid Frame Register!"); "Invalid Frame Register!");
} }

4
lib/Target/X86/X86ISelLowering.h
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@ -1151,8 +1151,8 @@ namespace llvm {
return nullptr; // nothing to do, move along. return nullptr; // nothing to do, move along.
} }
unsigned getRegisterByName(const char* RegName, EVT VT, Register getRegisterByName(const char* RegName, EVT VT,
SelectionDAG &DAG) const override; const MachineFunction &MF) const override;
/// If a physical register, this returns the register that receives the /// If a physical register, this returns the register that receives the
/// exception address on entry to an EH pad. /// exception address on entry to an EH pad.