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MachineBasicBlock: Add liveins() method returning an iterator_range

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245895 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matthias Braun 2015-08-24 22:59:52 +00:00
parent b7e01a085a
commit 56dd2d0886
20 changed files with 65 additions and 91 deletions
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3
include/llvm/CodeGen/MachineBasicBlock.h
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@ -336,6 +336,9 @@ public:
livein_iterator livein_begin() const { return LiveIns.begin(); }
livein_iterator livein_end() const { return LiveIns.end(); }
bool livein_empty() const { return LiveIns.empty(); }
iterator_range<livein_iterator> liveins() const {
return make_range(livein_begin(), livein_end());
}
/// Return alignment of the basic block. The alignment is specified as
/// log2(bytes).

5
lib/CodeGen/AggressiveAntiDepBreaker.cpp
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@ -149,9 +149,8 @@ void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
// Examine the live-in regs of all successors.
for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
SE = BB->succ_end(); SI != SE; ++SI)
for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
E = (*SI)->livein_end(); I != E; ++I) {
for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
for (unsigned LI : (*SI)->liveins()) {
for (MCRegAliasIterator AI(LI, TRI, true); AI.isValid(); ++AI) {
unsigned Reg = *AI;
State->UnionGroups(Reg, 0);
KillIndices[Reg] = BB->size();

5
lib/CodeGen/CriticalAntiDepBreaker.cpp
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@ -57,9 +57,8 @@ void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
// Examine the live-in regs of all successors.
for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
SE = BB->succ_end(); SI != SE; ++SI)
for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
E = (*SI)->livein_end(); I != E; ++I) {
for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
for (unsigned LI : (*SI)->liveins()) {
for (MCRegAliasIterator AI(LI, TRI, true); AI.isValid(); ++AI) {
unsigned Reg = *AI;
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
KillIndices[Reg] = BBSize;

5
lib/CodeGen/DeadMachineInstructionElim.cpp
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@ -110,9 +110,8 @@ bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
// block.
for (MachineBasicBlock::succ_iterator S = MBB.succ_begin(),
E = MBB.succ_end(); S != E; S++)
for (MachineBasicBlock::livein_iterator LI = (*S)->livein_begin();
LI != (*S)->livein_end(); LI++)
LivePhysRegs.set(*LI);
for (unsigned LI : (*S)->liveins())
LivePhysRegs.set(LI);
// Now scan the instructions and delete dead ones, tracking physreg
// liveness as we go.

5
lib/CodeGen/ExecutionDepsFix.cpp
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@ -375,9 +375,8 @@ void ExeDepsFix::enterBasicBlock(MachineBasicBlock *MBB) {
// This is the entry block.
if (MBB->pred_empty()) {
for (MachineBasicBlock::livein_iterator i = MBB->livein_begin(),
e = MBB->livein_end(); i != e; ++i) {
for (int rx : regIndices(*i)) {
for (unsigned LI : MBB->liveins()) {
for (int rx : regIndices(LI)) {
// Treat function live-ins as if they were defined just before the first
// instruction. Usually, function arguments are set up immediately
// before the call.

5
lib/CodeGen/LiveIntervalAnalysis.cpp
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@ -305,9 +305,8 @@ void LiveIntervals::computeLiveInRegUnits() {
// Create phi-defs at Begin for all live-in registers.
SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
for (MachineBasicBlock::livein_iterator LII = MBB->livein_begin(),
LIE = MBB->livein_end(); LII != LIE; ++LII) {
for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
for (unsigned LI : MBB->liveins()) {
for (MCRegUnitIterator Units(LI, TRI); Units.isValid(); ++Units) {
unsigned Unit = *Units;
LiveRange *LR = RegUnitRanges[Unit];
if (!LR) {

4
lib/CodeGen/LivePhysRegs.cpp
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@ -128,8 +128,8 @@ void LivePhysRegs::dump() const {
/// Add live-in registers of basic block \p MBB to \p LiveRegs.
static void addLiveIns(LivePhysRegs &LiveRegs, const MachineBasicBlock &MBB) {
for (unsigned Reg : make_range(MBB.livein_begin(), MBB.livein_end()))
LiveRegs.addReg(Reg);
for (unsigned LI : MBB.liveins())
LiveRegs.addReg(LI);
}
/// Add pristine registers to the given \p LiveRegs. This function removes

15
lib/CodeGen/LiveVariables.cpp
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@ -559,11 +559,10 @@ void LiveVariables::runOnInstr(MachineInstr *MI,
void LiveVariables::runOnBlock(MachineBasicBlock *MBB, const unsigned NumRegs) {
// Mark live-in registers as live-in.
SmallVector<unsigned, 4> Defs;
for (MachineBasicBlock::livein_iterator II = MBB->livein_begin(),
EE = MBB->livein_end(); II != EE; ++II) {
assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
for (unsigned LI : MBB->liveins()) {
assert(TargetRegisterInfo::isPhysicalRegister(LI) &&
"Cannot have a live-in virtual register!");
HandlePhysRegDef(*II, nullptr, Defs);
HandlePhysRegDef(LI, nullptr, Defs);
}
// Loop over all of the instructions, processing them.
@ -601,12 +600,10 @@ void LiveVariables::runOnBlock(MachineBasicBlock *MBB, const unsigned NumRegs) {
MachineBasicBlock *SuccMBB = *SI;
if (SuccMBB->isLandingPad())
continue;
for (MachineBasicBlock::livein_iterator LI = SuccMBB->livein_begin(),
LE = SuccMBB->livein_end(); LI != LE; ++LI) {
unsigned LReg = *LI;
if (!TRI->isInAllocatableClass(LReg))
for (unsigned LI : SuccMBB->liveins()) {
if (!TRI->isInAllocatableClass(LI))
// Ignore other live-ins, e.g. those that are live into landing pads.
LiveOuts.insert(LReg);
LiveOuts.insert(LI);
}
}

8
lib/CodeGen/MIRPrinter.cpp
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@ -473,10 +473,12 @@ void MIPrinter::print(const MachineBasicBlock &MBB) {
assert(TRI && "Expected target register info");
if (!MBB.livein_empty()) {
OS.indent(2) << "liveins: ";
for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) {
if (I != MBB.livein_begin())
bool First = true;
for (unsigned LI : MBB.liveins()) {
if (!First)
OS << ", ";
printReg(*I, OS, TRI);
First = false;
printReg(LI, OS, TRI);
}
OS << "\n";
HasLineAttributes = true;

13
lib/CodeGen/MachineBasicBlock.cpp
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@ -278,8 +278,9 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
if (!livein_empty()) {
if (Indexes) OS << '\t';
OS << " Live Ins:";
for (livein_iterator I = livein_begin(),E = livein_end(); I != E; ++I)
OS << ' ' << PrintReg(*I, TRI);
for (unsigned LI : make_range(livein_begin(), livein_end())) {
OS << ' ' << PrintReg(LI, TRI);
}
OS << '\n';
}
// Print the preds of this block according to the CFG.
@ -322,8 +323,7 @@ void MachineBasicBlock::printAsOperand(raw_ostream &OS,
}
void MachineBasicBlock::removeLiveIn(unsigned Reg) {
std::vector<unsigned>::iterator I =
std::find(LiveIns.begin(), LiveIns.end(), Reg);
livein_iterator I = std::find(LiveIns.begin(), LiveIns.end(), Reg);
if (I != LiveIns.end())
LiveIns.erase(I);
}
@ -804,9 +804,8 @@ MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P) {
i->getOperand(ni+1).setMBB(NMBB);
// Inherit live-ins from the successor
for (MachineBasicBlock::livein_iterator I = Succ->livein_begin(),
E = Succ->livein_end(); I != E; ++I)
NMBB->addLiveIn(*I);
for (unsigned LI : Succ->liveins())
NMBB->addLiveIn(LI);
// Update LiveVariables.
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();

6
lib/CodeGen/MachineLICM.cpp
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@ -534,10 +534,8 @@ void MachineLICM::HoistRegionPostRA() {
// Conservatively treat live-in's as an external def.
// FIXME: That means a reload that're reused in successor block(s) will not
// be LICM'ed.
for (MachineBasicBlock::livein_iterator I = BB->livein_begin(),
E = BB->livein_end(); I != E; ++I) {
unsigned Reg = *I;
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
for (unsigned LI : BB->liveins()) {
for (MCRegAliasIterator AI(LI, TRI, true); AI.isValid(); ++AI)
PhysRegDefs.set(*AI);
}

14
lib/CodeGen/MachineVerifier.cpp
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@ -507,11 +507,8 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
if (MRI->isSSA()) {
// If this block has allocatable physical registers live-in, check that
// it is an entry block or landing pad.
for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
LE = MBB->livein_end();
LI != LE; ++LI) {
unsigned reg = *LI;
if (isAllocatable(reg) && !MBB->isLandingPad() &&
for (unsigned LI : MBB->liveins()) {
if (isAllocatable(LI) && !MBB->isLandingPad() &&
MBB != MBB->getParent()->begin()) {
report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
}
@ -680,13 +677,12 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
}
regsLive.clear();
for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
E = MBB->livein_end(); I != E; ++I) {
if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
for (unsigned LI : MBB->liveins()) {
if (!TargetRegisterInfo::isPhysicalRegister(LI)) {
report("MBB live-in list contains non-physical register", MBB);
continue;
}
for (MCSubRegIterator SubRegs(*I, TRI, /*IncludeSelf=*/true);
for (MCSubRegIterator SubRegs(LI, TRI, /*IncludeSelf=*/true);
SubRegs.isValid(); ++SubRegs)
regsLive.insert(*SubRegs);
}

7
lib/CodeGen/RegAllocFast.cpp
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@ -799,10 +799,9 @@ void RAFast::AllocateBasicBlock() {
MachineBasicBlock::iterator MII = MBB->begin();
// Add live-in registers as live.
for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
E = MBB->livein_end(); I != E; ++I)
if (MRI->isAllocatable(*I))
definePhysReg(MII, *I, regReserved);
for (unsigned LI : MBB->liveins())
if (MRI->isAllocatable(LI))
definePhysReg(MII, LI, regReserved);
SmallVector<unsigned, 8> VirtDead;
SmallVector<MachineInstr*, 32> Coalesced;

5
lib/CodeGen/RegisterScavenging.cpp
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@ -50,9 +50,8 @@ void RegScavenger::initRegState() {
return;
// Live-in registers are in use.
for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
E = MBB->livein_end(); I != E; ++I)
setRegUsed(*I);
for (unsigned LI : MBB->liveins())
setRegUsed(LI);
// Pristine CSRs are also unavailable.
const MachineFunction &MF = *MBB->getParent();

14
lib/CodeGen/ScheduleDAGInstrs.cpp
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@ -242,11 +242,9 @@ void ScheduleDAGInstrs::addSchedBarrierDeps() {
assert(Uses.empty() && "Uses in set before adding deps?");
for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
SE = BB->succ_end(); SI != SE; ++SI)
for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
E = (*SI)->livein_end(); I != E; ++I) {
unsigned Reg = *I;
if (!Uses.contains(Reg))
Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
for (unsigned LI : (*SI)->liveins()) {
if (!Uses.contains(LI))
Uses.insert(PhysRegSUOper(&ExitSU, -1, LI));
}
}
}
@ -1080,11 +1078,9 @@ void ScheduleDAGInstrs::startBlockForKills(MachineBasicBlock *BB) {
// Examine the live-in regs of all successors.
for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
SE = BB->succ_end(); SI != SE; ++SI) {
for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
E = (*SI)->livein_end(); I != E; ++I) {
unsigned Reg = *I;
for (unsigned LI : (*SI)->liveins()) {
// Repeat, for reg and all subregs.
for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
for (MCSubRegIterator SubRegs(LI, TRI, /*IncludeSelf=*/true);
SubRegs.isValid(); ++SubRegs)
LiveRegs.set(*SubRegs);
}

7
lib/CodeGen/TailDuplication.cpp
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@ -791,13 +791,12 @@ TailDuplicatePass::TailDuplicate(MachineBasicBlock *TailBB,
RS->enterBasicBlock(PredBB);
if (!PredBB->empty())
RS->forward(std::prev(PredBB->end()));
for (MachineBasicBlock::livein_iterator I = TailBB->livein_begin(),
E = TailBB->livein_end(); I != E; ++I) {
if (!RS->isRegUsed(*I, false))
for (unsigned LI : TailBB->liveins()) {
if (!RS->isRegUsed(LI, false))
// If a register is previously livein to the tail but it's not live
// at the end of predecessor BB, then it should be added to its
// livein list.
PredBB->addLiveIn(*I);
PredBB->addLiveIn(LI);
}
}

6
lib/Target/ARM/ARMFrameLowering.cpp
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@ -1885,11 +1885,9 @@ void ARMFrameLowering::adjustForSegmentedStacks(
for (int Idx = 0; Idx < NbAddedBlocks; ++Idx)
BeforePrologueRegion.insert(AddedBlocks[Idx]);
for (MachineBasicBlock::livein_iterator i = PrologueMBB.livein_begin(),
e = PrologueMBB.livein_end();
i != e; ++i) {
for (unsigned LI : PrologueMBB.liveins()) {
for (MachineBasicBlock *PredBB : BeforePrologueRegion)
PredBB->addLiveIn(*i);
PredBB->addLiveIn(LI);
}
// Remove the newly added blocks from the list, since we know

5
lib/Target/Mips/MipsDelaySlotFiller.cpp
View File

@ -355,9 +355,8 @@ void RegDefsUses::addLiveOut(const MachineBasicBlock &MBB,
for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(),
SE = MBB.succ_end(); SI != SE; ++SI)
if (*SI != &SuccBB)
for (MachineBasicBlock::livein_iterator LI = (*SI)->livein_begin(),
LE = (*SI)->livein_end(); LI != LE; ++LI)
Uses.set(*LI);
for (unsigned LI : (*SI)->liveins())
Uses.set(LI);
}
bool RegDefsUses::update(const MachineInstr &MI, unsigned Begin, unsigned End) {

8
lib/Target/X86/X86FloatingPoint.cpp
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@ -120,12 +120,10 @@ namespace {
// Return a bitmask of FP registers in block's live-in list.
static unsigned calcLiveInMask(MachineBasicBlock *MBB) {
unsigned Mask = 0;
for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
E = MBB->livein_end(); I != E; ++I) {
unsigned Reg = *I;
if (Reg < X86::FP0 || Reg > X86::FP6)
for (unsigned LI : MBB->liveins()) {
if (LI < X86::FP0 || LI > X86::FP6)
continue;
Mask |= 1 << (Reg - X86::FP0);
Mask |= 1 << (LI - X86::FP0);
}
return Mask;
}

16
lib/Target/X86/X86FrameLowering.cpp
View File

@ -1518,11 +1518,9 @@ void X86FrameLowering::adjustForSegmentedStacks(
// The MOV R10, RAX needs to be in a different block, since the RET we emit in
// allocMBB needs to be last (terminating) instruction.
for (MachineBasicBlock::livein_iterator i = PrologueMBB.livein_begin(),
e = PrologueMBB.livein_end();
i != e; i++) {
allocMBB->addLiveIn(*i);
checkMBB->addLiveIn(*i);
for (unsigned LI : PrologueMBB.liveins()) {
allocMBB->addLiveIn(LI);
checkMBB->addLiveIn(LI);
}
if (IsNested)
@ -1792,11 +1790,9 @@ void X86FrameLowering::adjustForHiPEPrologue(
MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
for (MachineBasicBlock::livein_iterator I = PrologueMBB.livein_begin(),
E = PrologueMBB.livein_end();
I != E; I++) {
stackCheckMBB->addLiveIn(*I);
incStackMBB->addLiveIn(*I);
for (unsigned LI : PrologueMBB.liveins()) {
stackCheckMBB->addLiveIn(LI);
incStackMBB->addLiveIn(LI);
}
MF.push_front(incStackMBB);