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ARM64: add more scalar patterns for usqadd & suqadd.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205204 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-03-31 15:46:26 +00:00
parent 13277a78bc
commit 576c3f709f
2 changed files with 45 additions and 9 deletions
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18
lib/Target/ARM64/ARM64InstrFormats.td
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@ -5135,15 +5135,19 @@ multiclass SIMDTwoScalarBHSD<bit U, bits<5> opc, string asm,
(!cast<Instruction>(NAME # v1i64) FPR64:$Rn)>;
}
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
multiclass SIMDTwoScalarBHSDTied<bit U, bits<5> opc, string asm,
Intrinsic OpNode> {
def v1i64 : BaseSIMDTwoScalarTied<U, 0b11, opc, FPR64, FPR64, asm,
[(set (v1i64 FPR64:$dst),
(OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn)))]>;
def v1i32 : BaseSIMDTwoScalar<U, 0b10, opc, FPR32, FPR32, asm, []>;
def v1i16 : BaseSIMDTwoScalar<U, 0b01, opc, FPR16, FPR16, asm, []>;
def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
def v1i64 : BaseSIMDTwoScalarTied<U, 0b11, opc, FPR64, FPR64, asm,
[(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn)))]>;
def v1i32 : BaseSIMDTwoScalarTied<U, 0b10, opc, FPR32, FPR32, asm,
[(set (i32 FPR32:$dst), (OpNode (i32 FPR32:$Rd), (i32 FPR32:$Rn)))]>;
def v1i16 : BaseSIMDTwoScalarTied<U, 0b01, opc, FPR16, FPR16, asm, []>;
def v1i8 : BaseSIMDTwoScalarTied<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
}
def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn))),
(!cast<Instruction>(NAME # v1i64) FPR64:$Rd, FPR64:$Rn)>;
}

36
test/CodeGen/ARM64/vqadd.ll
View File

@ -209,10 +209,26 @@ define <2 x i64> @usqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
ret <2 x i64> %tmp3
}
define i64 @usqadd_d(i64 %l, i64 %r) nounwind {
; CHECK-LABEL: usqadd_d:
; CHECK: usqadd {{d[0-9]+}}, {{d[0-9]+}}
%sum = call i64 @llvm.arm64.neon.usqadd.i64(i64 %l, i64 %r)
ret i64 %sum
}
define i32 @usqadd_s(i32 %l, i32 %r) nounwind {
; CHECK-LABEL: usqadd_s:
; CHECK: usqadd {{s[0-9]+}}, {{s[0-9]+}}
%sum = call i32 @llvm.arm64.neon.usqadd.i32(i32 %l, i32 %r)
ret i32 %sum
}
declare <8 x i8> @llvm.arm64.neon.usqadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
declare <4 x i16> @llvm.arm64.neon.usqadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
declare <2 x i32> @llvm.arm64.neon.usqadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
declare <1 x i64> @llvm.arm64.neon.usqadd.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
declare i64 @llvm.arm64.neon.usqadd.i64(i64, i64) nounwind readnone
declare i32 @llvm.arm64.neon.usqadd.i32(i32, i32) nounwind readnone
declare <16 x i8> @llvm.arm64.neon.usqadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
declare <8 x i16> @llvm.arm64.neon.usqadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
@ -282,17 +298,33 @@ define <2 x i64> @suqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
ret <2 x i64> %tmp3
}
define <1 x i64> @suqadd_d(<1 x i64> %l, <1 x i64> %r) nounwind {
; CHECK-LABEL: suqadd_d:
define <1 x i64> @suqadd_1d(<1 x i64> %l, <1 x i64> %r) nounwind {
; CHECK-LABEL: suqadd_1d:
; CHECK: suqadd {{d[0-9]+}}, {{d[0-9]+}}
%sum = call <1 x i64> @llvm.arm64.neon.suqadd.v1i64(<1 x i64> %l, <1 x i64> %r)
ret <1 x i64> %sum
}
define i64 @suqadd_d(i64 %l, i64 %r) nounwind {
; CHECK-LABEL: suqadd_d:
; CHECK: suqadd {{d[0-9]+}}, {{d[0-9]+}}
%sum = call i64 @llvm.arm64.neon.suqadd.i64(i64 %l, i64 %r)
ret i64 %sum
}
define i32 @suqadd_s(i32 %l, i32 %r) nounwind {
; CHECK-LABEL: suqadd_s:
; CHECK: suqadd {{s[0-9]+}}, {{s[0-9]+}}
%sum = call i32 @llvm.arm64.neon.suqadd.i32(i32 %l, i32 %r)
ret i32 %sum
}
declare <8 x i8> @llvm.arm64.neon.suqadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
declare <4 x i16> @llvm.arm64.neon.suqadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
declare <2 x i32> @llvm.arm64.neon.suqadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
declare <1 x i64> @llvm.arm64.neon.suqadd.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
declare i64 @llvm.arm64.neon.suqadd.i64(i64, i64) nounwind readnone
declare i32 @llvm.arm64.neon.suqadd.i32(i32, i32) nounwind readnone
declare <16 x i8> @llvm.arm64.neon.suqadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
declare <8 x i16> @llvm.arm64.neon.suqadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone