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Get rid of flags that are dead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18169 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -24,9 +24,8 @@ include "PowerPCInstrInfo.td"
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def PowerPCInstrInfo : InstrInfo {
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let PHIInst = PHI;
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let TSFlagsFields = ["ArgCount", "Arg0Type", "Arg1Type", "Arg2Type",
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"Arg3Type", "Arg4Type", "VMX", "PPC64"];
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let TSFlagsShifts = [ 0, 3, 8, 13, 18, 23, 28, 29 ];
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let TSFlagsFields = [ "VMX", "PPC64" ];
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let TSFlagsShifts = [ 0, 1 ];
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let isLittleEndianEncoding = 1;
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}
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@ -24,9 +24,8 @@ include "PowerPCInstrInfo.td"
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def PowerPCInstrInfo : InstrInfo {
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let PHIInst = PHI;
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let TSFlagsFields = ["ArgCount", "Arg0Type", "Arg1Type", "Arg2Type",
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"Arg3Type", "Arg4Type", "VMX", "PPC64"];
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let TSFlagsShifts = [ 0, 3, 8, 13, 18, 23, 28, 29 ];
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let TSFlagsFields = [ "VMX", "PPC64" ];
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let TSFlagsShifts = [ 0, 1 ];
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let isLittleEndianEncoding = 1;
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}
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@ -24,9 +24,8 @@ include "PowerPCInstrInfo.td"
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def PowerPCInstrInfo : InstrInfo {
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let PHIInst = PHI;
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let TSFlagsFields = ["ArgCount", "Arg0Type", "Arg1Type", "Arg2Type",
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"Arg3Type", "Arg4Type", "VMX", "PPC64"];
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let TSFlagsShifts = [ 0, 3, 8, 13, 18, 23, 28, 29 ];
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let TSFlagsFields = [ "VMX", "PPC64" ];
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let TSFlagsShifts = [ 0, 1 ];
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let isLittleEndianEncoding = 1;
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}
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@ -18,49 +18,38 @@
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#include "llvm/Target/TargetInstrInfo.h"
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namespace llvm {
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namespace PPCII {
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enum {
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ArgCountShift = 0,
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ArgCountMask = 7,
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Arg0TypeShift = 3,
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Arg1TypeShift = 8,
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Arg2TypeShift = 13,
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Arg3TypeShift = 18,
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Arg4TypeShift = 23,
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VMX = 1<<28,
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PPC64 = 1<<29,
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ArgTypeMask = 31
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};
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enum {
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None = 0,
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Gpr = 1,
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Gpr0 = 2,
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Simm16 = 3,
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Zimm16 = 4,
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PCRelimm24 = 5,
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Imm24 = 6,
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Imm5 = 7,
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PCRelimm14 = 8,
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Imm14 = 9,
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Imm2 = 10,
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Crf = 11,
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Imm3 = 12,
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Imm1 = 13,
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Fpr = 14,
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Imm4 = 15,
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Imm8 = 16,
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Disimm16 = 17,
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Disimm14 = 18,
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Spr = 19,
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Sgr = 20,
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Imm15 = 21,
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Vpr = 22
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};
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}
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namespace PPCII {
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enum {
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VMX = 1 << 0,
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PPC64 = 1 << 1,
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};
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enum {
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None = 0,
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Gpr = 1,
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Gpr0 = 2,
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Simm16 = 3,
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Zimm16 = 4,
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PCRelimm24 = 5,
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Imm24 = 6,
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Imm5 = 7,
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PCRelimm14 = 8,
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Imm14 = 9,
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Imm2 = 10,
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Crf = 11,
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Imm3 = 12,
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Imm1 = 13,
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Fpr = 14,
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Imm4 = 15,
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Imm8 = 16,
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Disimm16 = 17,
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Disimm14 = 18,
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Spr = 19,
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Sgr = 20,
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Imm15 = 21,
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Vpr = 22
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};
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}
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}
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#endif
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