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Get rid of flags that are dead

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18169 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-11-23 20:37:41 +00:00
parent 8f9e6d6ed2
commit 583e32b653
4 changed files with 38 additions and 52 deletions
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5
lib/Target/PowerPC/PPC32.td
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@ -24,9 +24,8 @@ include "PowerPCInstrInfo.td"
def PowerPCInstrInfo : InstrInfo { def PowerPCInstrInfo : InstrInfo {
let PHIInst = PHI; let PHIInst = PHI;
let TSFlagsFields = ["ArgCount", "Arg0Type", "Arg1Type", "Arg2Type", let TSFlagsFields = [ "VMX", "PPC64" ];
"Arg3Type", "Arg4Type", "VMX", "PPC64"]; let TSFlagsShifts = [ 0, 1 ];
let TSFlagsShifts = [ 0, 3, 8, 13, 18, 23, 28, 29 ];
let isLittleEndianEncoding = 1; let isLittleEndianEncoding = 1;
} }

5
lib/Target/PowerPC/PPC64.td
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@ -24,9 +24,8 @@ include "PowerPCInstrInfo.td"
def PowerPCInstrInfo : InstrInfo { def PowerPCInstrInfo : InstrInfo {
let PHIInst = PHI; let PHIInst = PHI;
let TSFlagsFields = ["ArgCount", "Arg0Type", "Arg1Type", "Arg2Type", let TSFlagsFields = [ "VMX", "PPC64" ];
"Arg3Type", "Arg4Type", "VMX", "PPC64"]; let TSFlagsShifts = [ 0, 1 ];
let TSFlagsShifts = [ 0, 3, 8, 13, 18, 23, 28, 29 ];
let isLittleEndianEncoding = 1; let isLittleEndianEncoding = 1;
} }

5
lib/Target/PowerPC/PowerPC.td
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@ -24,9 +24,8 @@ include "PowerPCInstrInfo.td"
def PowerPCInstrInfo : InstrInfo { def PowerPCInstrInfo : InstrInfo {
let PHIInst = PHI; let PHIInst = PHI;
let TSFlagsFields = ["ArgCount", "Arg0Type", "Arg1Type", "Arg2Type", let TSFlagsFields = [ "VMX", "PPC64" ];
"Arg3Type", "Arg4Type", "VMX", "PPC64"]; let TSFlagsShifts = [ 0, 1 ];
let TSFlagsShifts = [ 0, 3, 8, 13, 18, 23, 28, 29 ];
let isLittleEndianEncoding = 1; let isLittleEndianEncoding = 1;
} }

73
lib/Target/PowerPC/PowerPCInstrInfo.h
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@ -18,49 +18,38 @@
#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetInstrInfo.h"
namespace llvm { namespace llvm {
namespace PPCII {
enum {
VMX = 1 << 0,
PPC64 = 1 << 1,
};
namespace PPCII { enum {
enum { None = 0,
ArgCountShift = 0, Gpr = 1,
ArgCountMask = 7, Gpr0 = 2,
Simm16 = 3,
Arg0TypeShift = 3, Zimm16 = 4,
Arg1TypeShift = 8, PCRelimm24 = 5,
Arg2TypeShift = 13, Imm24 = 6,
Arg3TypeShift = 18, Imm5 = 7,
Arg4TypeShift = 23, PCRelimm14 = 8,
VMX = 1<<28, Imm14 = 9,
PPC64 = 1<<29, Imm2 = 10,
ArgTypeMask = 31 Crf = 11,
}; Imm3 = 12,
Imm1 = 13,
enum { Fpr = 14,
None = 0, Imm4 = 15,
Gpr = 1, Imm8 = 16,
Gpr0 = 2, Disimm16 = 17,
Simm16 = 3, Disimm14 = 18,
Zimm16 = 4, Spr = 19,
PCRelimm24 = 5, Sgr = 20,
Imm24 = 6, Imm15 = 21,
Imm5 = 7, Vpr = 22
PCRelimm14 = 8, };
Imm14 = 9, }
Imm2 = 10,
Crf = 11,
Imm3 = 12,
Imm1 = 13,
Fpr = 14,
Imm4 = 15,
Imm8 = 16,
Disimm16 = 17,
Disimm14 = 18,
Spr = 19,
Sgr = 20,
Imm15 = 21,
Vpr = 22
};
}
} }
#endif #endif