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initial implementation of ARMRegisterInfo::eliminateFrameIndex

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fixes test/Regression/CodeGen/ARM/ret_arg5.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28854 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2006-06-18 00:08:07 +00:00
parent 5cff2677a6
commit 58421d7d08
4 changed files with 34 additions and 3 deletions
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4
lib/Target/ARM/ARMInstrInfo.td
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@ -53,3 +53,7 @@ def movrr : InstARM<(ops IntRegs:$dst, IntRegs:$src),
def movri : InstARM<(ops IntRegs:$dst, i32imm:$src),
"mov $dst, $src", [(set IntRegs:$dst, imm:$src)]>;
def addri : InstARM<(ops IntRegs:$dst, IntRegs:$a, i32imm:$b),
"add $dst, $a, $b",
[(set IntRegs:$dst, (add IntRegs:$a, imm:$b))]>;

24
lib/Target/ARM/ARMRegisterInfo.cpp
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@ -77,7 +77,29 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
void
ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
assert(0 && "Not Implemented");
MachineInstr &MI = *II;
MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
assert (MI.getOpcode() == ARM::movrr);
unsigned FrameIdx = 1;
int FrameIndex = MI.getOperand(FrameIdx).getFrameIndex();
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
unsigned StackSize = MF.getFrameInfo()->getStackSize();
Offset += StackSize;
// Insert a set of r12 with the full address
// r12 = r13 + offset
MachineBasicBlock *MBB2 = MI.getParent();
BuildMI(*MBB2, II, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
// Replace the FrameIndex with r12
MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12);
}
void ARMRegisterInfo::

8
lib/Target/ARM/ARMRegisterInfo.td
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@ -50,7 +50,13 @@ def IntRegs : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
let MethodBodies = [{
IntRegsClass::iterator
IntRegsClass::allocation_order_end(MachineFunction &MF) const {
return end() - 1;
// r15 == Program Counter
// r14 == Link Register
// r13 == Stack Pointer
// r12 == ip (scratch)
// r11 == Frame Pointer
// r10 == Stack Limit
return end() - 4;
}
}];
}

1
test/CodeGen/ARM/ret_arg5.ll
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@ -1,5 +1,4 @@
; RUN: llvm-as < %s | llc -march=arm
; XFAIL: *
int %test(int %a1, int %a2, int %a3, int %a4, int %a5) {
ret int %a5
}